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dt-bindings: cache: l2c2x0: Add missing power-domains

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On Renesas SH-Mobile and R-Mobile SoCs, the ARM PL310 L2 Cache
Controller is located in a controllable power area.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Link: https://patch.msgid.link/0a57ab356e5f426e28ead373b809f88a63e55380.1781105151.git.geert+renesas@glider.be
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
This commit is contained in:
Geert Uytterhoeven
2026-06-10 17:29:20 +02:00
committed by Rob Herring (Arm)
parent 8e45719acd
commit f638ffe4db
1 changed files with 3 additions and 0 deletions
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3
Documentation/devicetree/bindings/cache/l2c2x0.yaml vendored
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@@ -66,6 +66,9 @@ properties:
reg:
maxItems: 1
power-domains:
maxItems: 1
arm,data-latency:
description: Cycles of latency for Data RAM accesses. Specifies 3 cells of
read, write and setup latencies. Minimum valid values are 1. Controllers