From f638ffe4dbafcd51df1f98fd659e5e672cc7e539 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 10 Jun 2026 17:29:20 +0200 Subject: [PATCH] dt-bindings: cache: l2c2x0: Add missing power-domains On Renesas SH-Mobile and R-Mobile SoCs, the ARM PL310 L2 Cache Controller is located in a controllable power area. Signed-off-by: Geert Uytterhoeven Acked-by: Krzysztof Kozlowski Link: https://patch.msgid.link/0a57ab356e5f426e28ead373b809f88a63e55380.1781105151.git.geert+renesas@glider.be Signed-off-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/cache/l2c2x0.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/cache/l2c2x0.yaml b/Documentation/devicetree/bindings/cache/l2c2x0.yaml index 10c1a900202f..ee604117ffb3 100644 --- a/Documentation/devicetree/bindings/cache/l2c2x0.yaml +++ b/Documentation/devicetree/bindings/cache/l2c2x0.yaml @@ -66,6 +66,9 @@ properties: reg: maxItems: 1 + power-domains: + maxItems: 1 + arm,data-latency: description: Cycles of latency for Data RAM accesses. Specifies 3 cells of read, write and setup latencies. Minimum valid values are 1. Controllers