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arm64: dts: qcom: kodiak: Move PCIe GPIOs and PHYs to root ports

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The Qualcomm PCIe binding deprecates perst-gpios and wake-gpios
on the host bridge and expects board reset and wake GPIOs to be
described on the root port. PERST# is described there as
reset-gpios.

Move the PCIe PHY references in kodiak.dtsi to the PCIe0 and PCIe1
root port nodes, and move the board-specific PCIe reset and wake
GPIOs in the Kodiak DTs to the corresponding root ports.

Keep the PHY and GPIO resources on the same root port nodes so the
Qualcomm PCIe driver can parse the root port binding instead of
falling back to the legacy host bridge GPIO parsing.

Signed-off-by: Hongyang Zhao <hongyang.zhao@thundersoft.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260607-rubikpi-bugfix-next-20260605-v2-1-7bf229978bcd@thundersoft.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Hongyang Zhao
2026-06-07 12:17:26 +08:00
committed by Bjorn Andersson
parent f212c011af
commit ea85f665ff
7 changed files with 47 additions and 32 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
arch/arm64/boot/dts/qcom/kodiak.dtsi
View File

@@ -2286,9 +2286,6 @@ pcie0: pcie@1c00000 {
power-domains = <&gcc GCC_PCIE_0_GDSC>;
phys = <&pcie0_phy>;
phy-names = "pciephy";
pinctrl-names = "default";
pinctrl-0 = <&pcie0_clkreq_n>;
dma-coherent;
@@ -2300,6 +2297,8 @@ pcie0_port: pcie@0 {
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
phys = <&pcie0_phy>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
@@ -2416,9 +2415,6 @@ pcie1: pcie@1c08000 {
power-domains = <&gcc GCC_PCIE_1_GDSC>;
phys = <&pcie1_phy>;
phy-names = "pciephy";
pinctrl-names = "default";
pinctrl-0 = <&pcie1_clkreq_n>;
@@ -2434,6 +2430,8 @@ pcie1_port0: pcie@0 {
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
phys = <&pcie1_phy>;
#address-cells = <3>;
#size-cells = <2>;
ranges;

14
arch/arm64/boot/dts/qcom/qcm6490-particle-tachyon.dts
View File

@@ -543,9 +543,6 @@ &mdss_dp_out {
};
&pcie0 {
perst-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 89 GPIO_ACTIVE_HIGH>;
pinctrl-0 = <&pcie0_reset_n>, <&pcie0_wake_n>, <&pcie0_clkreq_n>;
pinctrl-names = "default";
@@ -559,9 +556,12 @@ &pcie0_phy {
status = "okay";
};
&pcie1 {
perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
&pcie0_port {
reset-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 89 GPIO_ACTIVE_HIGH>;
};
&pcie1 {
pinctrl-0 = <&pcie1_reset_n>, <&pcie1_wake_n>, <&pcie1_clkreq_n>;
pinctrl-names = "default";
@@ -577,6 +577,10 @@ &pcie1_phy {
status = "okay";
};
&pcie1_port0 {
reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
};
&pmk8350_adc_tm {
status = "okay";

16
arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts
View File

@@ -526,9 +526,6 @@ &lpass_va_macro {
};
&pcie0 {
perst-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 89 GPIO_ACTIVE_HIGH>;
pinctrl-0 = <&pcie0_clkreq_n>, <&pcie0_reset_n>, <&pcie0_wake_n>;
pinctrl-names = "default";
@@ -542,10 +539,12 @@ &pcie0_phy {
status = "okay";
};
&pcie1 {
perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
&pcie0_port {
reset-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 89 GPIO_ACTIVE_HIGH>;
};
&pcie1 {
pinctrl-0 = <&pcie1_clkreq_n>, <&pcie1_reset_n>, <&pcie1_wake_n>;
pinctrl-names = "default";
@@ -570,6 +569,11 @@ &pcie1_phy {
status = "okay";
};
&pcie1_port0 {
reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
};
&pm7325_gpios {
pm7325_adc_default: adc-default-state {
pins = "gpio2";

4
arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
View File

@@ -841,8 +841,6 @@ &mdss_edp_phy {
};
&pcie1 {
perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
pinctrl-0 = <&pcie1_reset_n>, <&pcie1_wake_n>, <&pcie1_clkreq_n>;
pinctrl-names = "default";
@@ -867,6 +865,8 @@ &pcie1_phy {
};
&pcie1_port0 {
reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
pcie@0,0 {
compatible = "pci1179,0623";
reg = <0x10000 0x0 0x0 0x0 0x0>;

14
arch/arm64/boot/dts/qcom/qcs6490-thundercomm-minipc-g1iot.dts
View File

@@ -688,9 +688,6 @@ &mdss_dsi_phy {
};
&pcie0 {
perst-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 89 GPIO_ACTIVE_HIGH>;
pinctrl-0 = <&pcie0_clkreq_n>,
<&pcie0_reset_n>,
<&pcie0_wake_n>;
@@ -706,10 +703,12 @@ &pcie0_phy {
status = "okay";
};
&pcie1 {
perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
&pcie0_port {
reset-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 89 GPIO_ACTIVE_HIGH>;
};
&pcie1 {
pinctrl-0 = <&pcie1_clkreq_n>,
<&pcie1_reset_n>,
<&pcie1_wake_n>;
@@ -736,6 +735,9 @@ &pcie1_phy {
};
&pcie1_port0 {
reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>;
pcie@0,0 {
compatible = "pci1179,0623";
reg = <0x10000 0x0 0x0 0x0 0x0>;

16
arch/arm64/boot/dts/qcom/qcs6490-thundercomm-rubikpi3.dts
View File

@@ -816,9 +816,6 @@ &mdss_dsi_phy {
};
&pcie0 {
perst-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 89 GPIO_ACTIVE_HIGH>;
pinctrl-0 = <&pcie0_clkreq_n>,
<&pcie0_reset_n>,
<&pcie0_wake_n>;
@@ -834,10 +831,12 @@ &pcie0_phy {
status = "okay";
};
&pcie1 {
perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 3 GPIO_ACTIVE_LOW>;
&pcie0_port {
reset-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 89 GPIO_ACTIVE_HIGH>;
};
&pcie1 {
pinctrl-0 = <&pcie1_clkreq_n>,
<&pcie1_reset_n>,
<&pcie1_wake_n>;
@@ -853,6 +852,11 @@ &pcie1_phy {
status = "okay";
};
&pcie1_port0 {
reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 3 GPIO_ACTIVE_LOW>;
};
&pm7325_gpios {
kypd_vol_up_n: kypd-vol-up-n-state {
pins = "gpio6";

5
arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
View File

@@ -418,7 +418,6 @@ &lpass_va_macro {
&pcie1 {
status = "okay";
perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
vddpe-3v3-supply = <&nvme_3v3_regulator>;
@@ -433,6 +432,10 @@ &pcie1_phy {
vdda-pll-supply = <&vreg_l6b_1p2>;
};
&pcie1_port0 {
reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>;
};
&pmk8350_vadc {
channel@3 {
reg = <PMK8350_ADC7_DIE_TEMP>;