From ea85f665ffa09e2b7b9b54dac50dbaf0cd88685c Mon Sep 17 00:00:00 2001 From: Hongyang Zhao Date: Sun, 7 Jun 2026 12:17:26 +0800 Subject: [PATCH] arm64: dts: qcom: kodiak: Move PCIe GPIOs and PHYs to root ports The Qualcomm PCIe binding deprecates perst-gpios and wake-gpios on the host bridge and expects board reset and wake GPIOs to be described on the root port. PERST# is described there as reset-gpios. Move the PCIe PHY references in kodiak.dtsi to the PCIe0 and PCIe1 root port nodes, and move the board-specific PCIe reset and wake GPIOs in the Kodiak DTs to the corresponding root ports. Keep the PHY and GPIO resources on the same root port nodes so the Qualcomm PCIe driver can parse the root port binding instead of falling back to the legacy host bridge GPIO parsing. Signed-off-by: Hongyang Zhao Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260607-rubikpi-bugfix-next-20260605-v2-1-7bf229978bcd@thundersoft.com Signed-off-by: Bjorn Andersson --- arch/arm64/boot/dts/qcom/kodiak.dtsi | 10 ++++------ .../boot/dts/qcom/qcm6490-particle-tachyon.dts | 14 +++++++++----- .../boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts | 16 ++++++++++------ arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 4 ++-- .../qcom/qcs6490-thundercomm-minipc-g1iot.dts | 14 ++++++++------ .../dts/qcom/qcs6490-thundercomm-rubikpi3.dts | 16 ++++++++++------ arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 5 ++++- 7 files changed, 47 insertions(+), 32 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/kodiak.dtsi b/arch/arm64/boot/dts/qcom/kodiak.dtsi index 90e50c245c0c..b951dd682543 100644 --- a/arch/arm64/boot/dts/qcom/kodiak.dtsi +++ b/arch/arm64/boot/dts/qcom/kodiak.dtsi @@ -2286,9 +2286,6 @@ pcie0: pcie@1c00000 { power-domains = <&gcc GCC_PCIE_0_GDSC>; - phys = <&pcie0_phy>; - phy-names = "pciephy"; - pinctrl-names = "default"; pinctrl-0 = <&pcie0_clkreq_n>; dma-coherent; @@ -2300,6 +2297,8 @@ pcie0_port: pcie@0 { reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; + phys = <&pcie0_phy>; + #address-cells = <3>; #size-cells = <2>; ranges; @@ -2416,9 +2415,6 @@ pcie1: pcie@1c08000 { power-domains = <&gcc GCC_PCIE_1_GDSC>; - phys = <&pcie1_phy>; - phy-names = "pciephy"; - pinctrl-names = "default"; pinctrl-0 = <&pcie1_clkreq_n>; @@ -2434,6 +2430,8 @@ pcie1_port0: pcie@0 { reg = <0x0 0x0 0x0 0x0 0x0>; bus-range = <0x01 0xff>; + phys = <&pcie1_phy>; + #address-cells = <3>; #size-cells = <2>; ranges; diff --git a/arch/arm64/boot/dts/qcom/qcm6490-particle-tachyon.dts b/arch/arm64/boot/dts/qcom/qcm6490-particle-tachyon.dts index fef9fb51642d..94eebb7de7b9 100644 --- a/arch/arm64/boot/dts/qcom/qcm6490-particle-tachyon.dts +++ b/arch/arm64/boot/dts/qcom/qcm6490-particle-tachyon.dts @@ -543,9 +543,6 @@ &mdss_dp_out { }; &pcie0 { - perst-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 89 GPIO_ACTIVE_HIGH>; - pinctrl-0 = <&pcie0_reset_n>, <&pcie0_wake_n>, <&pcie0_clkreq_n>; pinctrl-names = "default"; @@ -559,9 +556,12 @@ &pcie0_phy { status = "okay"; }; -&pcie1 { - perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; +&pcie0_port { + reset-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 89 GPIO_ACTIVE_HIGH>; +}; +&pcie1 { pinctrl-0 = <&pcie1_reset_n>, <&pcie1_wake_n>, <&pcie1_clkreq_n>; pinctrl-names = "default"; @@ -577,6 +577,10 @@ &pcie1_phy { status = "okay"; }; +&pcie1_port0 { + reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; +}; + &pmk8350_adc_tm { status = "okay"; diff --git a/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts b/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts index 6c1a73f18ec1..82ebd88f9aba 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts +++ b/arch/arm64/boot/dts/qcom/qcs6490-radxa-dragon-q6a.dts @@ -526,9 +526,6 @@ &lpass_va_macro { }; &pcie0 { - perst-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 89 GPIO_ACTIVE_HIGH>; - pinctrl-0 = <&pcie0_clkreq_n>, <&pcie0_reset_n>, <&pcie0_wake_n>; pinctrl-names = "default"; @@ -542,10 +539,12 @@ &pcie0_phy { status = "okay"; }; -&pcie1 { - perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>; +&pcie0_port { + reset-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 89 GPIO_ACTIVE_HIGH>; +}; +&pcie1 { pinctrl-0 = <&pcie1_clkreq_n>, <&pcie1_reset_n>, <&pcie1_wake_n>; pinctrl-names = "default"; @@ -570,6 +569,11 @@ &pcie1_phy { status = "okay"; }; +&pcie1_port0 { + reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>; +}; + &pm7325_gpios { pm7325_adc_default: adc-default-state { pins = "gpio2"; diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts index 9c24802e476e..e9a932c90d14 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts @@ -841,8 +841,6 @@ &mdss_edp_phy { }; &pcie1 { - perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&pcie1_reset_n>, <&pcie1_wake_n>, <&pcie1_clkreq_n>; pinctrl-names = "default"; @@ -867,6 +865,8 @@ &pcie1_phy { }; &pcie1_port0 { + reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; + pcie@0,0 { compatible = "pci1179,0623"; reg = <0x10000 0x0 0x0 0x0 0x0>; diff --git a/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-minipc-g1iot.dts b/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-minipc-g1iot.dts index 7de63ee37a84..c8eed8ba93f5 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-minipc-g1iot.dts +++ b/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-minipc-g1iot.dts @@ -688,9 +688,6 @@ &mdss_dsi_phy { }; &pcie0 { - perst-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 89 GPIO_ACTIVE_HIGH>; - pinctrl-0 = <&pcie0_clkreq_n>, <&pcie0_reset_n>, <&pcie0_wake_n>; @@ -706,10 +703,12 @@ &pcie0_phy { status = "okay"; }; -&pcie1 { - perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>; +&pcie0_port { + reset-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 89 GPIO_ACTIVE_HIGH>; +}; +&pcie1 { pinctrl-0 = <&pcie1_clkreq_n>, <&pcie1_reset_n>, <&pcie1_wake_n>; @@ -736,6 +735,9 @@ &pcie1_phy { }; &pcie1_port0 { + reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 3 GPIO_ACTIVE_HIGH>; + pcie@0,0 { compatible = "pci1179,0623"; reg = <0x10000 0x0 0x0 0x0 0x0>; diff --git a/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-rubikpi3.dts b/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-rubikpi3.dts index e701cc39210f..d8a9a7e47bdc 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-rubikpi3.dts +++ b/arch/arm64/boot/dts/qcom/qcs6490-thundercomm-rubikpi3.dts @@ -816,9 +816,6 @@ &mdss_dsi_phy { }; &pcie0 { - perst-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 89 GPIO_ACTIVE_HIGH>; - pinctrl-0 = <&pcie0_clkreq_n>, <&pcie0_reset_n>, <&pcie0_wake_n>; @@ -834,10 +831,12 @@ &pcie0_phy { status = "okay"; }; -&pcie1 { - perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; - wake-gpios = <&tlmm 3 GPIO_ACTIVE_LOW>; +&pcie0_port { + reset-gpios = <&tlmm 87 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 89 GPIO_ACTIVE_HIGH>; +}; +&pcie1 { pinctrl-0 = <&pcie1_clkreq_n>, <&pcie1_reset_n>, <&pcie1_wake_n>; @@ -853,6 +852,11 @@ &pcie1_phy { status = "okay"; }; +&pcie1_port0 { + reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 3 GPIO_ACTIVE_LOW>; +}; + &pm7325_gpios { kypd_vol_up_n: kypd-vol-up-n-state { pins = "gpio6"; diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi index 8cac4ce9c851..6bb806931b79 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi @@ -418,7 +418,6 @@ &lpass_va_macro { &pcie1 { status = "okay"; - perst-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; vddpe-3v3-supply = <&nvme_3v3_regulator>; @@ -433,6 +432,10 @@ &pcie1_phy { vdda-pll-supply = <&vreg_l6b_1p2>; }; +&pcie1_port0 { + reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; +}; + &pmk8350_vadc { channel@3 { reg = ;