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synced 2026-05-02 13:23:35 -04:00
drm/amd/display: hook up DCN20 color blocks data to DTN log
Color caps changed between HW versions, which caused the DCN10 color state sections in the DTN log to no longer match DCN2+ state. Create a color state log specific to DCN2.0 and hook it up to DCN2 family drivers. Instead of reading gamut remap reg values, display gamut remap matrix data in fixed 31.32. Signed-off-by: Melissa Wen <mwen@igalia.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Melissa Wen
committed by
Alex Deucher
Alex Deucher
parent
f5be15bb26
commit
e432f14a42
@@ -55,21 +55,23 @@ void dpp20_read_state(struct dpp *dpp_base,
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REG_GET(DPP_CONTROL,
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DPP_CLOCK_ENABLE, &s->is_enabled);
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// Degamma LUT (RAM)
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REG_GET(CM_DGAM_CONTROL,
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CM_DGAM_LUT_MODE, &s->dgam_lut_mode);
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// BGAM has no ROM, and definition is different, can't reuse same dump
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//REG_GET(CM_BLNDGAM_CONTROL,
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// CM_BLNDGAM_LUT_MODE, &s->rgam_lut_mode);
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REG_GET(CM_GAMUT_REMAP_CONTROL,
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CM_GAMUT_REMAP_MODE, &s->gamut_remap_mode);
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if (s->gamut_remap_mode) {
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s->gamut_remap_c11_c12 = REG_READ(CM_GAMUT_REMAP_C11_C12);
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s->gamut_remap_c13_c14 = REG_READ(CM_GAMUT_REMAP_C13_C14);
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s->gamut_remap_c21_c22 = REG_READ(CM_GAMUT_REMAP_C21_C22);
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s->gamut_remap_c23_c24 = REG_READ(CM_GAMUT_REMAP_C23_C24);
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s->gamut_remap_c31_c32 = REG_READ(CM_GAMUT_REMAP_C31_C32);
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s->gamut_remap_c33_c34 = REG_READ(CM_GAMUT_REMAP_C33_C34);
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}
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CM_DGAM_LUT_MODE, &s->dgam_lut_mode);
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// Shaper LUT (RAM), 3D LUT (mode, bit-depth, size)
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REG_GET(CM_SHAPER_CONTROL,
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CM_SHAPER_LUT_MODE, &s->shaper_lut_mode);
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REG_GET_2(CM_3DLUT_READ_WRITE_CONTROL,
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CM_3DLUT_CONFIG_STATUS, &s->lut3d_mode,
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CM_3DLUT_30BIT_EN, &s->lut3d_bit_depth);
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REG_GET(CM_3DLUT_MODE,
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CM_3DLUT_SIZE, &s->lut3d_size);
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// Blend/Out Gamma (RAM)
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REG_GET(CM_BLNDGAM_LUT_WRITE_EN_MASK,
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CM_BLNDGAM_CONFIG_STATUS, &s->rgam_lut_mode);
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}
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void dpp2_power_on_obuf(
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@@ -542,8 +542,30 @@ static struct mpcc *mpc2_get_mpcc_for_dpp(struct mpc_tree *tree, int dpp_id)
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return NULL;
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}
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static void mpc2_read_mpcc_state(
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struct mpc *mpc,
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int mpcc_inst,
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struct mpcc_state *s)
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{
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struct dcn20_mpc *mpc20 = TO_DCN20_MPC(mpc);
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REG_GET(MPCC_OPP_ID[mpcc_inst], MPCC_OPP_ID, &s->opp_id);
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REG_GET(MPCC_TOP_SEL[mpcc_inst], MPCC_TOP_SEL, &s->dpp_id);
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REG_GET(MPCC_BOT_SEL[mpcc_inst], MPCC_BOT_SEL, &s->bot_mpcc_id);
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REG_GET_4(MPCC_CONTROL[mpcc_inst], MPCC_MODE, &s->mode,
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MPCC_ALPHA_BLND_MODE, &s->alpha_mode,
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MPCC_ALPHA_MULTIPLIED_MODE, &s->pre_multiplied_alpha,
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MPCC_BLND_ACTIVE_OVERLAP_ONLY, &s->overlap_only);
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REG_GET_2(MPCC_STATUS[mpcc_inst], MPCC_IDLE, &s->idle,
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MPCC_BUSY, &s->busy);
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/* Gamma block state */
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REG_GET(MPCC_OGAM_LUT_RAM_CONTROL[mpcc_inst],
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MPCC_OGAM_CONFIG_STATUS, &s->rgam_mode);
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}
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static const struct mpc_funcs dcn20_mpc_funcs = {
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.read_mpcc_state = mpc1_read_mpcc_state,
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.read_mpcc_state = mpc2_read_mpcc_state,
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.insert_plane = mpc1_insert_plane,
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.remove_mpcc = mpc1_remove_mpcc,
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.mpc_init = mpc1_mpc_init,
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@@ -71,6 +71,112 @@
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#define FN(reg_name, field_name) \
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hws->shifts->field_name, hws->masks->field_name
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void dcn20_log_color_state(struct dc *dc,
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struct dc_log_buffer_ctx *log_ctx)
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{
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struct dc_context *dc_ctx = dc->ctx;
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struct resource_pool *pool = dc->res_pool;
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int i;
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DTN_INFO("DPP: DGAM mode SHAPER mode 3DLUT mode 3DLUT bit depth"
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" 3DLUT size RGAM mode GAMUT adjust "
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"C11 C12 C13 C14 "
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"C21 C22 C23 C24 "
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"C31 C32 C33 C34 \n");
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for (i = 0; i < pool->pipe_count; i++) {
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struct dpp *dpp = pool->dpps[i];
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struct dcn_dpp_state s = {0};
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dpp->funcs->dpp_read_state(dpp, &s);
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dpp->funcs->dpp_get_gamut_remap(dpp, &s.gamut_remap);
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if (!s.is_enabled)
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continue;
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DTN_INFO("[%2d]: %8s %11s %10s %15s %10s %9s %12s "
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"%010lld %010lld %010lld %010lld "
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"%010lld %010lld %010lld %010lld "
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"%010lld %010lld %010lld %010lld",
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dpp->inst,
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(s.dgam_lut_mode == 0) ? "Bypass" :
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((s.dgam_lut_mode == 1) ? "sRGB" :
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((s.dgam_lut_mode == 2) ? "Ycc" :
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((s.dgam_lut_mode == 3) ? "RAM" :
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((s.dgam_lut_mode == 4) ? "RAM" :
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"Unknown")))),
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(s.shaper_lut_mode == 1) ? "RAM A" :
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((s.shaper_lut_mode == 2) ? "RAM B" :
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"Bypass"),
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(s.lut3d_mode == 1) ? "RAM A" :
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((s.lut3d_mode == 2) ? "RAM B" :
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"Bypass"),
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(s.lut3d_bit_depth <= 0) ? "12-bit" : "10-bit",
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(s.lut3d_size == 0) ? "17x17x17" : "9x9x9",
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(s.rgam_lut_mode == 1) ? "RAM A" :
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((s.rgam_lut_mode == 1) ? "RAM B" : "Bypass"),
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(s.gamut_remap.gamut_adjust_type == 0) ? "Bypass" :
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((s.gamut_remap.gamut_adjust_type == 1) ? "HW" :
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"SW"),
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s.gamut_remap.temperature_matrix[0].value,
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s.gamut_remap.temperature_matrix[1].value,
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s.gamut_remap.temperature_matrix[2].value,
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s.gamut_remap.temperature_matrix[3].value,
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s.gamut_remap.temperature_matrix[4].value,
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s.gamut_remap.temperature_matrix[5].value,
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s.gamut_remap.temperature_matrix[6].value,
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s.gamut_remap.temperature_matrix[7].value,
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s.gamut_remap.temperature_matrix[8].value,
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s.gamut_remap.temperature_matrix[9].value,
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s.gamut_remap.temperature_matrix[10].value,
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s.gamut_remap.temperature_matrix[11].value);
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DTN_INFO("\n");
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}
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DTN_INFO("\n");
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DTN_INFO("DPP Color Caps: input_lut_shared:%d icsc:%d"
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" dgam_ram:%d dgam_rom: srgb:%d,bt2020:%d,gamma2_2:%d,pq:%d,hlg:%d"
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" post_csc:%d gamcor:%d dgam_rom_for_yuv:%d 3d_lut:%d"
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" blnd_lut:%d oscs:%d\n\n",
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dc->caps.color.dpp.input_lut_shared,
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dc->caps.color.dpp.icsc,
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dc->caps.color.dpp.dgam_ram,
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dc->caps.color.dpp.dgam_rom_caps.srgb,
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dc->caps.color.dpp.dgam_rom_caps.bt2020,
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dc->caps.color.dpp.dgam_rom_caps.gamma2_2,
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dc->caps.color.dpp.dgam_rom_caps.pq,
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dc->caps.color.dpp.dgam_rom_caps.hlg,
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dc->caps.color.dpp.post_csc,
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dc->caps.color.dpp.gamma_corr,
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dc->caps.color.dpp.dgam_rom_for_yuv,
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dc->caps.color.dpp.hw_3d_lut,
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dc->caps.color.dpp.ogam_ram,
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dc->caps.color.dpp.ocsc);
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DTN_INFO("MPCC: OPP DPP MPCCBOT MODE ALPHA_MODE PREMULT OVERLAP_ONLY IDLE"
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" OGAM mode\n");
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for (i = 0; i < pool->pipe_count; i++) {
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struct mpcc_state s = {0};
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pool->mpc->funcs->read_mpcc_state(pool->mpc, i, &s);
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if (s.opp_id != 0xf)
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DTN_INFO("[%2d]: %2xh %2xh %6xh %4d %10d %7d %12d %4d %9s\n",
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i, s.opp_id, s.dpp_id, s.bot_mpcc_id,
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s.mode, s.alpha_mode, s.pre_multiplied_alpha, s.overlap_only,
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s.idle,
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(s.rgam_mode == 1) ? "RAM A" :
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((s.rgam_mode == 2) ? "RAM B" :
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"Bypass"));
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}
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DTN_INFO("\n");
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DTN_INFO("MPC Color Caps: gamut_remap:%d, 3dlut:%d, ogam_ram:%d, ocsc:%d\n\n",
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dc->caps.color.mpc.gamut_remap,
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dc->caps.color.mpc.num_3dluts,
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dc->caps.color.mpc.ogam_ram,
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dc->caps.color.mpc.ocsc);
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}
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static int find_free_gsl_group(const struct dc *dc)
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{
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if (dc->res_pool->gsl_groups.gsl_0 == 0)
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@@ -28,6 +28,8 @@
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#include "hw_sequencer_private.h"
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void dcn20_log_color_state(struct dc *dc,
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struct dc_log_buffer_ctx *log_ctx);
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bool dcn20_set_blend_lut(
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struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state);
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bool dcn20_set_shaper_3dlut(
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