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drm/amd/display: add DPP and MPC color caps to DTN log

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Add color caps information for DPP and MPC block to show HW color caps.

Signed-off-by: Melissa Wen <mwen@igalia.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Melissa Wen
2023-11-28 16:52:56 -01:00
committed by Alex Deucher
parent 8feca9f32c
commit f5be15bb26
2 changed files with 46 additions and 0 deletions
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23
drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
View File

@@ -347,6 +347,24 @@ static void dcn10_log_color_state(struct dc *dc,
DTN_INFO("\n");
}
DTN_INFO("\n");
DTN_INFO("DPP Color Caps: input_lut_shared:%d icsc:%d"
" dgam_ram:%d dgam_rom: srgb:%d,bt2020:%d,gamma2_2:%d,pq:%d,hlg:%d"
" post_csc:%d gamcor:%d dgam_rom_for_yuv:%d 3d_lut:%d"
" blnd_lut:%d oscs:%d\n\n",
dc->caps.color.dpp.input_lut_shared,
dc->caps.color.dpp.icsc,
dc->caps.color.dpp.dgam_ram,
dc->caps.color.dpp.dgam_rom_caps.srgb,
dc->caps.color.dpp.dgam_rom_caps.bt2020,
dc->caps.color.dpp.dgam_rom_caps.gamma2_2,
dc->caps.color.dpp.dgam_rom_caps.pq,
dc->caps.color.dpp.dgam_rom_caps.hlg,
dc->caps.color.dpp.post_csc,
dc->caps.color.dpp.gamma_corr,
dc->caps.color.dpp.dgam_rom_for_yuv,
dc->caps.color.dpp.hw_3d_lut,
dc->caps.color.dpp.ogam_ram,
dc->caps.color.dpp.ocsc);
DTN_INFO("MPCC: OPP DPP MPCCBOT MODE ALPHA_MODE PREMULT OVERLAP_ONLY IDLE\n");
for (i = 0; i < pool->pipe_count; i++) {
@@ -360,6 +378,11 @@ static void dcn10_log_color_state(struct dc *dc,
s.idle);
}
DTN_INFO("\n");
DTN_INFO("MPC Color Caps: gamut_remap:%d, 3dlut:%d, ogam_ram:%d, ocsc:%d\n\n",
dc->caps.color.mpc.gamut_remap,
dc->caps.color.mpc.num_3dluts,
dc->caps.color.mpc.ogam_ram,
dc->caps.color.mpc.ocsc);
}
void dcn10_log_hw_state(struct dc *dc,

23
drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
View File

@@ -140,6 +140,24 @@ void dcn30_log_color_state(struct dc *dc,
DTN_INFO("\n");
}
DTN_INFO("\n");
DTN_INFO("DPP Color Caps: input_lut_shared:%d icsc:%d"
" dgam_ram:%d dgam_rom: srgb:%d,bt2020:%d,gamma2_2:%d,pq:%d,hlg:%d"
" post_csc:%d gamcor:%d dgam_rom_for_yuv:%d 3d_lut:%d"
" blnd_lut:%d oscs:%d\n\n",
dc->caps.color.dpp.input_lut_shared,
dc->caps.color.dpp.icsc,
dc->caps.color.dpp.dgam_ram,
dc->caps.color.dpp.dgam_rom_caps.srgb,
dc->caps.color.dpp.dgam_rom_caps.bt2020,
dc->caps.color.dpp.dgam_rom_caps.gamma2_2,
dc->caps.color.dpp.dgam_rom_caps.pq,
dc->caps.color.dpp.dgam_rom_caps.hlg,
dc->caps.color.dpp.post_csc,
dc->caps.color.dpp.gamma_corr,
dc->caps.color.dpp.dgam_rom_for_yuv,
dc->caps.color.dpp.hw_3d_lut,
dc->caps.color.dpp.ogam_ram,
dc->caps.color.dpp.ocsc);
DTN_INFO("MPCC: OPP DPP MPCCBOT MODE ALPHA_MODE PREMULT OVERLAP_ONLY IDLE"
" SHAPER mode 3DLUT mode 3DLUT bit-depth 3DLUT size OGAM mode OGAM LUT"
@@ -193,6 +211,11 @@ void dcn30_log_color_state(struct dc *dc,
}
DTN_INFO("\n");
DTN_INFO("MPC Color Caps: gamut_remap:%d, 3dlut:%d, ogam_ram:%d, ocsc:%d\n\n",
dc->caps.color.mpc.gamut_remap,
dc->caps.color.mpc.num_3dluts,
dc->caps.color.mpc.ogam_ram,
dc->caps.color.mpc.ocsc);
}
bool dcn30_set_blend_lut(