mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
synced 2026-07-21 21:38:04 -04:00
Merge branches 'clk-renesas', 'clk-socfpga', 'clk-amlogic' and 'clk-canaan' into clk-next
* clk-renesas: (36 commits)
clk: renesas: r9a08g045: Drop unused pm_domain header file
clk: renesas: r8a779g0: Add DSC clock
clk: renesas: rzg2l: Rename iterator in for_each_mod_clock() to avoid shadowing
clk: renesas: r9a08g045: Drop unused DEF_G3S_MUX macro
clk: renesas: rzg2l: Rename RZG3L-prefixed PLL macros to CPG-prefixed ones
clk: renesas: rzg3s/rzg3l: Simplify PLL configuration macro
clk: renesas: rzg2l: Simplify SAM PLL configuration macro
clk: renesas: r8a73a4: Add ZT/ZTR trace clocks
dt-bindings: clock: renesas,cpg-clocks: Document ZT/ZTR trace clock on R-Mobile APE6
clk: renesas: r9a08g046: Add RSPI clocks and resets
clk: renesas: r9a08g046: Add SSIF-2 clocks and resets
clk: renesas: r9a08g046: Add RSCI clocks and resets
clk: renesas: cpg-mssr: Add number of clock cells check
clk: renesas: rzg2l: Refactor rzg3l_cpg_pll_clk_endisable()
clk: renesas: rzg2l: Consolidate DEF_MUX() and DEF_MUX_FLAGS()
clk: renesas: r9a08g046: Add IA55_PCLK to critical module clocks
clk: renesas: r9a09g047: Add support for LCDC{0,1} clocks and resets
clk: renesas: r9a09g047: Add support for DSI clocks and resets
clk: renesas: r9a09g047: Add support for SMUX2_DSI{0,1}_CLK
clk: renesas: r9a09g047: Add CLK_PLLDSI{0,1}_CSDIV clocks
...
* clk-socfpga:
clk: socfpga: agilex: implement l3_main_free_clk
* clk-amlogic:
dt-bindings: clock: amlogic: t7: Add missing mpll3 parent clock
dt-bindings: clock: amlogic: Fix redundant hyphen in "amlogic,t7-gp1--pll" string.
* clk-canaan:
clk: canaan: Add clock driver for Canaan K230
dt-bindings: clock: Add Canaan K230 clock controller
This commit is contained in:
Stephen Boyd
@@ -24,7 +24,7 @@ properties:
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const: 1
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clocks:
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minItems: 14
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minItems: 15
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items:
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- description: input oscillator
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- description: input sys clk
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@@ -40,12 +40,13 @@ properties:
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- description: input gp1 pll
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- description: input mpll1
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- description: input mpll2
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- description: input mpll3
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- description: external input rmii oscillator (optional)
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- description: input video pll0 (optional)
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- description: external pad input for rtc (optional)
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clock-names:
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minItems: 14
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minItems: 15
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items:
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- const: xtal
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- const: sys
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@@ -61,6 +62,7 @@ properties:
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- const: gp1
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- const: mpll1
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- const: mpll2
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- const: mpll3
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- const: ext_rmii
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- const: vid_pll0
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- const: ext_rtc
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@@ -97,7 +99,8 @@ examples:
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<&gp0 1>,
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<&gp1 1>,
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<&mpll 4>,
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<&mpll 6>;
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<&mpll 6>,
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<&mpll 8>;
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clock-names = "xtal",
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"sys",
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"fix",
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@@ -111,6 +114,7 @@ examples:
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"gp0",
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"gp1",
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"mpll1",
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"mpll2";
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"mpll2",
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"mpll3";
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};
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};
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@@ -72,7 +72,7 @@ allOf:
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contains:
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enum:
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- amlogic,t7-gp0-pll
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- amlogic,t7-gp1--pll
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- amlogic,t7-gp1-pll
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- amlogic,t7-hifi-pll
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- amlogic,t7-pcie-pll
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- amlogic,t7-mpll
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59
Documentation/devicetree/bindings/clock/canaan,k230-clk.yaml
Normal file
59
Documentation/devicetree/bindings/clock/canaan,k230-clk.yaml
Normal file
@@ -0,0 +1,59 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/canaan,k230-clk.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Canaan Kendryte K230 Clock
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maintainers:
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- Xukai Wang <kingxukai@zohomail.com>
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description:
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The Canaan K230 clock controller generates various clocks for SoC
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peripherals. See include/dt-bindings/clock/canaan,k230-clk.h for
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valid clock IDs.
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properties:
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compatible:
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const: canaan,k230-clk
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reg:
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items:
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- description: PLL control registers
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- description: Sysclk control registers
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clocks:
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items:
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- description: Main external reference clock
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- description:
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External clock which used as the pulse input
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for the timer to provide timing signals.
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clock-names:
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items:
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- const: osc24m
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- const: timer-pulse-in
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'#clock-cells':
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const: 1
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- '#clock-cells'
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additionalProperties: false
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examples:
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- |
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clock-controller@91102000 {
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compatible = "canaan,k230-clk";
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reg = <0x91102000 0x40>,
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<0x91100000 0x108>;
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clocks = <&osc24m>, <&timerx_pulse_in>;
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clock-names = "osc24m", "timer-pulse-in";
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#clock-cells = <1>;
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};
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@@ -41,7 +41,7 @@ properties:
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clock-output-names:
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minItems: 3
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maxItems: 17
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maxItems: 19
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renesas,mode:
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description: Board-specific settings of the MD_CK* bits on R-Mobile A1
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@@ -90,6 +90,8 @@ allOf:
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- const: zx
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- const: zs
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- const: hp
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- const: ztr
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- const: zt
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- if:
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properties:
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@@ -123,6 +125,8 @@ allOf:
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- const: zb
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- const: m3
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- const: cp
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- const: ztr
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- const: zt
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required:
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- renesas,mode
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@@ -240,6 +244,6 @@ examples:
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#clock-cells = <1>;
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clock-output-names = "system", "pllc0", "pllc1", "pllc2", "r",
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"usb24s", "i", "zg", "b", "m1", "hp", "hpp",
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"usbp", "s", "zb", "m3", "cp";
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"usbp", "s", "zb", "m3", "cp", "ztr", "zt";
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renesas,mode = <0x05>;
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};
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@@ -480,6 +480,12 @@ config COMMON_CLK_K210
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help
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Support for the Canaan Kendryte K210 RISC-V SoC clocks.
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config COMMON_CLK_K230
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bool "Clock driver for the Canaan Kendryte K230 SoC"
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depends on ARCH_CANAAN || COMPILE_TEST
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help
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Support for the Canaan Kendryte K230 RISC-V SoC clocks.
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config COMMON_CLK_SP7021
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tristate "Clock driver for Sunplus SP7021 SoC"
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depends on SOC_SP7021 || COMPILE_TEST
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@@ -65,6 +65,7 @@ obj-$(CONFIG_COMMON_CLK_GEMINI) += clk-gemini.o
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obj-$(CONFIG_ARCH_HIGHBANK) += clk-highbank.o
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obj-$(CONFIG_CLK_HSDK) += clk-hsdk-pll.o
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obj-$(CONFIG_COMMON_CLK_K210) += clk-k210.o
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obj-$(CONFIG_COMMON_CLK_K230) += clk-k230.o
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obj-$(CONFIG_LMK04832) += clk-lmk04832.o
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obj-$(CONFIG_COMMON_CLK_LAN966X) += clk-lan966x.o
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obj-$(CONFIG_COMMON_CLK_LOCHNAGAR) += clk-lochnagar.o
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2452
drivers/clk/clk-k230.c
Normal file
2452
drivers/clk/clk-k230.c
Normal file
File diff suppressed because it is too large
Load Diff
@@ -42,6 +42,8 @@ static struct div4_clk div4_clks[] = {
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{ "b", CPG_FRQCRA, 8 },
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{ "m1", CPG_FRQCRA, 4 },
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{ "m2", CPG_FRQCRA, 0 },
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{ "ztr", CPG_FRQCRB, 20 },
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{ "zt", CPG_FRQCRB, 16 },
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{ "zx", CPG_FRQCRB, 12 },
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{ "zs", CPG_FRQCRB, 8 },
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{ "hp", CPG_FRQCRB, 4 },
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@@ -37,6 +37,8 @@ static struct div4_clk div4_clks[] = {
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{ "zg", CPG_FRQCRA, 16 },
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{ "b", CPG_FRQCRA, 8 },
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{ "m1", CPG_FRQCRA, 4 },
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{ "ztr", CPG_FRQCRB, 20 },
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{ "zt", CPG_FRQCRB, 16 },
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{ "hp", CPG_FRQCRB, 4 },
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{ "hpp", CPG_FRQCRC, 20 },
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{ "usbp", CPG_FRQCRC, 16 },
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@@ -245,6 +245,7 @@ static const struct mssr_mod_clk r8a779g0_mod_clks[] __initconst = {
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DEF_MOD("fcpvx0", 1100, R8A779G0_CLK_S0D1_VIO),
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DEF_MOD("fcpvx1", 1101, R8A779G0_CLK_S0D1_VIO),
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DEF_MOD("tsn", 2723, R8A779G0_CLK_S0D4_HSC),
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DEF_MOD("dsc", 2819, R8A779G0_CLK_VIOBUSD2),
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DEF_MOD("ssiu", 2926, R8A779G0_CLK_S0D6_PER),
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DEF_MOD("ssi", 2927, R8A779G0_CLK_S0D6_PER),
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};
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@@ -103,7 +103,7 @@ static const struct cpg_core_clk r9a07g043_core_clks[] __initconst = {
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/* Internal Core Clocks */
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DEF_FIXED(".osc", R9A07G043_OSCCLK, CLK_EXTAL, 1, 1),
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DEF_FIXED(".osc_div1000", CLK_OSC_DIV1000, CLK_EXTAL, 1, 1000),
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DEF_SAMPLL(".pll1", CLK_PLL1, CLK_EXTAL, PLL146_CONF(0)),
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DEF_SAMPLL(".pll1", CLK_PLL1, CLK_EXTAL, CPG_SAM_PLL_CONF(0)),
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DEF_FIXED(".pll2", CLK_PLL2, CLK_EXTAL, 200, 3),
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DEF_FIXED(".pll2_div2", CLK_PLL2_DIV2, CLK_PLL2, 1, 2),
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DEF_FIXED(".clk_800", CLK_PLL2_800, CLK_PLL2, 1, 2),
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@@ -159,7 +159,7 @@ static const struct {
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/* Internal Core Clocks */
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DEF_FIXED(".osc", R9A07G044_OSCCLK, CLK_EXTAL, 1, 1),
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DEF_FIXED(".osc_div1000", CLK_OSC_DIV1000, CLK_EXTAL, 1, 1000),
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DEF_SAMPLL(".pll1", CLK_PLL1, CLK_EXTAL, PLL146_CONF(0)),
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DEF_SAMPLL(".pll1", CLK_PLL1, CLK_EXTAL, CPG_SAM_PLL_CONF(0)),
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DEF_FIXED(".pll2", CLK_PLL2, CLK_EXTAL, 200, 3),
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DEF_FIXED(".pll2_533", CLK_PLL2_533, CLK_PLL2, 1, 3),
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DEF_FIXED(".pll3", CLK_PLL3, CLK_EXTAL, 200, 3),
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@@ -9,7 +9,6 @@
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#include <linux/device.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/pm_domain.h>
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#include <dt-bindings/clock/r9a08g045-cpg.h>
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@@ -50,16 +49,6 @@
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#define G3S_SEL_SDHI1 SEL_PLL_PACK(G3S_CPG_SDHI_DSEL, 4, 2)
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#define G3S_SEL_SDHI2 SEL_PLL_PACK(G3S_CPG_SDHI_DSEL, 8, 2)
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/* PLL 1/4/6 configuration registers macro. */
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#define G3S_PLL146_CONF(clk1, clk2, setting) ((clk1) << 22 | (clk2) << 12 | (setting))
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#define DEF_G3S_MUX(_name, _id, _conf, _parent_names, _mux_flags, _clk_flags) \
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DEF_TYPE(_name, _id, CLK_TYPE_MUX, .conf = (_conf), \
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.parent_names = (_parent_names), \
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.num_parents = ARRAY_SIZE((_parent_names)), \
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.mux_flags = CLK_MUX_HIWORD_MASK | (_mux_flags), \
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.flag = (_clk_flags))
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enum clk_ids {
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/* Core Clock Outputs exported to DT */
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LAST_DT_CORE_CLK = R9A08G045_SWD,
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@@ -134,7 +123,7 @@ static const struct cpg_core_clk r9a08g045_core_clks[] __initconst = {
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/* Internal Core Clocks */
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DEF_FIXED(".osc_div1000", CLK_OSC_DIV1000, CLK_EXTAL, 1, 1000),
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DEF_G3S_PLL(".pll1", CLK_PLL1, CLK_EXTAL, G3S_PLL146_CONF(0x4, 0x8, 0x100),
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DEF_G3S_PLL(".pll1", CLK_PLL1, CLK_EXTAL, CPG_PLL_CONF(0, 0x100),
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1100000000UL),
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DEF_FIXED(".pll2", CLK_PLL2, CLK_EXTAL, 200, 3),
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DEF_FIXED(".pll3", CLK_PLL3, CLK_EXTAL, 200, 3),
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@@ -17,17 +17,69 @@
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/* RZ/G3L Specific registers. */
|
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#define G3L_CPG_PL2_DDIV (0x204)
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#define G3L_CPG_PL3_DDIV (0x208)
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#define G3L_CPG_CA55CORE_DDIV (0x234)
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#define G3L_CPG_RSCI_DDIV (0x238)
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#define G3L_CPG_RSPI_DDIV (0x23c)
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#define G3L_CLKDIVSTATUS (0x280)
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#define G3L_CPG_ETH_SSEL (0x410)
|
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#define G3L_CPG_RSCI_SSEL (0x414)
|
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#define G3L_CPG_RSPI_SSEL (0x418)
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#define G3L_CPG_ETH_SDIV (0x434)
|
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|
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/* RZ/G3L Specific division configuration. */
|
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#define G3L_DIVPL2A DDIV_PACK(G3L_CPG_PL2_DDIV, 0, 2)
|
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#define G3L_DIVPL2B DDIV_PACK(G3L_CPG_PL2_DDIV, 4, 2)
|
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#define G3L_DIVPL3A DDIV_PACK(G3L_CPG_PL3_DDIV, 0, 2)
|
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#define G3L_DIV_CA55_CORE0 DDIV_PACK(G3L_CPG_CA55CORE_DDIV, 0, 3)
|
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#define G3L_DIV_CA55_CORE1 DDIV_PACK(G3L_CPG_CA55CORE_DDIV, 4, 3)
|
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#define G3L_DIV_CA55_CORE2 DDIV_PACK(G3L_CPG_CA55CORE_DDIV, 8, 3)
|
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#define G3L_DIV_CA55_CORE3 DDIV_PACK(G3L_CPG_CA55CORE_DDIV, 12, 3)
|
||||
#define G3L_DIV_RSCI0 DDIV_PACK(G3L_CPG_RSCI_DDIV, 0, 2)
|
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#define G3L_DIV_RSCI1 DDIV_PACK(G3L_CPG_RSCI_DDIV, 2, 2)
|
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#define G3L_DIV_RSCI2 DDIV_PACK(G3L_CPG_RSCI_DDIV, 4, 2)
|
||||
#define G3L_DIV_RSCI3 DDIV_PACK(G3L_CPG_RSCI_DDIV, 6, 2)
|
||||
#define G3L_DIV_RSPI0 DDIV_PACK(G3L_CPG_RSPI_DDIV, 0, 2)
|
||||
#define G3L_DIV_RSPI1 DDIV_PACK(G3L_CPG_RSPI_DDIV, 2, 2)
|
||||
#define G3L_DIV_RSPI2 DDIV_PACK(G3L_CPG_RSPI_DDIV, 4, 2)
|
||||
#define G3L_SDIV_ETH_A DDIV_PACK(G3L_CPG_ETH_SDIV, 0, 2)
|
||||
#define G3L_SDIV_ETH_B DDIV_PACK(G3L_CPG_ETH_SDIV, 4, 1)
|
||||
#define G3L_SDIV_ETH_C DDIV_PACK(G3L_CPG_ETH_SDIV, 8, 2)
|
||||
#define G3L_SDIV_ETH_D DDIV_PACK(G3L_CPG_ETH_SDIV, 12, 1)
|
||||
|
||||
/* RZ/G3L Clock status configuration. */
|
||||
#define G3L_DIVPL2A_STS DDIV_PACK(G3L_CLKDIVSTATUS, 4, 1)
|
||||
#define G3L_DIVPL2B_STS DDIV_PACK(G3L_CLKDIVSTATUS, 5, 1)
|
||||
#define G3L_DIVPL3A_STS DDIV_PACK(G3L_CLKDIVSTATUS, 8, 1)
|
||||
#define G3L_DIV_CA55_CORE0_STS DDIV_PACK(G3L_CLKDIVSTATUS, 12, 1)
|
||||
#define G3L_DIV_CA55_CORE1_STS DDIV_PACK(G3L_CLKDIVSTATUS, 13, 1)
|
||||
#define G3L_DIV_CA55_CORE2_STS DDIV_PACK(G3L_CLKDIVSTATUS, 14, 1)
|
||||
#define G3L_DIV_CA55_CORE3_STS DDIV_PACK(G3L_CLKDIVSTATUS, 15, 1)
|
||||
#define G3L_DIV_RSCI0_STS DDIV_PACK(G3L_CLKDIVSTATUS, 16, 1)
|
||||
#define G3L_DIV_RSCI1_STS DDIV_PACK(G3L_CLKDIVSTATUS, 17, 1)
|
||||
#define G3L_DIV_RSCI2_STS DDIV_PACK(G3L_CLKDIVSTATUS, 18, 1)
|
||||
#define G3L_DIV_RSCI3_STS DDIV_PACK(G3L_CLKDIVSTATUS, 19, 1)
|
||||
#define G3L_DIV_RSPI0_STS DDIV_PACK(G3L_CLKDIVSTATUS, 20, 1)
|
||||
#define G3L_DIV_RSPI1_STS DDIV_PACK(G3L_CLKDIVSTATUS, 21, 1)
|
||||
#define G3L_DIV_RSPI2_STS DDIV_PACK(G3L_CLKDIVSTATUS, 22, 1)
|
||||
|
||||
/* RZ/G3L Specific clocks select. */
|
||||
#define G3L_SEL_ETH0_TX SEL_PLL_PACK(G3L_CPG_ETH_SSEL, 0, 1)
|
||||
#define G3L_SEL_ETH0_RX SEL_PLL_PACK(G3L_CPG_ETH_SSEL, 1, 1)
|
||||
#define G3L_SEL_ETH0_RM SEL_PLL_PACK(G3L_CPG_ETH_SSEL, 2, 1)
|
||||
#define G3L_SEL_ETH0_CLK_TX_I SEL_PLL_PACK(G3L_CPG_ETH_SSEL, 3, 1)
|
||||
#define G3L_SEL_ETH0_CLK_RX_I SEL_PLL_PACK(G3L_CPG_ETH_SSEL, 4, 1)
|
||||
#define G3L_SEL_ETH1_TX SEL_PLL_PACK(G3L_CPG_ETH_SSEL, 8, 1)
|
||||
#define G3L_SEL_ETH1_RX SEL_PLL_PACK(G3L_CPG_ETH_SSEL, 9, 1)
|
||||
#define G3L_SEL_ETH1_RM SEL_PLL_PACK(G3L_CPG_ETH_SSEL, 10, 1)
|
||||
#define G3L_SEL_ETH1_CLK_TX_I SEL_PLL_PACK(G3L_CPG_ETH_SSEL, 11, 1)
|
||||
#define G3L_SEL_ETH1_CLK_RX_I SEL_PLL_PACK(G3L_CPG_ETH_SSEL, 12, 1)
|
||||
#define G3L_SEL_RSCI0 SEL_PLL_PACK(G3L_CPG_RSCI_SSEL, 0, 2)
|
||||
#define G3L_SEL_RSCI1 SEL_PLL_PACK(G3L_CPG_RSCI_SSEL, 2, 2)
|
||||
#define G3L_SEL_RSCI2 SEL_PLL_PACK(G3L_CPG_RSCI_SSEL, 4, 2)
|
||||
#define G3L_SEL_RSCI3 SEL_PLL_PACK(G3L_CPG_RSCI_SSEL, 6, 2)
|
||||
#define G3L_SEL_RSPI0 SEL_PLL_PACK(G3L_CPG_RSPI_SSEL, 0, 2)
|
||||
#define G3L_SEL_RSPI1 SEL_PLL_PACK(G3L_CPG_RSPI_SSEL, 2, 2)
|
||||
#define G3L_SEL_RSPI2 SEL_PLL_PACK(G3L_CPG_RSPI_SSEL, 4, 2)
|
||||
|
||||
enum clk_ids {
|
||||
/* Core Clock Outputs exported to DT */
|
||||
@@ -41,16 +93,72 @@ enum clk_ids {
|
||||
CLK_ETH1_RXC_RX_CLK_IN,
|
||||
|
||||
/* Internal Core Clocks */
|
||||
CLK_PLL1,
|
||||
CLK_PLL2,
|
||||
CLK_PLL2_DIV2,
|
||||
CLK_PLL2_DIV2_4,
|
||||
CLK_PLL2_DIV5,
|
||||
CLK_PLL2_DIV6,
|
||||
CLK_PLL2_DIV7,
|
||||
CLK_PLL3,
|
||||
CLK_PLL3_DIV2,
|
||||
CLK_PLL6,
|
||||
CLK_PLL6_DIV10,
|
||||
CLK_SEL_ETH0_TX,
|
||||
CLK_SEL_ETH0_RX,
|
||||
CLK_SEL_ETH0_RM,
|
||||
CLK_SEL_ETH1_TX,
|
||||
CLK_SEL_ETH1_RX,
|
||||
CLK_SEL_ETH1_RM,
|
||||
CLK_SEL_RSCI0,
|
||||
CLK_SEL_RSCI1,
|
||||
CLK_SEL_RSCI2,
|
||||
CLK_SEL_RSCI3,
|
||||
CLK_SEL_RSPI0,
|
||||
CLK_SEL_RSPI1,
|
||||
CLK_SEL_RSPI2,
|
||||
CLK_ETH0_TR,
|
||||
CLK_ETH0_RM,
|
||||
CLK_ETH1_TR,
|
||||
CLK_ETH1_RM,
|
||||
|
||||
/* Module Clocks */
|
||||
MOD_CLK_BASE,
|
||||
};
|
||||
|
||||
/* Divider tables */
|
||||
static const struct clk_div_table dtable_1_8[] = {
|
||||
{ 0, 1 },
|
||||
{ 1, 2 },
|
||||
{ 2, 4 },
|
||||
{ 3, 8 },
|
||||
{ 0, 0 },
|
||||
};
|
||||
|
||||
static const struct clk_div_table dtable_1_32[] = {
|
||||
{ 0, 1 },
|
||||
{ 1, 2 },
|
||||
{ 2, 4 },
|
||||
{ 3, 8 },
|
||||
{ 4, 16 },
|
||||
{ 5, 32 },
|
||||
{ 0, 0 },
|
||||
};
|
||||
|
||||
static const struct clk_div_table dtable_2_20[] = {
|
||||
{ 0, 2 },
|
||||
{ 1, 20 },
|
||||
{ 0, 0 },
|
||||
};
|
||||
|
||||
static const struct clk_div_table dtable_2_16[] = {
|
||||
{ 0, 2 },
|
||||
{ 1, 4 },
|
||||
{ 2, 8 },
|
||||
{ 3, 16 },
|
||||
{ 0, 0 },
|
||||
};
|
||||
|
||||
static const struct clk_div_table dtable_4_128[] = {
|
||||
{ 0, 4 },
|
||||
{ 1, 8 },
|
||||
@@ -59,6 +167,13 @@ static const struct clk_div_table dtable_4_128[] = {
|
||||
{ 0, 0 },
|
||||
};
|
||||
|
||||
static const struct clk_div_table dtable_4_200[] = {
|
||||
{ 0, 4 },
|
||||
{ 1, 20 },
|
||||
{ 2, 200 },
|
||||
{ 0, 0 },
|
||||
};
|
||||
|
||||
static const struct clk_div_table dtable_8_256[] = {
|
||||
{ 0, 8 },
|
||||
{ 1, 16 },
|
||||
@@ -67,6 +182,19 @@ static const struct clk_div_table dtable_8_256[] = {
|
||||
{ 0, 0 },
|
||||
};
|
||||
|
||||
/* Mux clock names tables. */
|
||||
static const char * const sel_eth0_tx[] = { ".div_eth0_tr", "eth0_txc_tx_clk" };
|
||||
static const char * const sel_eth0_rx[] = { ".div_eth0_tr", "eth0_rxc_rx_clk" };
|
||||
static const char * const sel_eth0_rm[] = { ".pll6_div10", "eth0_rxc_rx_clk" };
|
||||
static const char * const sel_eth1_tx[] = { ".div_eth1_tr", "eth1_txc_tx_clk" };
|
||||
static const char * const sel_eth1_rx[] = { ".div_eth1_tr", "eth1_rxc_rx_clk" };
|
||||
static const char * const sel_eth1_rm[] = { ".pll6_div10", "eth1_rxc_rx_clk" };
|
||||
static const char * const sel_rsci_rspi[] = { ".pll2_div5", ".pll2_div6", ".pll2_div7", ".pll2_div2_4" };
|
||||
static const char * const sel_eth0_clk_tx_i[] = { ".sel_eth0_tx", ".div_eth0_rm" };
|
||||
static const char * const sel_eth0_clk_rx_i[] = { ".sel_eth0_rx", ".div_eth0_rm" };
|
||||
static const char * const sel_eth1_clk_tx_i[] = { ".sel_eth1_tx", ".div_eth1_rm" };
|
||||
static const char * const sel_eth1_clk_rx_i[] = { ".sel_eth1_rx", ".div_eth1_rm" };
|
||||
|
||||
static const struct cpg_core_clk r9a08g046_core_clks[] __initconst = {
|
||||
/* External Clock Inputs */
|
||||
DEF_INPUT("extal", CLK_EXTAL),
|
||||
@@ -76,18 +204,82 @@ static const struct cpg_core_clk r9a08g046_core_clks[] __initconst = {
|
||||
DEF_INPUT("eth1_rxc_rx_clk", CLK_ETH1_RXC_RX_CLK_IN),
|
||||
|
||||
/* Internal Core Clocks */
|
||||
DEF_G3L_PLL(".pll1", CLK_PLL1, CLK_EXTAL, CPG_PLL_CONF(0, 0x100),
|
||||
1200000000UL),
|
||||
DEF_FIXED(".pll2", CLK_PLL2, CLK_EXTAL, 200, 3),
|
||||
DEF_FIXED(".pll3", CLK_PLL3, CLK_EXTAL, 200, 3),
|
||||
DEF_G3L_PLL(".pll6", CLK_PLL6, CLK_EXTAL, CPG_PLL_CONF(0x50, 0),
|
||||
500000000UL),
|
||||
DEF_FIXED(".pll2_div2", CLK_PLL2_DIV2, CLK_PLL2, 1, 2),
|
||||
DEF_FIXED(".pll2_div2_4", CLK_PLL2_DIV2_4, CLK_PLL2_DIV2, 1, 4),
|
||||
DEF_FIXED(".pll2_div5", CLK_PLL2_DIV5, CLK_PLL2, 1, 5),
|
||||
DEF_FIXED(".pll2_div6", CLK_PLL2_DIV6, CLK_PLL2, 1, 6),
|
||||
DEF_FIXED(".pll2_div7", CLK_PLL2_DIV7, CLK_PLL2, 1, 7),
|
||||
DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 1, 2),
|
||||
DEF_FIXED(".pll6_div10", CLK_PLL6_DIV10, CLK_PLL6, 1, 10),
|
||||
DEF_MUX(".sel_rsci0", CLK_SEL_RSCI0, G3L_SEL_RSCI0, sel_rsci_rspi),
|
||||
DEF_MUX(".sel_rsci1", CLK_SEL_RSCI1, G3L_SEL_RSCI1, sel_rsci_rspi),
|
||||
DEF_MUX(".sel_rsci2", CLK_SEL_RSCI2, G3L_SEL_RSCI2, sel_rsci_rspi),
|
||||
DEF_MUX(".sel_rsci3", CLK_SEL_RSCI3, G3L_SEL_RSCI3, sel_rsci_rspi),
|
||||
DEF_MUX(".sel_rspi0", CLK_SEL_RSPI0, G3L_SEL_RSPI0, sel_rsci_rspi),
|
||||
DEF_MUX(".sel_rspi1", CLK_SEL_RSPI1, G3L_SEL_RSPI1, sel_rsci_rspi),
|
||||
DEF_MUX(".sel_rspi2", CLK_SEL_RSPI2, G3L_SEL_RSPI2, sel_rsci_rspi),
|
||||
DEF_MUX(".sel_eth0_tx", CLK_SEL_ETH0_TX, G3L_SEL_ETH0_TX, sel_eth0_tx),
|
||||
DEF_MUX(".sel_eth0_rx", CLK_SEL_ETH0_RX, G3L_SEL_ETH0_RX, sel_eth0_rx),
|
||||
DEF_MUX(".sel_eth0_rm", CLK_SEL_ETH0_RM, G3L_SEL_ETH0_RM, sel_eth0_rm),
|
||||
DEF_MUX(".sel_eth1_tx", CLK_SEL_ETH1_TX, G3L_SEL_ETH1_TX, sel_eth1_tx),
|
||||
DEF_MUX(".sel_eth1_rx", CLK_SEL_ETH1_RX, G3L_SEL_ETH1_RX, sel_eth1_rx),
|
||||
DEF_MUX(".sel_eth1_rm", CLK_SEL_ETH1_RM, G3L_SEL_ETH1_RM, sel_eth1_rm),
|
||||
DEF_DIV(".div_eth0_tr", CLK_ETH0_TR, CLK_PLL6, G3L_SDIV_ETH_A, dtable_4_200),
|
||||
DEF_DIV(".div_eth1_tr", CLK_ETH1_TR, CLK_PLL6, G3L_SDIV_ETH_C, dtable_4_200),
|
||||
DEF_DIV(".div_eth0_rm", CLK_ETH0_RM, CLK_SEL_ETH0_RM, G3L_SDIV_ETH_B, dtable_2_20),
|
||||
DEF_DIV(".div_eth1_rm", CLK_ETH1_RM, CLK_SEL_ETH1_RM, G3L_SDIV_ETH_D, dtable_2_20),
|
||||
|
||||
/* Core output clk */
|
||||
DEF_G3S_DIV("IC0", R9A08G046_CLK_IC0, CLK_PLL1, G3L_DIV_CA55_CORE0, G3L_DIV_CA55_CORE0_STS,
|
||||
dtable_1_32, 0, 0, 0, NULL),
|
||||
DEF_G3S_DIV("IC1", R9A08G046_CLK_IC1, CLK_PLL1, G3L_DIV_CA55_CORE1, G3L_DIV_CA55_CORE1_STS,
|
||||
dtable_1_32, 0, 0, 0, NULL),
|
||||
DEF_G3S_DIV("IC2", R9A08G046_CLK_IC2, CLK_PLL1, G3L_DIV_CA55_CORE2, G3L_DIV_CA55_CORE2_STS,
|
||||
dtable_1_32, 0, 0, 0, NULL),
|
||||
DEF_G3S_DIV("IC3", R9A08G046_CLK_IC3, CLK_PLL1, G3L_DIV_CA55_CORE3, G3L_DIV_CA55_CORE3_STS,
|
||||
dtable_1_32, 0, 0, 0, NULL),
|
||||
DEF_G3S_DIV("P0", R9A08G046_CLK_P0, CLK_PLL2_DIV2, G3L_DIVPL2B, G3L_DIVPL2B_STS,
|
||||
dtable_8_256, 0, 0, 0, NULL),
|
||||
DEF_G3S_DIV("P1", R9A08G046_CLK_P1, CLK_PLL3_DIV2, G3L_DIVPL3A, G3L_DIVPL3A_STS,
|
||||
dtable_4_128, 0, 0, 0, NULL),
|
||||
DEF_G3S_DIV("P3", R9A08G046_CLK_P3, CLK_PLL2_DIV2, G3L_DIVPL2A, G3L_DIVPL2A_STS,
|
||||
dtable_4_128, 0, 0, 0, NULL),
|
||||
DEF_G3S_DIV("P13", R9A08G046_CLK_P13, CLK_SEL_RSCI0, G3L_DIV_RSCI0, G3L_DIV_RSCI0_STS,
|
||||
dtable_2_16, 0, 100000000UL, 0, NULL),
|
||||
DEF_G3S_DIV("P14", R9A08G046_CLK_P14, CLK_SEL_RSCI1, G3L_DIV_RSCI1, G3L_DIV_RSCI1_STS,
|
||||
dtable_2_16, 0, 100000000UL, 0, NULL),
|
||||
DEF_G3S_DIV("P15", R9A08G046_CLK_P15, CLK_SEL_RSCI2, G3L_DIV_RSCI2, G3L_DIV_RSCI2_STS,
|
||||
dtable_2_16, 0, 100000000UL, 0, NULL),
|
||||
DEF_G3S_DIV("P16", R9A08G046_CLK_P16, CLK_SEL_RSCI3, G3L_DIV_RSCI3, G3L_DIV_RSCI3_STS,
|
||||
dtable_2_16, 0, 100000000UL, 0, NULL),
|
||||
DEF_G3S_DIV("P17", R9A08G046_CLK_P17, CLK_SEL_RSPI0, G3L_DIV_RSPI0, G3L_DIV_RSPI0_STS,
|
||||
dtable_1_8, 0, 200000000UL, 0, NULL),
|
||||
DEF_G3S_DIV("P18", R9A08G046_CLK_P18, CLK_SEL_RSPI1, G3L_DIV_RSPI1, G3L_DIV_RSPI1_STS,
|
||||
dtable_1_8, 0, 200000000UL, 0, NULL),
|
||||
DEF_G3S_DIV("P19", R9A08G046_CLK_P19, CLK_SEL_RSPI2, G3L_DIV_RSPI2, G3L_DIV_RSPI2_STS,
|
||||
dtable_1_8, 0, 200000000UL, 0, NULL),
|
||||
DEF_FIXED("HP", R9A08G046_CLK_HP, CLK_PLL6_DIV10, 1, 1),
|
||||
DEF_MUX_FLAGS("ETHTX01", R9A08G046_CLK_ETHTX01, G3L_SEL_ETH0_CLK_TX_I, sel_eth0_clk_tx_i,
|
||||
CLK_SET_RATE_PARENT),
|
||||
DEF_MUX_FLAGS("ETHRX01", R9A08G046_CLK_ETHRX01, G3L_SEL_ETH0_CLK_RX_I, sel_eth0_clk_rx_i,
|
||||
CLK_SET_RATE_PARENT),
|
||||
DEF_MUX_FLAGS("ETHTX11", R9A08G046_CLK_ETHTX11, G3L_SEL_ETH1_CLK_TX_I, sel_eth1_clk_tx_i,
|
||||
CLK_SET_RATE_PARENT),
|
||||
DEF_MUX_FLAGS("ETHRX11", R9A08G046_CLK_ETHRX11, G3L_SEL_ETH1_CLK_RX_I, sel_eth1_clk_rx_i,
|
||||
CLK_SET_RATE_PARENT),
|
||||
DEF_FIXED("ETHRM0", R9A08G046_CLK_ETHRM0, CLK_SEL_ETH0_RM, 1, 1),
|
||||
DEF_FIXED("ETHTX02", R9A08G046_CLK_ETHTX02, CLK_SEL_ETH0_TX, 1, 1),
|
||||
DEF_FIXED("ETHRX02", R9A08G046_CLK_ETHRX02, CLK_SEL_ETH0_RX, 1, 1),
|
||||
DEF_FIXED("ETHRM1", R9A08G046_CLK_ETHRM1, CLK_SEL_ETH1_RM, 1, 1),
|
||||
DEF_FIXED("ETHTX12", R9A08G046_CLK_ETHTX12, CLK_SEL_ETH1_TX, 1, 1),
|
||||
DEF_FIXED("ETHRX12", R9A08G046_CLK_ETHRX12, CLK_SEL_ETH1_RX, 1, 1),
|
||||
DEF_FIXED("OSCCLK", R9A08G046_OSCCLK, CLK_EXTAL, 1, 1),
|
||||
};
|
||||
|
||||
static const struct rzg2l_mod_clk r9a08g046_mod_clks[] = {
|
||||
@@ -101,8 +293,116 @@ static const struct rzg2l_mod_clk r9a08g046_mod_clks[] = {
|
||||
MSTOP(BUS_REG1, BIT(2))),
|
||||
DEF_MOD("dmac_pclk", R9A08G046_DMAC_PCLK, R9A08G046_CLK_P3, 0x52c, 1,
|
||||
MSTOP(BUS_REG1, BIT(3))),
|
||||
DEF_MOD("wdt0_pclk", R9A08G046_WDT0_PCLK, R9A08G046_CLK_P0, 0x548, 0,
|
||||
MSTOP(BUS_REG0, BIT(0))),
|
||||
DEF_MOD("wdt0_clk", R9A08G046_WDT0_CLK, R9A08G046_OSCCLK, 0x548, 1,
|
||||
MSTOP(BUS_REG0, BIT(0))),
|
||||
DEF_MOD("ssi0_pclk2", R9A08G046_SSI0_PCLK2, R9A08G046_CLK_P0, 0x570, 0,
|
||||
MSTOP(BUS_MCPU1, BIT(10))),
|
||||
DEF_MOD("ssi0_pclk_sfr", R9A08G046_SSI0_PCLK_SFR, R9A08G046_CLK_P0, 0x570, 1,
|
||||
MSTOP(BUS_MCPU1, BIT(10))),
|
||||
DEF_MOD("ssi1_pclk2", R9A08G046_SSI1_PCLK2, R9A08G046_CLK_P0, 0x570, 2,
|
||||
MSTOP(BUS_MCPU1, BIT(11))),
|
||||
DEF_MOD("ssi1_pclk_sfr", R9A08G046_SSI1_PCLK_SFR, R9A08G046_CLK_P0, 0x570, 3,
|
||||
MSTOP(BUS_MCPU1, BIT(11))),
|
||||
DEF_MOD("ssi2_pclk2", R9A08G046_SSI2_PCLK2, R9A08G046_CLK_P0, 0x570, 4,
|
||||
MSTOP(BUS_MCPU1, BIT(12))),
|
||||
DEF_MOD("ssi2_pclk_sfr", R9A08G046_SSI2_PCLK_SFR, R9A08G046_CLK_P0, 0x570, 5,
|
||||
MSTOP(BUS_MCPU1, BIT(12))),
|
||||
DEF_MOD("ssi3_pclk2", R9A08G046_SSI3_PCLK2, R9A08G046_CLK_P0, 0x570, 6,
|
||||
MSTOP(BUS_MCPU1, BIT(13))),
|
||||
DEF_MOD("ssi3_pclk_sfr", R9A08G046_SSI3_PCLK_SFR, R9A08G046_CLK_P0, 0x570, 7,
|
||||
MSTOP(BUS_MCPU1, BIT(13))),
|
||||
DEF_MOD("eth0_clk_axi", R9A08G046_ETH0_CLK_AXI, R9A08G046_CLK_P1, 0x57c, 0,
|
||||
MSTOP(BUS_PERI_COM, BIT(2))),
|
||||
DEF_MOD("eth1_clk_axi", R9A08G046_ETH1_CLK_AXI, R9A08G046_CLK_P1, 0x57c, 1,
|
||||
MSTOP(BUS_PERI_COM, BIT(3))),
|
||||
DEF_MOD("eth0_clk_chi", R9A08G046_ETH0_CLK_CHI, R9A08G046_CLK_P1, 0x57c, 2,
|
||||
MSTOP(BUS_PERI_COM, BIT(2))),
|
||||
DEF_MOD("eth1_clk_chi", R9A08G046_ETH1_CLK_CHI, R9A08G046_CLK_P1, 0x57c, 3,
|
||||
MSTOP(BUS_PERI_COM, BIT(3))),
|
||||
DEF_COUPLED("eth0_tx_i", R9A08G046_ETH0_CLK_TX_I, R9A08G046_CLK_ETHTX01, 0x57c, 4,
|
||||
MSTOP(BUS_PERI_COM, BIT(2))),
|
||||
DEF_COUPLED("eth0_tx_180_i", R9A08G046_ETH0_CLK_TX_180_I, R9A08G046_CLK_ETHTX02, 0x57c, 4,
|
||||
MSTOP(BUS_PERI_COM, BIT(2))),
|
||||
DEF_COUPLED("eth1_tx_i", R9A08G046_ETH1_CLK_TX_I, R9A08G046_CLK_ETHTX11, 0x57c, 5,
|
||||
MSTOP(BUS_PERI_COM, BIT(3))),
|
||||
DEF_COUPLED("eth1_tx_180_i", R9A08G046_ETH1_CLK_TX_180_I, R9A08G046_CLK_ETHTX12, 0x57c, 5,
|
||||
MSTOP(BUS_PERI_COM, BIT(3))),
|
||||
DEF_COUPLED("eth0_rx_i", R9A08G046_ETH0_CLK_RX_I, R9A08G046_CLK_ETHRX01, 0x57c, 6,
|
||||
MSTOP(BUS_PERI_COM, BIT(2))),
|
||||
DEF_COUPLED("eth0_rx_180_i", R9A08G046_ETH0_CLK_RX_180_I, R9A08G046_CLK_ETHRX02, 0x57c, 6,
|
||||
MSTOP(BUS_PERI_COM, BIT(2))),
|
||||
DEF_COUPLED("eth1_rx_i", R9A08G046_ETH1_CLK_RX_I, R9A08G046_CLK_ETHRX11, 0x57c, 7,
|
||||
MSTOP(BUS_PERI_COM, BIT(3))),
|
||||
DEF_COUPLED("eth1_rx_180_i", R9A08G046_ETH1_CLK_RX_180_I, R9A08G046_CLK_ETHRX12, 0x57c, 7,
|
||||
MSTOP(BUS_PERI_COM, BIT(3))),
|
||||
DEF_MOD("eth0_ptp_ref_i", R9A08G046_ETH0_CLK_PTP_REF_I, R9A08G046_CLK_HP, 0x57c, 8,
|
||||
MSTOP(BUS_PERI_COM, BIT(2))),
|
||||
DEF_MOD("eth1_ptp_ref_i", R9A08G046_ETH1_CLK_PTP_REF_I, R9A08G046_CLK_HP, 0x57c, 9,
|
||||
MSTOP(BUS_PERI_COM, BIT(3))),
|
||||
DEF_MOD("eth0_rmii_i", R9A08G046_ETH0_CLK_RMII_I, R9A08G046_CLK_ETHRM0, 0x57c, 10,
|
||||
MSTOP(BUS_PERI_COM, BIT(2))),
|
||||
DEF_MOD("eth1_rmii_i", R9A08G046_ETH1_CLK_RMII_I, R9A08G046_CLK_ETHRM1, 0x57c, 11,
|
||||
MSTOP(BUS_PERI_COM, BIT(3))),
|
||||
DEF_COUPLED("eth0_tx_i_rmii", R9A08G046_ETH0_CLK_TX_I_RMII, R9A08G046_CLK_ETHTX01, 0x57c, 12,
|
||||
MSTOP(BUS_PERI_COM, BIT(2))),
|
||||
DEF_COUPLED("eth0_rx_i_rmii", R9A08G046_ETH0_CLK_RX_I_RMII, R9A08G046_CLK_ETHRX01, 0x57c, 12,
|
||||
MSTOP(BUS_PERI_COM, BIT(2))),
|
||||
DEF_COUPLED("eth1_tx_i_rmii", R9A08G046_ETH1_CLK_TX_I_RMII, R9A08G046_CLK_ETHTX11, 0x57c, 13,
|
||||
MSTOP(BUS_PERI_COM, BIT(3))),
|
||||
DEF_COUPLED("eth1_rx_i_rmii", R9A08G046_ETH1_CLK_RX_I_RMII, R9A08G046_CLK_ETHRX11, 0x57c, 13,
|
||||
MSTOP(BUS_PERI_COM, BIT(3))),
|
||||
DEF_MOD("i2c0_pclk", R9A08G046_I2C0_PCLK, R9A08G046_CLK_P0, 0x580, 0,
|
||||
MSTOP(BUS_MCPU2, BIT(10))),
|
||||
DEF_MOD("i2c1_pclk", R9A08G046_I2C1_PCLK, R9A08G046_CLK_P0, 0x580, 1,
|
||||
MSTOP(BUS_MCPU2, BIT(11))),
|
||||
DEF_MOD("i2c2_pclk", R9A08G046_I2C2_PCLK, R9A08G046_CLK_P0, 0x580, 2,
|
||||
MSTOP(BUS_MCPU2, BIT(12))),
|
||||
DEF_MOD("i2c3_pclk", R9A08G046_I2C3_PCLK, R9A08G046_CLK_P0, 0x580, 3,
|
||||
MSTOP(BUS_MCPU2, BIT(13))),
|
||||
DEF_MOD("scif0_clk_pck", R9A08G046_SCIF0_CLK_PCK, R9A08G046_CLK_P0, 0x584, 0,
|
||||
MSTOP(BUS_MCPU2, BIT(1))),
|
||||
DEF_MOD("scif1_clk_pck", R9A08G046_SCIF1_CLK_PCK, R9A08G046_CLK_P0, 0x584, 1,
|
||||
MSTOP(BUS_MCPU2, BIT(2))),
|
||||
DEF_MOD("scif2_clk_pck", R9A08G046_SCIF2_CLK_PCK, R9A08G046_CLK_P0, 0x584, 2,
|
||||
MSTOP(BUS_MCPU2, BIT(3))),
|
||||
DEF_MOD("scif3_clk_pck", R9A08G046_SCIF3_CLK_PCK, R9A08G046_CLK_P0, 0x584, 3,
|
||||
MSTOP(BUS_MCPU2, BIT(4))),
|
||||
DEF_MOD("scif4_clk_pck", R9A08G046_SCIF4_CLK_PCK, R9A08G046_CLK_P0, 0x584, 4,
|
||||
MSTOP(BUS_MCPU2, BIT(5))),
|
||||
DEF_MOD("scif5_clk_pck", R9A08G046_SCIF5_CLK_PCK, R9A08G046_CLK_P0, 0x584, 5,
|
||||
MSTOP(BUS_MCPU3, BIT(4))),
|
||||
DEF_MOD("rspi0_pclk", R9A08G046_RSPI0_PCLK, R9A08G046_CLK_P3, 0x590, 0,
|
||||
MSTOP(BUS_MCPU1, BIT(14))),
|
||||
DEF_MOD("rspi1_pclk", R9A08G046_RSPI1_PCLK, R9A08G046_CLK_P3, 0x590, 1,
|
||||
MSTOP(BUS_MCPU1, BIT(15))),
|
||||
DEF_MOD("rspi2_pclk", R9A08G046_RSPI2_PCLK, R9A08G046_CLK_P3, 0x590, 2,
|
||||
MSTOP(BUS_MCPU2, BIT(0))),
|
||||
DEF_MOD("rspi0_tclk", R9A08G046_RSPI0_TCLK, R9A08G046_CLK_P17, 0x590, 8,
|
||||
MSTOP(BUS_MCPU1, BIT(14))),
|
||||
DEF_MOD("rspi1_tclk", R9A08G046_RSPI1_TCLK, R9A08G046_CLK_P18, 0x590, 9,
|
||||
MSTOP(BUS_MCPU1, BIT(15))),
|
||||
DEF_MOD("rspi2_tclk", R9A08G046_RSPI2_TCLK, R9A08G046_CLK_P19, 0x590, 10,
|
||||
MSTOP(BUS_MCPU2, BIT(0))),
|
||||
DEF_MOD("gpio_hclk", R9A08G046_GPIO_HCLK, R9A08G046_OSCCLK, 0x598, 0,
|
||||
MSTOP(BUS_PERI_CPU, BIT(6))),
|
||||
DEF_MOD("rsci0_pclk", R9A08G046_RSCI0_PCLK, R9A08G046_CLK_P0, 0x618, 0,
|
||||
MSTOP(BUS_MCPU2, BIT(7))),
|
||||
DEF_MOD("rsci1_pclk", R9A08G046_RSCI1_PCLK, R9A08G046_CLK_P0, 0x618, 1,
|
||||
MSTOP(BUS_MCPU2, BIT(8))),
|
||||
DEF_MOD("rsci2_pclk", R9A08G046_RSCI2_PCLK, R9A08G046_CLK_P0, 0x618, 2,
|
||||
MSTOP(BUS_MCPU3, BIT(11))),
|
||||
DEF_MOD("rsci3_pclk", R9A08G046_RSCI3_PCLK, R9A08G046_CLK_P0, 0x618, 3,
|
||||
MSTOP(BUS_MCPU3, BIT(12))),
|
||||
DEF_MOD("rsci0_tclk", R9A08G046_RSCI0_TCLK, R9A08G046_CLK_P13, 0x618, 8,
|
||||
MSTOP(BUS_MCPU2, BIT(7))),
|
||||
DEF_MOD("rsci1_tclk", R9A08G046_RSCI1_TCLK, R9A08G046_CLK_P14, 0x618, 9,
|
||||
MSTOP(BUS_MCPU2, BIT(8))),
|
||||
DEF_MOD("rsci2_tclk", R9A08G046_RSCI2_TCLK, R9A08G046_CLK_P15, 0x618, 10,
|
||||
MSTOP(BUS_MCPU3, BIT(11))),
|
||||
DEF_MOD("rsci3_tclk", R9A08G046_RSCI3_TCLK, R9A08G046_CLK_P16, 0x618, 11,
|
||||
MSTOP(BUS_MCPU3, BIT(12))),
|
||||
};
|
||||
|
||||
static const struct rzg2l_reset r9a08g046_resets[] = {
|
||||
@@ -111,11 +411,45 @@ static const struct rzg2l_reset r9a08g046_resets[] = {
|
||||
DEF_RST(R9A08G046_IA55_RESETN, 0x818, 0),
|
||||
DEF_RST(R9A08G046_DMAC_ARESETN, 0x82c, 0),
|
||||
DEF_RST(R9A08G046_DMAC_RST_ASYNC, 0x82c, 1),
|
||||
DEF_RST(R9A08G046_WDT0_PRESETN, 0x848, 0),
|
||||
DEF_RST(R9A08G046_SSI0_RST_M2_REG, 0x870, 0),
|
||||
DEF_RST(R9A08G046_SSI1_RST_M2_REG, 0x870, 1),
|
||||
DEF_RST(R9A08G046_SSI2_RST_M2_REG, 0x870, 2),
|
||||
DEF_RST(R9A08G046_SSI3_RST_M2_REG, 0x870, 3),
|
||||
DEF_RST(R9A08G046_ETH0_ARESET_N, 0x87c, 0),
|
||||
DEF_RST(R9A08G046_ETH1_ARESET_N, 0x87c, 1),
|
||||
DEF_RST(R9A08G046_I2C0_MRST, 0x880, 0),
|
||||
DEF_RST(R9A08G046_I2C1_MRST, 0x880, 1),
|
||||
DEF_RST(R9A08G046_I2C2_MRST, 0x880, 2),
|
||||
DEF_RST(R9A08G046_I2C3_MRST, 0x880, 3),
|
||||
DEF_RST(R9A08G046_SCIF0_RST_SYSTEM_N, 0x884, 0),
|
||||
DEF_RST(R9A08G046_SCIF1_RST_SYSTEM_N, 0x884, 1),
|
||||
DEF_RST(R9A08G046_SCIF2_RST_SYSTEM_N, 0x884, 2),
|
||||
DEF_RST(R9A08G046_SCIF3_RST_SYSTEM_N, 0x884, 3),
|
||||
DEF_RST(R9A08G046_SCIF4_RST_SYSTEM_N, 0x884, 4),
|
||||
DEF_RST(R9A08G046_SCIF5_RST_SYSTEM_N, 0x884, 5),
|
||||
DEF_RST(R9A08G046_RSPI0_PRESETN, 0x890, 0),
|
||||
DEF_RST(R9A08G046_RSPI1_PRESETN, 0x890, 1),
|
||||
DEF_RST(R9A08G046_RSPI2_PRESETN, 0x890, 2),
|
||||
DEF_RST(R9A08G046_RSPI0_TRESETN, 0x890, 8),
|
||||
DEF_RST(R9A08G046_RSPI1_TRESETN, 0x890, 9),
|
||||
DEF_RST(R9A08G046_RSPI2_TRESETN, 0x890, 10),
|
||||
DEF_RST(R9A08G046_GPIO_RSTN, 0x898, 0),
|
||||
DEF_RST(R9A08G046_GPIO_PORT_RESETN, 0x898, 1),
|
||||
DEF_RST(R9A08G046_GPIO_SPARE_RESETN, 0x898, 2),
|
||||
DEF_RST(R9A08G046_RSCI0_PRESETN, 0x918, 0),
|
||||
DEF_RST(R9A08G046_RSCI1_PRESETN, 0x918, 1),
|
||||
DEF_RST(R9A08G046_RSCI2_PRESETN, 0x918, 2),
|
||||
DEF_RST(R9A08G046_RSCI3_PRESETN, 0x918, 3),
|
||||
DEF_RST(R9A08G046_RSCI0_TRESETN, 0x918, 8),
|
||||
DEF_RST(R9A08G046_RSCI1_TRESETN, 0x918, 9),
|
||||
DEF_RST(R9A08G046_RSCI2_TRESETN, 0x918, 10),
|
||||
DEF_RST(R9A08G046_RSCI3_TRESETN, 0x918, 11),
|
||||
};
|
||||
|
||||
static const unsigned int r9a08g046_crit_mod_clks[] __initconst = {
|
||||
MOD_CLK_BASE + R9A08G046_GIC600_GICCLK,
|
||||
MOD_CLK_BASE + R9A08G046_IA55_PCLK,
|
||||
MOD_CLK_BASE + R9A08G046_IA55_CLK,
|
||||
MOD_CLK_BASE + R9A08G046_DMAC_ACLK,
|
||||
};
|
||||
@@ -125,6 +459,23 @@ static const unsigned int r9a08g046_crit_resets[] = {
|
||||
R9A08G046_DMAC_RST_ASYNC,
|
||||
};
|
||||
|
||||
static const unsigned int r9a08g046_no_pm_mod_clks[] = {
|
||||
MOD_CLK_BASE + R9A08G046_ETH0_CLK_TX_I,
|
||||
MOD_CLK_BASE + R9A08G046_ETH0_CLK_TX_180_I,
|
||||
MOD_CLK_BASE + R9A08G046_ETH0_CLK_RX_I,
|
||||
MOD_CLK_BASE + R9A08G046_ETH0_CLK_RX_180_I,
|
||||
MOD_CLK_BASE + R9A08G046_ETH0_CLK_RMII_I,
|
||||
MOD_CLK_BASE + R9A08G046_ETH0_CLK_TX_I_RMII,
|
||||
MOD_CLK_BASE + R9A08G046_ETH0_CLK_RX_I_RMII,
|
||||
MOD_CLK_BASE + R9A08G046_ETH1_CLK_TX_I,
|
||||
MOD_CLK_BASE + R9A08G046_ETH1_CLK_TX_180_I,
|
||||
MOD_CLK_BASE + R9A08G046_ETH1_CLK_RX_I,
|
||||
MOD_CLK_BASE + R9A08G046_ETH1_CLK_RX_180_I,
|
||||
MOD_CLK_BASE + R9A08G046_ETH1_CLK_RMII_I,
|
||||
MOD_CLK_BASE + R9A08G046_ETH1_CLK_TX_I_RMII,
|
||||
MOD_CLK_BASE + R9A08G046_ETH1_CLK_RX_I_RMII,
|
||||
};
|
||||
|
||||
const struct rzg2l_cpg_info r9a08g046_cpg_info = {
|
||||
/* Core Clocks */
|
||||
.core_clks = r9a08g046_core_clks,
|
||||
@@ -141,6 +492,10 @@ const struct rzg2l_cpg_info r9a08g046_cpg_info = {
|
||||
.num_mod_clks = ARRAY_SIZE(r9a08g046_mod_clks),
|
||||
.num_hw_mod_clks = R9A08G046_BSC_X_BCK_BSC + 1,
|
||||
|
||||
/* No PM modules Clocks */
|
||||
.no_pm_mod_clks = r9a08g046_no_pm_mod_clks,
|
||||
.num_no_pm_mod_clks = ARRAY_SIZE(r9a08g046_no_pm_mod_clks),
|
||||
|
||||
/* Resets */
|
||||
.resets = r9a08g046_resets,
|
||||
.num_resets = R9A08G046_BSC_X_PRESET_BSC + 1, /* Last reset ID + 1 */
|
||||
|
||||
@@ -16,11 +16,6 @@
|
||||
|
||||
#include "rzg2l-cpg.h"
|
||||
|
||||
#define RZV2M_SAMPLL4_CLK1 0x104
|
||||
#define RZV2M_SAMPLL4_CLK2 0x108
|
||||
|
||||
#define PLL4_CONF (RZV2M_SAMPLL4_CLK1 << 22 | RZV2M_SAMPLL4_CLK2 << 12)
|
||||
|
||||
#define DIV_A DDIV_PACK(0x200, 0, 3)
|
||||
#define DIV_B DDIV_PACK(0x204, 0, 2)
|
||||
#define DIV_D DDIV_PACK(0x204, 4, 2)
|
||||
@@ -131,7 +126,7 @@ static const struct cpg_core_clk r9a09g011_core_clks[] __initconst = {
|
||||
DEF_FIXED(".pll2_400", CLK_PLL2_400, CLK_PLL2_800, 1, 2),
|
||||
DEF_FIXED(".pll2_200", CLK_PLL2_200, CLK_PLL2_800, 1, 4),
|
||||
DEF_FIXED(".pll2_100", CLK_PLL2_100, CLK_PLL2_800, 1, 8),
|
||||
DEF_SAMPLL(".pll4", CLK_PLL4, CLK_MAIN_2, PLL4_CONF),
|
||||
DEF_SAMPLL(".pll4", CLK_PLL4, CLK_MAIN_2, CPG_SAM_PLL_CONF(0x100)),
|
||||
|
||||
DEF_DIV_RO(".diva", CLK_DIV_A, CLK_PLL1, DIV_A, dtable_diva),
|
||||
DEF_DIV_RO(".divb", CLK_DIV_B, CLK_PLL2_400, DIV_B, dtable_divb),
|
||||
|
||||
@@ -6,6 +6,7 @@
|
||||
*/
|
||||
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/clk/renesas.h>
|
||||
#include <linux/device.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/kernel.h>
|
||||
@@ -30,6 +31,8 @@ enum clk_ids {
|
||||
CLK_PLLCA55,
|
||||
CLK_PLLVDO,
|
||||
CLK_PLLETH,
|
||||
CLK_PLLDSI0,
|
||||
CLK_PLLDSI1,
|
||||
|
||||
/* Internal Core Clocks */
|
||||
CLK_PLLCM33_DIV3,
|
||||
@@ -57,6 +60,8 @@ enum clk_ids {
|
||||
CLK_PLLETH_DIV_125_FIX,
|
||||
CLK_CSDIV_PLLETH_GBE0,
|
||||
CLK_CSDIV_PLLETH_GBE1,
|
||||
CLK_SMUX2_DSI0_CLK,
|
||||
CLK_SMUX2_DSI1_CLK,
|
||||
CLK_SMUX2_GBE0_TXCLK,
|
||||
CLK_SMUX2_GBE0_RXCLK,
|
||||
CLK_SMUX2_GBE1_TXCLK,
|
||||
@@ -64,6 +69,12 @@ enum clk_ids {
|
||||
CLK_PLLDTY_DIV16,
|
||||
CLK_PLLVDO_CRU0,
|
||||
CLK_PLLVDO_GPU,
|
||||
CLK_PLLETH_DIV4_LPCLK,
|
||||
CLK_PLLETH_LPCLK,
|
||||
CLK_PLLDSI0_DIV7,
|
||||
CLK_PLLDSI1_DIV7,
|
||||
CLK_PLLDSI0_CSDIV,
|
||||
CLK_PLLDSI1_CSDIV,
|
||||
|
||||
/* Module Clocks */
|
||||
MOD_CLK_BASE,
|
||||
@@ -91,6 +102,18 @@ static const struct clk_div_table dtable_2_16[] = {
|
||||
{0, 0},
|
||||
};
|
||||
|
||||
static const struct clk_div_table dtable_2_16_plldsi[] = {
|
||||
{0, 2},
|
||||
{1, 4},
|
||||
{2, 6},
|
||||
{3, 8},
|
||||
{4, 10},
|
||||
{5, 12},
|
||||
{6, 14},
|
||||
{7, 16},
|
||||
{0, 0},
|
||||
};
|
||||
|
||||
static const struct clk_div_table dtable_2_64[] = {
|
||||
{0, 2},
|
||||
{1, 4},
|
||||
@@ -107,7 +130,23 @@ static const struct clk_div_table dtable_2_100[] = {
|
||||
{0, 0},
|
||||
};
|
||||
|
||||
static const struct clk_div_table dtable_16_128[] = {
|
||||
{0, 16},
|
||||
{1, 32},
|
||||
{2, 64},
|
||||
{3, 128},
|
||||
{0, 0},
|
||||
};
|
||||
|
||||
RZG3E_CPG_PLL_DSI0_LIMITS(rzg3e_cpg_pll_dsi0_limits);
|
||||
RZG3E_CPG_PLL_DSI1_LIMITS(rzg3e_cpg_pll_dsi1_limits);
|
||||
|
||||
#define PLLDSI0 PLL_PACK_LIMITS(0xc0, 1, 0, &rzg3e_cpg_pll_dsi0_limits)
|
||||
#define PLLDSI1 PLL_PACK_LIMITS(0x160, 1, 1, &rzg3e_cpg_pll_dsi1_limits)
|
||||
|
||||
/* Mux clock tables */
|
||||
static const char * const smux2_dsi0_clk[] = { ".plldsi0_div7", ".plldsi0_csdiv" };
|
||||
static const char * const smux2_dsi1_clk[] = { ".plldsi1_div7", ".plldsi1_csdiv" };
|
||||
static const char * const smux2_gbe0_rxclk[] = { ".plleth_gbe0", "et0_rxclk" };
|
||||
static const char * const smux2_gbe0_txclk[] = { ".plleth_gbe0", "et0_txclk" };
|
||||
static const char * const smux2_gbe1_rxclk[] = { ".plleth_gbe1", "et1_rxclk" };
|
||||
@@ -128,6 +167,8 @@ static const struct cpg_core_clk r9a09g047_core_clks[] __initconst = {
|
||||
DEF_PLL(".pllca55", CLK_PLLCA55, CLK_QEXTAL, PLLCA55),
|
||||
DEF_FIXED(".plleth", CLK_PLLETH, CLK_QEXTAL, 125, 3),
|
||||
DEF_FIXED(".pllvdo", CLK_PLLVDO, CLK_QEXTAL, 105, 2),
|
||||
DEF_PLLDSI(".plldsi0", CLK_PLLDSI0, CLK_QEXTAL, PLLDSI0),
|
||||
DEF_PLLDSI(".plldsi1", CLK_PLLDSI1, CLK_QEXTAL, PLLDSI1),
|
||||
|
||||
/* Internal Core Clocks */
|
||||
DEF_FIXED(".pllcm33_div3", CLK_PLLCM33_DIV3, CLK_PLLCM33, 1, 3),
|
||||
@@ -171,6 +212,21 @@ static const struct cpg_core_clk r9a09g047_core_clks[] __initconst = {
|
||||
DEF_DDIV(".pllvdo_cru0", CLK_PLLVDO_CRU0, CLK_PLLVDO, CDDIV3_DIVCTL3, dtable_2_4),
|
||||
DEF_DDIV(".pllvdo_gpu", CLK_PLLVDO_GPU, CLK_PLLVDO, CDDIV3_DIVCTL1, dtable_2_64),
|
||||
|
||||
DEF_FIXED(".plleth_div4_lpclk", CLK_PLLETH_DIV4_LPCLK, CLK_PLLETH, 1, 4),
|
||||
DEF_CSDIV(".plleth_lpclk", CLK_PLLETH_LPCLK, CLK_PLLETH_DIV4_LPCLK,
|
||||
CSDIV0_DIVCTL2, dtable_16_128),
|
||||
|
||||
DEF_PLLDSI_DIV(".plldsi0_csdiv", CLK_PLLDSI0_CSDIV, CLK_PLLDSI0,
|
||||
CSDIV1_DIVCTL2, dtable_2_16_plldsi),
|
||||
DEF_PLLDSI_DIV(".plldsi1_csdiv", CLK_PLLDSI1_CSDIV, CLK_PLLDSI1,
|
||||
CSDIV1_DIVCTL3, dtable_2_16_plldsi),
|
||||
DEF_FIXED(".plldsi0_div7", CLK_PLLDSI0_DIV7, CLK_PLLDSI0, 1, 7),
|
||||
DEF_FIXED(".plldsi1_div7", CLK_PLLDSI1_DIV7, CLK_PLLDSI1, 1, 7),
|
||||
DEF_PLLDSI_SMUX(".smux2_dsi0_clk", CLK_SMUX2_DSI0_CLK,
|
||||
SSEL3_SELCTL0, smux2_dsi0_clk),
|
||||
DEF_PLLDSI_SMUX(".smux2_dsi1_clk", CLK_SMUX2_DSI1_CLK,
|
||||
SSEL3_SELCTL1, smux2_dsi1_clk),
|
||||
|
||||
/* Core Clocks */
|
||||
DEF_FIXED("sys_0_pclk", R9A09G047_SYS_0_PCLK, CLK_QEXTAL, 1, 1),
|
||||
DEF_DDIV("ca55_0_coreclk0", R9A09G047_CA55_0_CORECLK0, CLK_PLLCA55,
|
||||
@@ -452,6 +508,22 @@ static const struct rzv2h_mod_clk r9a09g047_mod_clks[] __initconst = {
|
||||
BUS_MSTOP(9, BIT(4))),
|
||||
DEF_MOD("cru_0_pclk", CLK_PLLDTY_DIV16, 13, 4, 6, 20,
|
||||
BUS_MSTOP(9, BIT(4))),
|
||||
DEF_MOD("dsi_0_pclk", CLK_PLLDTY_DIV16, 14, 8, 7, 8,
|
||||
BUS_MSTOP(9, BIT(15) | BIT(14))),
|
||||
DEF_MOD("dsi_0_aclk", CLK_PLLDTY_ACPU_DIV2, 14, 9, 7, 9,
|
||||
BUS_MSTOP(9, BIT(15) | BIT(14))),
|
||||
DEF_MOD("dsi_0_vclk1", CLK_SMUX2_DSI0_CLK, 14, 10, 7, 10,
|
||||
BUS_MSTOP(9, BIT(15) | BIT(14))),
|
||||
DEF_MOD("dsi_0_lpclk", CLK_PLLETH_LPCLK, 14, 11, 7, 11,
|
||||
BUS_MSTOP(9, BIT(15) | BIT(14))),
|
||||
DEF_MOD("dsi_0_pllref_clk", CLK_QEXTAL, 14, 12, 7, 12,
|
||||
BUS_MSTOP(9, BIT(15) | BIT(14))),
|
||||
DEF_MOD("lcdc_0_clk_a", CLK_PLLDTY_ACPU_DIV2, 14, 13, 7, 13,
|
||||
BUS_MSTOP(10, BIT(3) | BIT(2) | BIT(1))),
|
||||
DEF_MOD("lcdc_0_clk_p", CLK_PLLDTY_DIV16, 14, 14, 7, 14,
|
||||
BUS_MSTOP(10, BIT(3) | BIT(2) | BIT(1))),
|
||||
DEF_MOD("lcdc_0_clk_d", CLK_SMUX2_DSI0_CLK, 14, 15, 7, 15,
|
||||
BUS_MSTOP(10, BIT(3) | BIT(2) | BIT(1))),
|
||||
DEF_MOD("ge3d_clk", CLK_PLLVDO_GPU, 15, 0, 7, 16,
|
||||
BUS_MSTOP(3, BIT(4))),
|
||||
DEF_MOD("ge3d_axi_clk", CLK_PLLDTY_ACPU_DIV2, 15, 1, 7, 17,
|
||||
@@ -460,6 +532,14 @@ static const struct rzv2h_mod_clk r9a09g047_mod_clks[] __initconst = {
|
||||
BUS_MSTOP(3, BIT(4))),
|
||||
DEF_MOD("tsu_1_pclk", CLK_QEXTAL, 16, 10, 8, 10,
|
||||
BUS_MSTOP(2, BIT(15))),
|
||||
DEF_MOD("dsi_0_vclk2", CLK_SMUX2_DSI1_CLK, 25, 0, 10, 21,
|
||||
BUS_MSTOP(9, BIT(15) | BIT(14))),
|
||||
DEF_MOD("lcdc_1_clk_a", CLK_PLLDTY_ACPU_DIV2, 26, 8, 10, 30,
|
||||
BUS_MSTOP(13, BIT(5) | BIT(4) | BIT(3))),
|
||||
DEF_MOD("lcdc_1_clk_p", CLK_PLLDTY_DIV16, 26, 9, 10, 31,
|
||||
BUS_MSTOP(13, BIT(5) | BIT(4) | BIT(3))),
|
||||
DEF_MOD("lcdc_1_clk_d", CLK_SMUX2_DSI1_CLK, 26, 10, 11, 0,
|
||||
BUS_MSTOP(13, BIT(5) | BIT(4) | BIT(3))),
|
||||
};
|
||||
|
||||
static const struct rzv2h_reset r9a09g047_resets[] __initconst = {
|
||||
@@ -535,10 +615,14 @@ static const struct rzv2h_reset r9a09g047_resets[] __initconst = {
|
||||
DEF_RST(12, 5, 5, 22), /* CRU_0_PRESETN */
|
||||
DEF_RST(12, 6, 5, 23), /* CRU_0_ARESETN */
|
||||
DEF_RST(12, 7, 5, 24), /* CRU_0_S_RESETN */
|
||||
DEF_RST(13, 7, 6, 8), /* DSI_0_PRESETN */
|
||||
DEF_RST(13, 8, 6, 9), /* DSI_0_ARESETN */
|
||||
DEF_RST(13, 12, 6, 13), /* LCDC_0_RESET_N */
|
||||
DEF_RST(13, 13, 6, 14), /* GE3D_RESETN */
|
||||
DEF_RST(13, 14, 6, 15), /* GE3D_AXI_RESETN */
|
||||
DEF_RST(13, 15, 6, 16), /* GE3D_ACE_RESETN */
|
||||
DEF_RST(15, 8, 7, 9), /* TSU_1_PRESETN */
|
||||
DEF_RST(17, 14, 8, 15), /* LCDC_1_RESET_N */
|
||||
};
|
||||
|
||||
const struct rzv2h_cpg_info r9a09g047_cpg_info __initconst = {
|
||||
|
||||
@@ -257,6 +257,7 @@ static const struct mssr_mod_clk r9a09g077_mod_clks[] __initconst = {
|
||||
DEF_MOD("spi0", 104, CLK_SPI0ASYNC),
|
||||
DEF_MOD("spi1", 105, CLK_SPI1ASYNC),
|
||||
DEF_MOD("spi2", 106, CLK_SPI2ASYNC),
|
||||
DEF_MOD("mtu3", 200, R9A09G077_CLK_PCLKH),
|
||||
DEF_MOD("adc0", 206, R9A09G077_CLK_PCLKH),
|
||||
DEF_MOD("adc1", 207, R9A09G077_CLK_PCLKH),
|
||||
DEF_MOD("adc2", 225, R9A09G077_CLK_PCLKM),
|
||||
|
||||
@@ -370,6 +370,9 @@ struct clk *cpg_mssr_clk_src_twocell_get(struct of_phandle_args *clkspec,
|
||||
struct clk *clk;
|
||||
int range_check;
|
||||
|
||||
if (clkspec->args_count != 2)
|
||||
return ERR_PTR(-EINVAL);
|
||||
|
||||
switch (clkspec->args[0]) {
|
||||
case CPG_CORE:
|
||||
type = "core";
|
||||
|
||||
@@ -58,15 +58,22 @@
|
||||
#define RZG3S_DIV_NF GENMASK(12, 1)
|
||||
#define RZG3S_SEL_PLL BIT(0)
|
||||
|
||||
#define CPG_PLL1_SETTING_OFFSET(conf) FIELD_GET(GENMASK(11, 0), (conf))
|
||||
#define CPG_PLL_STBY_OFFSET(conf) FIELD_GET(GENMASK(23, 12), (conf))
|
||||
#define CPG_PLL_STBY_RESETB_WEN BIT(16)
|
||||
#define CPG_PLL_STBY_RESETB BIT(0)
|
||||
#define CPG_PLL_CLK1_OFFSET(x) (CPG_PLL_STBY_OFFSET(x) + 0x4)
|
||||
#define CPG_PLL_CLK2_OFFSET(x) (CPG_PLL_STBY_OFFSET(x) + 0x8)
|
||||
#define CPG_PLL_MON_OFFSET(x) (CPG_PLL_STBY_OFFSET(x) + 0xc)
|
||||
#define CPG_PLL_MON_LOCK BIT(4)
|
||||
#define CPG_PLL_MON_RESETB BIT(0)
|
||||
|
||||
#define CLK_ON_R(reg) (reg)
|
||||
#define CLK_MON_R(reg) (0x180 + (reg))
|
||||
#define CLK_RST_R(reg) (reg)
|
||||
#define CLK_MRST_R(reg) (0x180 + (reg))
|
||||
|
||||
#define GET_REG_OFFSET(val) ((val >> 20) & 0xfff)
|
||||
#define GET_REG_SAMPLL_CLK1(val) ((val >> 22) & 0xfff)
|
||||
#define GET_REG_SAMPLL_CLK2(val) ((val >> 12) & 0xfff)
|
||||
#define GET_REG_SAMPLL_SETTING(val) ((val) & 0xfff)
|
||||
|
||||
#define CPG_WEN_BIT BIT(16)
|
||||
|
||||
@@ -1086,8 +1093,8 @@ static unsigned long rzg2l_cpg_pll_clk_recalc_rate(struct clk_hw *hw,
|
||||
if (pll_clk->type != CLK_TYPE_SAM_PLL)
|
||||
return parent_rate;
|
||||
|
||||
val1 = readl(priv->base + GET_REG_SAMPLL_CLK1(pll_clk->conf));
|
||||
val2 = readl(priv->base + GET_REG_SAMPLL_CLK2(pll_clk->conf));
|
||||
val1 = readl(priv->base + CPG_PLL_CLK1_OFFSET(pll_clk->conf));
|
||||
val2 = readl(priv->base + CPG_PLL_CLK2_OFFSET(pll_clk->conf));
|
||||
|
||||
rate = mul_u64_u32_shr(parent_rate, (MDIV(val1) << 16) + KDIV(val1),
|
||||
16 + SDIV(val2));
|
||||
@@ -1107,17 +1114,14 @@ static unsigned long rzg3s_cpg_pll_clk_recalc_rate(struct clk_hw *hw,
|
||||
u32 nir, nfr, mr, pr, val, setting;
|
||||
u64 rate;
|
||||
|
||||
if (pll_clk->type != CLK_TYPE_G3S_PLL)
|
||||
return parent_rate;
|
||||
|
||||
setting = GET_REG_SAMPLL_SETTING(pll_clk->conf);
|
||||
setting = CPG_PLL1_SETTING_OFFSET(pll_clk->conf);
|
||||
if (setting) {
|
||||
val = readl(priv->base + setting);
|
||||
if (val & RZG3S_SEL_PLL)
|
||||
return pll_clk->default_rate;
|
||||
}
|
||||
|
||||
val = readl(priv->base + GET_REG_SAMPLL_CLK1(pll_clk->conf));
|
||||
val = readl(priv->base + CPG_PLL_CLK1_OFFSET(pll_clk->conf));
|
||||
|
||||
pr = 1 << FIELD_GET(RZG3S_DIV_P, val);
|
||||
/* Hardware interprets values higher than 8 as p = 16. */
|
||||
@@ -1178,6 +1182,61 @@ rzg2l_cpg_pll_clk_register(const struct cpg_core_clk *core,
|
||||
return pll_clk->hw.clk;
|
||||
}
|
||||
|
||||
static int rzg3l_cpg_pll_clk_is_enabled(struct clk_hw *hw)
|
||||
{
|
||||
struct pll_clk *pll_clk = to_pll(hw);
|
||||
struct rzg2l_cpg_priv *priv = pll_clk->priv;
|
||||
u32 val = readl(priv->base + CPG_PLL_MON_OFFSET(pll_clk->conf));
|
||||
u32 mon_val = CPG_PLL_MON_RESETB | CPG_PLL_MON_LOCK;
|
||||
|
||||
/* Ensure both RESETB and LOCK bits are set */
|
||||
return (mon_val == (val & mon_val));
|
||||
}
|
||||
|
||||
static int rzg3l_cpg_pll_clk_endisable(struct clk_hw *hw, bool enable)
|
||||
{
|
||||
struct pll_clk *pll_clk = to_pll(hw);
|
||||
struct rzg2l_cpg_priv *priv = pll_clk->priv;
|
||||
u32 mon_mask = CPG_PLL_MON_RESETB | CPG_PLL_MON_LOCK;
|
||||
u32 val = CPG_PLL_STBY_RESETB_WEN;
|
||||
u32 stby_offset, mon_offset;
|
||||
u32 mon_val = 0;
|
||||
int ret;
|
||||
|
||||
stby_offset = CPG_PLL_STBY_OFFSET(pll_clk->conf);
|
||||
mon_offset = CPG_PLL_MON_OFFSET(pll_clk->conf);
|
||||
|
||||
if (enable) {
|
||||
val |= CPG_PLL_STBY_RESETB;
|
||||
mon_val = mon_mask;
|
||||
}
|
||||
|
||||
writel(val, priv->base + stby_offset);
|
||||
|
||||
/* ensure PLL is in normal/standby mode */
|
||||
ret = readl_poll_timeout_atomic(priv->base + mon_offset, val,
|
||||
mon_val == (val & mon_mask), 10, 100);
|
||||
if (ret)
|
||||
dev_err(priv->dev, "Failed to %s PLL 0x%x/%pC\n", enable ?
|
||||
"enable" : "disable", stby_offset, hw->clk);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int rzg3l_cpg_pll_clk_enable(struct clk_hw *hw)
|
||||
{
|
||||
if (rzg3l_cpg_pll_clk_is_enabled(hw))
|
||||
return 0;
|
||||
|
||||
return rzg3l_cpg_pll_clk_endisable(hw, true);
|
||||
}
|
||||
|
||||
static const struct clk_ops rzg3l_cpg_pll_ops = {
|
||||
.is_enabled = rzg3l_cpg_pll_clk_is_enabled,
|
||||
.enable = rzg3l_cpg_pll_clk_enable,
|
||||
.recalc_rate = rzg3s_cpg_pll_clk_recalc_rate,
|
||||
};
|
||||
|
||||
static struct clk
|
||||
*rzg2l_cpg_clk_src_twocell_get(struct of_phandle_args *clkspec,
|
||||
void *data)
|
||||
@@ -1261,6 +1320,9 @@ rzg2l_cpg_register_core_clk(const struct cpg_core_clk *core,
|
||||
case CLK_TYPE_SAM_PLL:
|
||||
clk = rzg2l_cpg_pll_clk_register(core, priv, &rzg2l_cpg_pll_ops);
|
||||
break;
|
||||
case CLK_TYPE_G3L_PLL:
|
||||
clk = rzg2l_cpg_pll_clk_register(core, priv, &rzg3l_cpg_pll_ops);
|
||||
break;
|
||||
case CLK_TYPE_G3S_PLL:
|
||||
clk = rzg2l_cpg_pll_clk_register(core, priv, &rzg3s_cpg_pll_ops);
|
||||
break;
|
||||
@@ -1340,10 +1402,10 @@ struct mod_clock {
|
||||
#define to_mod_clock(_hw) container_of(_hw, struct mod_clock, hw)
|
||||
|
||||
#define for_each_mod_clock(mod_clock, hw, priv) \
|
||||
for (unsigned int i = 0; (priv) && i < (priv)->num_mod_clks; i++) \
|
||||
if ((priv)->clks[(priv)->num_core_clks + i] == ERR_PTR(-ENOENT)) \
|
||||
for (unsigned int __i = 0; (priv) && __i < (priv)->num_mod_clks; __i++) \
|
||||
if ((priv)->clks[(priv)->num_core_clks + __i] == ERR_PTR(-ENOENT)) \
|
||||
continue; \
|
||||
else if (((hw) = __clk_get_hw((priv)->clks[(priv)->num_core_clks + i])) && \
|
||||
else if (((hw) = __clk_get_hw((priv)->clks[(priv)->num_core_clks + __i])) && \
|
||||
((mod_clock) = to_mod_clock(hw)))
|
||||
|
||||
/* Need to be called with a lock held to avoid concurrent access to mstop->usecnt. */
|
||||
|
||||
@@ -58,11 +58,8 @@
|
||||
#define CPG_CLKSTATUS_SELSDHI0_STS BIT(28)
|
||||
#define CPG_CLKSTATUS_SELSDHI1_STS BIT(29)
|
||||
|
||||
/* n = 0/1/2 for PLL1/4/6 */
|
||||
#define CPG_SAMPLL_CLK1(n) (0x04 + (16 * n))
|
||||
#define CPG_SAMPLL_CLK2(n) (0x08 + (16 * n))
|
||||
|
||||
#define PLL146_CONF(n) (CPG_SAMPLL_CLK1(n) << 22 | CPG_SAMPLL_CLK2(n) << 12)
|
||||
#define CPG_SAM_PLL_CONF(stby) ((stby) << 12)
|
||||
#define CPG_PLL_CONF(stby, setting) ((stby) << 12 | (setting))
|
||||
|
||||
#define DDIV_PACK(offset, bitpos, size) \
|
||||
(((offset) << 20) | ((bitpos) << 12) | ((size) << 8))
|
||||
@@ -123,6 +120,7 @@ enum clk_types {
|
||||
CLK_TYPE_IN, /* External Clock Input */
|
||||
CLK_TYPE_FF, /* Fixed Factor Clock */
|
||||
CLK_TYPE_SAM_PLL,
|
||||
CLK_TYPE_G3L_PLL,
|
||||
CLK_TYPE_G3S_PLL,
|
||||
|
||||
/* Clock with divider */
|
||||
@@ -152,6 +150,9 @@ enum clk_types {
|
||||
DEF_TYPE(_name, _id, _type, .parent = _parent)
|
||||
#define DEF_SAMPLL(_name, _id, _parent, _conf) \
|
||||
DEF_TYPE(_name, _id, CLK_TYPE_SAM_PLL, .parent = _parent, .conf = _conf)
|
||||
#define DEF_G3L_PLL(_name, _id, _parent, _conf, _default_rate) \
|
||||
DEF_TYPE(_name, _id, CLK_TYPE_G3L_PLL, .parent = _parent, .conf = _conf, \
|
||||
.default_rate = _default_rate)
|
||||
#define DEF_G3S_PLL(_name, _id, _parent, _conf, _default_rate) \
|
||||
DEF_TYPE(_name, _id, CLK_TYPE_G3S_PLL, .parent = _parent, .conf = _conf, \
|
||||
.default_rate = _default_rate)
|
||||
@@ -174,11 +175,14 @@ enum clk_types {
|
||||
.invalid_rate = _invalid_rate, \
|
||||
.max_rate = _max_rate, .flag = (_clk_flags), \
|
||||
.notifier = _notif)
|
||||
#define DEF_MUX(_name, _id, _conf, _parent_names) \
|
||||
#define DEF_MUX_FLAGS(_name, _id, _conf, _parent_names, _flag) \
|
||||
DEF_TYPE(_name, _id, CLK_TYPE_MUX, .conf = _conf, \
|
||||
.parent_names = _parent_names, \
|
||||
.num_parents = ARRAY_SIZE(_parent_names), \
|
||||
.mux_flags = CLK_MUX_HIWORD_MASK)
|
||||
.mux_flags = CLK_MUX_HIWORD_MASK, \
|
||||
.flag = _flag)
|
||||
#define DEF_MUX(_name, _id, _conf, _parent_names) \
|
||||
DEF_MUX_FLAGS(_name, _id, _conf, _parent_names, 0)
|
||||
#define DEF_MUX_RO(_name, _id, _conf, _parent_names) \
|
||||
DEF_TYPE(_name, _id, CLK_TYPE_MUX, .conf = _conf, \
|
||||
.parent_names = _parent_names, \
|
||||
|
||||
@@ -76,6 +76,11 @@
|
||||
/* On RZ/G3E SoC we have two DSI PLLs */
|
||||
#define MAX_CPG_DSI_PLL 2
|
||||
|
||||
#define CPG_PLLDSI_SMUX_LVDS_DUTY_NUM 4
|
||||
#define CPG_PLLDSI_SMUX_LVDS_DUTY_DEN 7
|
||||
#define CPG_PLLDSI_SMUX_DSI_RGB_DUTY_NUM 1
|
||||
#define CPG_PLLDSI_SMUX_DSI_RGB_DUTY_DEN 2
|
||||
|
||||
/**
|
||||
* struct rzv2h_pll_dsi_info - PLL DSI information, holds the limits and parameters
|
||||
*
|
||||
@@ -418,6 +423,20 @@ bool rzv2h_get_pll_divs_pars(const struct rzv2h_pll_limits *limits,
|
||||
}
|
||||
EXPORT_SYMBOL_NS_GPL(rzv2h_get_pll_divs_pars, "RZV2H_CPG");
|
||||
|
||||
/**
|
||||
* struct rzv2h_plldsi_mux_clk - PLL DSI MUX clock
|
||||
*
|
||||
* @priv: CPG private data
|
||||
* @mux: mux clk
|
||||
*/
|
||||
struct rzv2h_plldsi_mux_clk {
|
||||
struct rzv2h_cpg_priv *priv;
|
||||
struct clk_mux mux;
|
||||
};
|
||||
|
||||
#define to_plldsi_clk_mux(_mux) \
|
||||
container_of(_mux, struct rzv2h_plldsi_mux_clk, mux)
|
||||
|
||||
static unsigned long rzv2h_cpg_plldsi_div_recalc_rate(struct clk_hw *hw,
|
||||
unsigned long parent_rate)
|
||||
{
|
||||
@@ -649,6 +668,165 @@ static int rzv2h_cpg_plldsi_set_rate(struct clk_hw *hw, unsigned long rate,
|
||||
return rzv2h_cpg_pll_set_rate(pll_clk, &dsi_info->pll_dsi_parameters.pll, true);
|
||||
}
|
||||
|
||||
static u8 rzv2h_cpg_plldsi_smux_get_parent(struct clk_hw *hw)
|
||||
{
|
||||
return clk_mux_ops.get_parent(hw);
|
||||
}
|
||||
|
||||
static int rzv2h_cpg_plldsi_smux_set_parent(struct clk_hw *hw, u8 index)
|
||||
{
|
||||
return clk_mux_ops.set_parent(hw, index);
|
||||
}
|
||||
|
||||
static int rzv2h_cpg_plldsi_smux_lvds_determine_rate(struct rzv2h_cpg_priv *priv,
|
||||
struct pll_clk *pll_clk,
|
||||
struct clk_rate_request *req)
|
||||
{
|
||||
struct rzv2h_pll_div_pars *dsi_params;
|
||||
struct rzv2h_pll_dsi_info *dsi_info;
|
||||
u8 lvds_table[] = { 7 };
|
||||
u64 rate_millihz;
|
||||
|
||||
dsi_info = &priv->pll_dsi_info[pll_clk->pll.instance];
|
||||
dsi_params = &dsi_info->pll_dsi_parameters;
|
||||
|
||||
rate_millihz = mul_u32_u32(req->rate, MILLI);
|
||||
if (!rzv2h_get_pll_divs_pars(dsi_info->pll_dsi_limits, dsi_params,
|
||||
lvds_table, ARRAY_SIZE(lvds_table), rate_millihz)) {
|
||||
dev_err(priv->dev, "failed to determine rate for req->rate: %lu\n",
|
||||
req->rate);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
req->rate = DIV_ROUND_CLOSEST_ULL(dsi_params->div.freq_millihz, MILLI);
|
||||
req->best_parent_rate = req->rate;
|
||||
dsi_info->req_pll_dsi_rate = req->best_parent_rate * dsi_params->div.divider_value;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rzv2h_cpg_plldsi_smux_determine_rate(struct clk_hw *hw,
|
||||
struct clk_rate_request *req)
|
||||
{
|
||||
struct clk_mux *mux = to_clk_mux(hw);
|
||||
struct rzv2h_plldsi_mux_clk *dsi_mux = to_plldsi_clk_mux(mux);
|
||||
struct pll_clk *pll_clk = to_pll(clk_hw_get_parent(hw));
|
||||
struct rzv2h_cpg_priv *priv = dsi_mux->priv;
|
||||
|
||||
/*
|
||||
* For LVDS output (parent index 0), calculate PLL parameters with
|
||||
* fixed divider value of 7. For DSI/RGB output (parent index 1) skip
|
||||
* PLL calculation here as it's handled by determine_rate of the
|
||||
* divider (up one level).
|
||||
*/
|
||||
if (!clk_mux_ops.get_parent(hw))
|
||||
return rzv2h_cpg_plldsi_smux_lvds_determine_rate(priv, pll_clk, req);
|
||||
|
||||
req->best_parent_rate = req->rate;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rzv2h_cpg_plldsi_smux_get_duty_cycle(struct clk_hw *hw,
|
||||
struct clk_duty *duty)
|
||||
{
|
||||
u8 parent = clk_mux_ops.get_parent(hw);
|
||||
|
||||
/*
|
||||
* CDIV7_DSIx_CLK - LVDS path (div7) - duty 4/7.
|
||||
* CSDIV_DSIx - DSI/RGB path (csdiv) - duty 1/2.
|
||||
*/
|
||||
if (parent == 0) {
|
||||
duty->num = CPG_PLLDSI_SMUX_LVDS_DUTY_NUM;
|
||||
duty->den = CPG_PLLDSI_SMUX_LVDS_DUTY_DEN;
|
||||
} else {
|
||||
duty->num = CPG_PLLDSI_SMUX_DSI_RGB_DUTY_NUM;
|
||||
duty->den = CPG_PLLDSI_SMUX_DSI_RGB_DUTY_DEN;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rzv2h_cpg_plldsi_smux_set_duty_cycle(struct clk_hw *hw,
|
||||
struct clk_duty *duty)
|
||||
{
|
||||
struct clk_hw *parent_hw;
|
||||
u8 parent_idx;
|
||||
|
||||
/*
|
||||
* Select parent based on requested duty cycle:
|
||||
* - If duty > 50% (num/den > 1/2), select LVDS path (parent 0)
|
||||
* - Otherwise, select DSI/RGB path (parent 1)
|
||||
*/
|
||||
if (duty->num * CPG_PLLDSI_SMUX_DSI_RGB_DUTY_DEN >
|
||||
duty->den * CPG_PLLDSI_SMUX_DSI_RGB_DUTY_NUM)
|
||||
parent_idx = 0;
|
||||
else
|
||||
parent_idx = 1;
|
||||
|
||||
if (parent_idx >= clk_hw_get_num_parents(hw))
|
||||
return -EINVAL;
|
||||
|
||||
parent_hw = clk_hw_get_parent_by_index(hw, parent_idx);
|
||||
if (!parent_hw)
|
||||
return -EINVAL;
|
||||
|
||||
return clk_hw_set_parent(hw, parent_hw);
|
||||
}
|
||||
|
||||
static const struct clk_ops rzv2h_cpg_plldsi_smux_ops = {
|
||||
.determine_rate = rzv2h_cpg_plldsi_smux_determine_rate,
|
||||
.get_parent = rzv2h_cpg_plldsi_smux_get_parent,
|
||||
.set_parent = rzv2h_cpg_plldsi_smux_set_parent,
|
||||
.get_duty_cycle = rzv2h_cpg_plldsi_smux_get_duty_cycle,
|
||||
.set_duty_cycle = rzv2h_cpg_plldsi_smux_set_duty_cycle,
|
||||
};
|
||||
|
||||
static struct clk * __init
|
||||
rzv2h_cpg_plldsi_smux_clk_register(const struct cpg_core_clk *core,
|
||||
struct rzv2h_cpg_priv *priv)
|
||||
{
|
||||
struct rzv2h_plldsi_mux_clk *clk_hw_data;
|
||||
struct clk_init_data init;
|
||||
struct clk_hw *clk_hw;
|
||||
struct smuxed smux;
|
||||
int ret;
|
||||
|
||||
smux = core->cfg.smux;
|
||||
|
||||
if (smux.shift + smux.width > 16) {
|
||||
dev_err(priv->dev, "mux value exceeds LOWORD field\n");
|
||||
return ERR_PTR(-EINVAL);
|
||||
}
|
||||
|
||||
clk_hw_data = devm_kzalloc(priv->dev, sizeof(*clk_hw_data), GFP_KERNEL);
|
||||
if (!clk_hw_data)
|
||||
return ERR_PTR(-ENOMEM);
|
||||
|
||||
clk_hw_data->priv = priv;
|
||||
|
||||
init.name = core->name;
|
||||
init.ops = &rzv2h_cpg_plldsi_smux_ops;
|
||||
init.flags = core->flag;
|
||||
init.parent_names = core->parent_names;
|
||||
init.num_parents = core->num_parents;
|
||||
|
||||
clk_hw_data->mux.reg = priv->base + smux.offset;
|
||||
|
||||
clk_hw_data->mux.shift = smux.shift;
|
||||
clk_hw_data->mux.mask = clk_div_mask(smux.width);
|
||||
clk_hw_data->mux.flags = core->mux_flags;
|
||||
clk_hw_data->mux.lock = &priv->rmw_lock;
|
||||
|
||||
clk_hw = &clk_hw_data->mux.hw;
|
||||
clk_hw->init = &init;
|
||||
|
||||
ret = devm_clk_hw_register(priv->dev, clk_hw);
|
||||
if (ret)
|
||||
return ERR_PTR(ret);
|
||||
|
||||
return clk_hw->clk;
|
||||
}
|
||||
|
||||
static int rzv2h_cpg_pll_clk_is_enabled(struct clk_hw *hw)
|
||||
{
|
||||
struct pll_clk *pll_clk = to_pll(hw);
|
||||
@@ -1085,6 +1263,9 @@ rzv2h_cpg_register_core_clk(const struct cpg_core_clk *core,
|
||||
case CLK_TYPE_PLLDSI_DIV:
|
||||
clk = rzv2h_cpg_plldsi_div_clk_register(core, priv);
|
||||
break;
|
||||
case CLK_TYPE_PLLDSI_SMUX:
|
||||
clk = rzv2h_cpg_plldsi_smux_clk_register(core, priv);
|
||||
break;
|
||||
default:
|
||||
goto fail;
|
||||
}
|
||||
|
||||
@@ -121,6 +121,7 @@ struct fixed_mod_conf {
|
||||
|
||||
#define CPG_SSEL0 (0x300)
|
||||
#define CPG_SSEL1 (0x304)
|
||||
#define CPG_SSEL3 (0x30C)
|
||||
#define CPG_CDDIV0 (0x400)
|
||||
#define CPG_CDDIV1 (0x404)
|
||||
#define CPG_CDDIV2 (0x408)
|
||||
@@ -148,6 +149,7 @@ struct fixed_mod_conf {
|
||||
#define CSDIV0_DIVCTL2 DDIV_PACK(CPG_CSDIV0, 8, 2, CSDIV_NO_MON)
|
||||
#define CSDIV0_DIVCTL3 DDIV_PACK_NO_RMW(CPG_CSDIV0, 12, 2, CSDIV_NO_MON)
|
||||
#define CSDIV1_DIVCTL2 DDIV_PACK(CPG_CSDIV1, 8, 4, CSDIV_NO_MON)
|
||||
#define CSDIV1_DIVCTL3 DDIV_PACK(CPG_CSDIV1, 12, 4, CSDIV_NO_MON)
|
||||
|
||||
#define SSEL0_SELCTL2 SMUX_PACK(CPG_SSEL0, 8, 1)
|
||||
#define SSEL0_SELCTL3 SMUX_PACK(CPG_SSEL0, 12, 1)
|
||||
@@ -155,6 +157,8 @@ struct fixed_mod_conf {
|
||||
#define SSEL1_SELCTL1 SMUX_PACK(CPG_SSEL1, 4, 1)
|
||||
#define SSEL1_SELCTL2 SMUX_PACK(CPG_SSEL1, 8, 1)
|
||||
#define SSEL1_SELCTL3 SMUX_PACK(CPG_SSEL1, 12, 1)
|
||||
#define SSEL3_SELCTL0 SMUX_PACK(CPG_SSEL3, 0, 1)
|
||||
#define SSEL3_SELCTL1 SMUX_PACK(CPG_SSEL3, 4, 1)
|
||||
|
||||
#define BUS_MSTOP_IDX_MASK GENMASK(31, 16)
|
||||
#define BUS_MSTOP_BITS_MASK GENMASK(15, 0)
|
||||
@@ -203,6 +207,7 @@ enum clk_types {
|
||||
CLK_TYPE_SMUX, /* Static Mux */
|
||||
CLK_TYPE_PLLDSI, /* PLLDSI */
|
||||
CLK_TYPE_PLLDSI_DIV, /* PLLDSI divider */
|
||||
CLK_TYPE_PLLDSI_SMUX, /* PLLDSI Static Mux */
|
||||
};
|
||||
|
||||
#define DEF_TYPE(_name, _id, _type...) \
|
||||
@@ -241,6 +246,13 @@ enum clk_types {
|
||||
.dtable = _dtable, \
|
||||
.parent = _parent, \
|
||||
.flag = CLK_SET_RATE_PARENT)
|
||||
#define DEF_PLLDSI_SMUX(_name, _id, _smux_packed, _parent_names) \
|
||||
DEF_TYPE(_name, _id, CLK_TYPE_PLLDSI_SMUX, \
|
||||
.cfg.smux = _smux_packed, \
|
||||
.parent_names = _parent_names, \
|
||||
.num_parents = ARRAY_SIZE(_parent_names), \
|
||||
.flag = CLK_SET_RATE_PARENT, \
|
||||
.mux_flags = CLK_MUX_HIWORD_MASK)
|
||||
|
||||
/**
|
||||
* struct rzv2h_mod_clk - Module Clocks definitions
|
||||
|
||||
@@ -259,6 +259,8 @@ static const struct stratix10_perip_cnt_clock agilex_main_perip_cnt_clks[] = {
|
||||
0, 0x3C, 0, 0, 0},
|
||||
{ AGILEX_NOC_FREE_CLK, "noc_free_clk", NULL, noc_free_mux, ARRAY_SIZE(noc_free_mux),
|
||||
0, 0x40, 0, 0, 0},
|
||||
{ AGILEX_L3_MAIN_FREE_CLK, "l3_main_free_clk", "noc_free_clk", NULL,
|
||||
1, 0, 0, 1, 0, 0},
|
||||
{ AGILEX_L4_SYS_FREE_CLK, "l4_sys_free_clk", NULL, noc_mux, ARRAY_SIZE(noc_mux), 0,
|
||||
0, 4, 0x30, 1},
|
||||
{ AGILEX_EMAC_A_FREE_CLK, "emaca_free_clk", NULL, emaca_free_mux, ARRAY_SIZE(emaca_free_mux),
|
||||
|
||||
220
include/dt-bindings/clock/canaan,k230-clk.h
Normal file
220
include/dt-bindings/clock/canaan,k230-clk.h
Normal file
@@ -0,0 +1,220 @@
|
||||
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
|
||||
/*
|
||||
* Kendryte Canaan K230 Clock Drivers
|
||||
*
|
||||
* Author: Xukai Wang <kingxukai@zohomail.com>
|
||||
*/
|
||||
|
||||
#ifndef __DT_BINDINGS_CANAAN_K230_CLOCK_H__
|
||||
#define __DT_BINDINGS_CANAAN_K230_CLOCK_H__
|
||||
|
||||
#define K230_CPU0_SRC_GATE 0
|
||||
#define K230_CPU0_PLIC_GATE 1
|
||||
#define K230_CPU0_NOC_DDRCP4_GATE 2
|
||||
#define K230_CPU0_APB_GATE 3
|
||||
#define K230_CPU0_SRC_RATE 4
|
||||
#define K230_CPU0_AXI_RATE 5
|
||||
#define K230_CPU0_PLIC_RATE 6
|
||||
#define K230_CPU0_APB_RATE 7
|
||||
#define K230_HS_SSI0_MUX 8
|
||||
#define K230_HS_USB_REF_MUX 9
|
||||
#define K230_HS_HCLK_HIGH_GATE 10
|
||||
#define K230_HS_HCLK_GATE 11
|
||||
#define K230_HS_SD0_AHB_GATE 12
|
||||
#define K230_HS_SD1_AHB_GATE 13
|
||||
#define K230_HS_SSI1_AHB_GATE 14
|
||||
#define K230_HS_SSI2_AHB_GATE 15
|
||||
#define K230_HS_USB0_AHB_GATE 16
|
||||
#define K230_HS_USB1_AHB_GATE 17
|
||||
#define K230_HS_SSI0_AXI_GATE 18
|
||||
#define K230_HS_SSI1_GATE 19
|
||||
#define K230_HS_SSI2_GATE 20
|
||||
#define K230_HS_QSPI_AXI_SRC_GATE 21
|
||||
#define K230_HS_SSI1_AXI_GATE 22
|
||||
#define K230_HS_SSI2_AXI_GATE 23
|
||||
#define K230_HS_SD_CARD_SRC_GATE 24
|
||||
#define K230_HS_SD0_CARD_GATE 25
|
||||
#define K230_HS_SD1_CARD_GATE 26
|
||||
#define K230_HS_SD_AXI_SRC_GATE 27
|
||||
#define K230_HS_SD0_AXI_GATE 28
|
||||
#define K230_HS_SD1_AXI_GATE 29
|
||||
#define K230_HS_SD0_BASE_GATE 30
|
||||
#define K230_HS_SD1_BASE_GATE 31
|
||||
#define K230_HS_SSI0_GATE 32
|
||||
#define K230_HS_SD_TIMER_SRC_GATE 33
|
||||
#define K230_HS_SD0_TIMER_GATE 34
|
||||
#define K230_HS_SD1_TIMER_GATE 35
|
||||
#define K230_HS_USB0_REF_GATE 36
|
||||
#define K230_HS_USB1_REF_GATE 37
|
||||
#define K230_HS_HCLK_HIGH_RATE 38
|
||||
#define K230_HS_HCLK_RATE 39
|
||||
#define K230_HS_SSI0_AXI_RATE 40
|
||||
#define K230_HS_SSI1_RATE 41
|
||||
#define K230_HS_SSI2_RATE 42
|
||||
#define K230_HS_QSPI_AXI_SRC_RATE 43
|
||||
#define K230_HS_SD_CARD_SRC_RATE 44
|
||||
#define K230_HS_SD_AXI_SRC_RATE 45
|
||||
#define K230_HS_USB_REF_50M_RATE 46
|
||||
#define K230_HS_SD_TIMER_SRC_RATE 47
|
||||
#define K230_TIMER0_MUX 48
|
||||
#define K230_TIMER1_MUX 49
|
||||
#define K230_TIMER2_MUX 50
|
||||
#define K230_TIMER3_MUX 51
|
||||
#define K230_TIMER4_MUX 52
|
||||
#define K230_TIMER5_MUX 53
|
||||
#define K230_SHRM_SRAM_MUX 54
|
||||
#define K230_DDRC_SRC_MUX 55
|
||||
#define K230_AI_SRC_MUX 56
|
||||
#define K230_CAMERA0_MUX 57
|
||||
#define K230_CAMERA1_MUX 58
|
||||
#define K230_CAMERA2_MUX 59
|
||||
#define K230_CPU1_SRC_MUX 60
|
||||
#define K230_CPU1_SRC_GATE 61
|
||||
#define K230_CPU1_PLIC_GATE 62
|
||||
#define K230_CPU1_APB_GATE 63
|
||||
#define K230_CPU1_SRC_RATE 64
|
||||
#define K230_CPU1_AXI_RATE 65
|
||||
#define K230_CPU1_PLIC_RATE 66
|
||||
#define K230_PMU_APB_GATE 67
|
||||
#define K230_LS_APB_SRC_GATE 68
|
||||
#define K230_LS_UART0_APB_GATE 69
|
||||
#define K230_LS_UART1_APB_GATE 70
|
||||
#define K230_LS_UART2_APB_GATE 71
|
||||
#define K230_LS_UART3_APB_GATE 72
|
||||
#define K230_LS_UART4_APB_GATE 73
|
||||
#define K230_LS_I2C0_APB_GATE 74
|
||||
#define K230_LS_I2C1_APB_GATE 75
|
||||
#define K230_LS_I2C2_APB_GATE 76
|
||||
#define K230_LS_I2C3_APB_GATE 77
|
||||
#define K230_LS_I2C4_APB_GATE 78
|
||||
#define K230_LS_GPIO_APB_GATE 79
|
||||
#define K230_LS_PWM_APB_GATE 80
|
||||
#define K230_LS_JAMLINK0_APB_GATE 81
|
||||
#define K230_LS_JAMLINK1_APB_GATE 82
|
||||
#define K230_LS_JAMLINK2_APB_GATE 83
|
||||
#define K230_LS_JAMLINK3_APB_GATE 84
|
||||
#define K230_LS_AUDIO_APB_GATE 85
|
||||
#define K230_LS_ADC_APB_GATE 86
|
||||
#define K230_LS_CODEC_APB_GATE 87
|
||||
#define K230_LS_I2C0_GATE 88
|
||||
#define K230_LS_I2C1_GATE 89
|
||||
#define K230_LS_I2C2_GATE 90
|
||||
#define K230_LS_I2C3_GATE 91
|
||||
#define K230_LS_I2C4_GATE 92
|
||||
#define K230_LS_CODEC_ADC_GATE 93
|
||||
#define K230_LS_CODEC_DAC_GATE 94
|
||||
#define K230_LS_AUDIO_DEV_GATE 95
|
||||
#define K230_LS_PDM_GATE 96
|
||||
#define K230_LS_ADC_GATE 97
|
||||
#define K230_LS_UART0_GATE 98
|
||||
#define K230_LS_UART1_GATE 99
|
||||
#define K230_LS_UART2_GATE 100
|
||||
#define K230_LS_UART3_GATE 101
|
||||
#define K230_LS_UART4_GATE 102
|
||||
#define K230_LS_JAMLINK0CO_GATE 103
|
||||
#define K230_LS_JAMLINK1CO_GATE 104
|
||||
#define K230_LS_JAMLINK2CO_GATE 105
|
||||
#define K230_LS_JAMLINK3CO_GATE 106
|
||||
#define K230_LS_GPIO_DEBOUNCE_GATE 107
|
||||
#define K230_SYSCTL_WDT0_APB_GATE 108
|
||||
#define K230_SYSCTL_WDT1_APB_GATE 109
|
||||
#define K230_SYSCTL_TIMER_APB_GATE 110
|
||||
#define K230_SYSCTL_IOMUX_APB_GATE 111
|
||||
#define K230_SYSCTL_MAILBOX_APB_GATE 112
|
||||
#define K230_SYSCTL_HDI_GATE 113
|
||||
#define K230_SYSCTL_TIME_STAMP_GATE 114
|
||||
#define K230_SYSCTL_WDT0_GATE 115
|
||||
#define K230_SYSCTL_WDT1_GATE 116
|
||||
#define K230_TIMER0_GATE 117
|
||||
#define K230_TIMER1_GATE 118
|
||||
#define K230_TIMER2_GATE 119
|
||||
#define K230_TIMER3_GATE 120
|
||||
#define K230_TIMER4_GATE 121
|
||||
#define K230_TIMER5_GATE 122
|
||||
#define K230_SHRM_APB_GATE 123
|
||||
#define K230_SHRM_AXI_GATE 124
|
||||
#define K230_SHRM_AXI_SLAVE_GATE 125
|
||||
#define K230_SHRM_NONAI2D_AXI_GATE 126
|
||||
#define K230_SHRM_SRAM_GATE 127
|
||||
#define K230_SHRM_DECOMPRESS_AXI_GATE 128
|
||||
#define K230_SHRM_SDMA_AXI_GATE 129
|
||||
#define K230_SHRM_PDMA_AXI_GATE 130
|
||||
#define K230_DDRC_SRC_GATE 131
|
||||
#define K230_DDRC_BYPASS_GATE 132
|
||||
#define K230_DDRC_APB_GATE 133
|
||||
#define K230_DISPLAY_AHB_GATE 134
|
||||
#define K230_DISPLAY_AXI_GATE 135
|
||||
#define K230_DISPLAY_GPU_GATE 136
|
||||
#define K230_DISPLAY_DPIP_GATE 137
|
||||
#define K230_DISPLAY_CFG_GATE 138
|
||||
#define K230_DISPLAY_REF_GATE 139
|
||||
#define K230_USB_480M_GATE 140
|
||||
#define K230_USB_100M_GATE 141
|
||||
#define K230_DPHY_DFT_GATE 142
|
||||
#define K230_SPI2AXI_GATE 143
|
||||
#define K230_AI_SRC_GATE 144
|
||||
#define K230_AI_AXI_GATE 145
|
||||
#define K230_AI_SRC_RATE 146
|
||||
#define K230_CAMERA0_GATE 147
|
||||
#define K230_CAMERA1_GATE 148
|
||||
#define K230_CAMERA2_GATE 149
|
||||
#define K230_LS_APB_SRC_RATE 150
|
||||
#define K230_LS_I2C0_RATE 151
|
||||
#define K230_LS_I2C1_RATE 152
|
||||
#define K230_LS_I2C2_RATE 153
|
||||
#define K230_LS_I2C3_RATE 154
|
||||
#define K230_LS_I2C4_RATE 155
|
||||
#define K230_LS_CODEC_ADC_RATE 156
|
||||
#define K230_LS_CODEC_DAC_RATE 157
|
||||
#define K230_LS_AUDIO_DEV_RATE 158
|
||||
#define K230_LS_PDM_RATE 159
|
||||
#define K230_LS_ADC_RATE 160
|
||||
#define K230_LS_UART0_RATE 161
|
||||
#define K230_LS_UART1_RATE 162
|
||||
#define K230_LS_UART2_RATE 163
|
||||
#define K230_LS_UART3_RATE 164
|
||||
#define K230_LS_UART4_RATE 165
|
||||
#define K230_LS_JAMLINKCO_SRC_RATE 166
|
||||
#define K230_LS_GPIO_DEBOUNCE_RATE 167
|
||||
#define K230_SYSCTL_HDI_RATE 168
|
||||
#define K230_SYSCTL_TIME_STAMP_RATE 169
|
||||
#define K230_SYSCTL_TEMP_SENSOR_RATE 170
|
||||
#define K230_SYSCTL_WDT0_RATE 171
|
||||
#define K230_SYSCTL_WDT1_RATE 172
|
||||
#define K230_TIMER0_SRC_RATE 173
|
||||
#define K230_TIMER1_SRC_RATE 174
|
||||
#define K230_TIMER2_SRC_RATE 175
|
||||
#define K230_TIMER3_SRC_RATE 176
|
||||
#define K230_TIMER4_SRC_RATE 177
|
||||
#define K230_TIMER5_SRC_RATE 178
|
||||
#define K230_SHRM_APB_RATE 179
|
||||
#define K230_DDRC_SRC_RATE 180
|
||||
#define K230_DDRC_APB_RATE 181
|
||||
#define K230_DISPLAY_AHB_RATE 182
|
||||
#define K230_DISPLAY_CLKEXT_RATE 183
|
||||
#define K230_DISPLAY_GPU_RATE 184
|
||||
#define K230_DISPLAY_DPIP_RATE 185
|
||||
#define K230_DISPLAY_CFG_RATE 186
|
||||
#define K230_VPU_SRC_GATE 187
|
||||
#define K230_VPU_AXI_GATE 188
|
||||
#define K230_VPU_DDRCP2_GATE 189
|
||||
#define K230_VPU_CFG_GATE 190
|
||||
#define K230_VPU_SRC_RATE 191
|
||||
#define K230_VPU_AXI_SRC_RATE 192
|
||||
#define K230_VPU_CFG_RATE 193
|
||||
#define K230_SEC_APB_GATE 194
|
||||
#define K230_SEC_FIX_GATE 195
|
||||
#define K230_SEC_AXI_GATE 196
|
||||
#define K230_SEC_APB_RATE 197
|
||||
#define K230_SEC_FIX_RATE 198
|
||||
#define K230_SEC_AXI_RATE 199
|
||||
#define K230_USB_480M_RATE 200
|
||||
#define K230_USB_100M_RATE 201
|
||||
#define K230_DPHY_DFT_RATE 202
|
||||
#define K230_SPI2AXI_RATE 203
|
||||
#define K230_CAMERA0_RATE 204
|
||||
#define K230_CAMERA1_RATE 205
|
||||
#define K230_CAMERA2_RATE 206
|
||||
#define K230_SHRM_SRAM_DIV2 207
|
||||
|
||||
#endif /* __DT_BINDINGS_CANAAN_K230_CLOCK_H__ */
|
||||
@@ -23,6 +23,8 @@
|
||||
#define R8A73A4_CLK_ZX 13
|
||||
#define R8A73A4_CLK_ZS 14
|
||||
#define R8A73A4_CLK_HP 15
|
||||
#define R8A73A4_CLK_ZTR 16
|
||||
#define R8A73A4_CLK_ZT 17
|
||||
|
||||
/* MSTP1 */
|
||||
#define R8A73A4_CLK_TMU0 25
|
||||
|
||||
@@ -24,6 +24,8 @@
|
||||
#define R8A7740_CLK_ZB 14
|
||||
#define R8A7740_CLK_M3 15
|
||||
#define R8A7740_CLK_CP 16
|
||||
#define R8A7740_CLK_ZTR 17
|
||||
#define R8A7740_CLK_ZT 18
|
||||
|
||||
/* MSTP1 */
|
||||
#define R8A7740_CLK_CEU21 28
|
||||
|
||||
@@ -164,6 +164,26 @@ struct rzv2h_pll_div_pars {
|
||||
.k = { .min = -32768, .max = 32767 }, \
|
||||
} \
|
||||
|
||||
#define RZG3E_CPG_PLL_DSI0_LIMITS(name) \
|
||||
static const struct rzv2h_pll_limits (name) = { \
|
||||
.fout = { .min = 25 * MEGA, .max = 1218 * MEGA }, \
|
||||
.fvco = { .min = 1600 * MEGA, .max = 3200 * MEGA }, \
|
||||
.m = { .min = 64, .max = 533 }, \
|
||||
.p = { .min = 1, .max = 4 }, \
|
||||
.s = { .min = 0, .max = 6 }, \
|
||||
.k = { .min = -32768, .max = 32767 }, \
|
||||
} \
|
||||
|
||||
#define RZG3E_CPG_PLL_DSI1_LIMITS(name) \
|
||||
static const struct rzv2h_pll_limits (name) = { \
|
||||
.fout = { .min = 25 * MEGA, .max = 609 * MEGA }, \
|
||||
.fvco = { .min = 1600 * MEGA, .max = 3200 * MEGA }, \
|
||||
.m = { .min = 64, .max = 533 }, \
|
||||
.p = { .min = 1, .max = 4 }, \
|
||||
.s = { .min = 0, .max = 6 }, \
|
||||
.k = { .min = -32768, .max = 32767 }, \
|
||||
} \
|
||||
|
||||
#ifdef CONFIG_CLK_RZV2H
|
||||
bool rzv2h_get_pll_pars(const struct rzv2h_pll_limits *limits,
|
||||
struct rzv2h_pll_pars *pars, u64 freq_millihz);
|
||||
|
||||
Reference in New Issue
Block a user