mirrors/linux
2
0
Fork 0
mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git synced 2026-07-22 02:17:36 -04:00
Code Issues Packages Projects Releases Wiki Activity

Merge branches 'clk-cleanup', 'clk-mediatek', 'clk-marvell' and 'clk-versal' into clk-next

Browse Source 
* clk-cleanup:
  clk: hisilicon: Improve deallocation in error path
  clk-lpc18xx-ccu: kzalloc + kcalloc to kzalloc_flex
  clk: bulk: Use dev_err_probe() helper in of_clk_bulk_get()
  clk: bcm: iproc-asiu: simplify allocation
  clk: clk-max77686: kzalloc + kcalloc to kzalloc
  clk: visconti: pll: use kzalloc_flex
  clk: hisilicon: clkdivider-hi6220: use kzalloc_flex
  clk: mvebu: use kzalloc_flex

* clk-mediatek:
  clk: mediatek: mt7988: use MUX_CLR_SET for gate-less muxes
  clk: mediatek: mt8192: use MUX_CLR_SET
  clk: mediatek: add MUX_CLR_SET macro

* clk-marvell:
  clk: mmp: pxa1908-apbcp: Add reset cells
  clk: mmp: pxa1908-apbc: Add reset cells
  dt-bindings: clock: marvell,pxa1908: Add #reset-cells

* clk-versal:
  clk: clk-axi-clkgen: Add support versal timings
This commit is contained in:
Stephen Boyd
2026-06-25 07:55:16 -07:00
parent 7b03559044 845a025a94 8267609a38 0aef2f0db6
commit 124e5c5ec9
8 changed files with 147 additions and 72 deletions
Download Patch File Download Diff File Expand all files Collapse all files

34
Documentation/devicetree/bindings/clock/marvell,pxa1908.yaml
View File

@@ -37,6 +37,9 @@ properties:
'#power-domain-cells':
const: 1
'#reset-cells':
const: 1
required:
- compatible
- reg
@@ -44,16 +47,27 @@ required:
additionalProperties: false
if:
not:
properties:
compatible:
contains:
const: marvell,pxa1908-apmu
then:
properties:
'#power-domain-cells': false
allOf:
- if:
not:
properties:
compatible:
contains:
const: marvell,pxa1908-apmu
then:
properties:
'#power-domain-cells': false
- if:
not:
properties:
compatible:
contains:
enum:
- marvell,pxa1908-apbc
- marvell,pxa1908-apbcp
then:
properties:
'#reset-cells': false
examples:
# APMU block:

5
drivers/clk/clk-axi-clkgen.c
View File

@@ -521,7 +521,7 @@ static int axi_clkgen_setup_limits(struct axi_clkgen *axi_clkgen,
axi_clkgen->limits.fvco_max = 1200000;
axi_clkgen->limits.fpfd_max = 450000;
break;
case ADI_AXI_FPGA_SPEED_2 ... ADI_AXI_FPGA_SPEED_2LV:
case ADI_AXI_FPGA_SPEED_2 ... ADI_AXI_FPGA_SPEED_2MP:
axi_clkgen->limits.fvco_max = 1440000;
axi_clkgen->limits.fpfd_max = 500000;
if (family == ADI_AXI_FPGA_FAMILY_KINTEX || family == ADI_AXI_FPGA_FAMILY_ARTIX) {
@@ -546,6 +546,9 @@ static int axi_clkgen_setup_limits(struct axi_clkgen *axi_clkgen,
if (tech == ADI_AXI_FPGA_TECH_ULTRASCALE_PLUS) {
axi_clkgen->limits.fvco_max = 1600000;
axi_clkgen->limits.fvco_min = 800000;
} else if (tech == ADI_AXI_FPGA_TECH_VERSAL) {
axi_clkgen->limits.fvco_max = 4320000;
axi_clkgen->limits.fvco_min = 2160000;
}
return 0;

80
drivers/clk/mediatek/clk-mt7988-infracfg.c
View File

@@ -56,49 +56,45 @@ static const char *const infra_pcie_gfmux_tl_ck_o_p3_parents[] __initconst = {
static const struct mtk_mux infra_muxes[] = {
/* MODULE_CLK_SEL_0 */
MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_UART0_SEL, "infra_mux_uart0_sel",
infra_mux_uart0_parents, 0x0018, 0x0010, 0x0014, 0, 1, -1, -1, -1),
MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_UART1_SEL, "infra_mux_uart1_sel",
infra_mux_uart1_parents, 0x0018, 0x0010, 0x0014, 1, 1, -1, -1, -1),
MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_UART2_SEL, "infra_mux_uart2_sel",
infra_mux_uart2_parents, 0x0018, 0x0010, 0x0014, 2, 1, -1, -1, -1),
MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_SPI0_SEL, "infra_mux_spi0_sel", infra_mux_spi0_parents,
0x0018, 0x0010, 0x0014, 4, 1, -1, -1, -1),
MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_SPI1_SEL, "infra_mux_spi1_sel", infra_mux_spi1_parents,
0x0018, 0x0010, 0x0014, 5, 1, -1, -1, -1),
MUX_GATE_CLR_SET_UPD(CLK_INFRA_MUX_SPI2_SEL, "infra_mux_spi2_sel", infra_mux_spi0_parents,
0x0018, 0x0010, 0x0014, 6, 1, -1, -1, -1),
MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_SEL, "infra_pwm_sel", infra_pwm_bck_parents, 0x0018,
0x0010, 0x0014, 14, 2, -1, -1, -1),
MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK1_SEL, "infra_pwm_ck1_sel", infra_pwm_bck_parents,
0x0018, 0x0010, 0x0014, 16, 2, -1, -1, -1),
MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK2_SEL, "infra_pwm_ck2_sel", infra_pwm_bck_parents,
0x0018, 0x0010, 0x0014, 18, 2, -1, -1, -1),
MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK3_SEL, "infra_pwm_ck3_sel", infra_pwm_bck_parents,
0x0018, 0x0010, 0x0014, 20, 2, -1, -1, -1),
MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK4_SEL, "infra_pwm_ck4_sel", infra_pwm_bck_parents,
0x0018, 0x0010, 0x0014, 22, 2, -1, -1, -1),
MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK5_SEL, "infra_pwm_ck5_sel", infra_pwm_bck_parents,
0x0018, 0x0010, 0x0014, 24, 2, -1, -1, -1),
MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK6_SEL, "infra_pwm_ck6_sel", infra_pwm_bck_parents,
0x0018, 0x0010, 0x0014, 26, 2, -1, -1, -1),
MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK7_SEL, "infra_pwm_ck7_sel", infra_pwm_bck_parents,
0x0018, 0x0010, 0x0014, 28, 2, -1, -1, -1),
MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_CK8_SEL, "infra_pwm_ck8_sel", infra_pwm_bck_parents,
0x0018, 0x0010, 0x0014, 30, 2, -1, -1, -1),
MUX_CLR_SET(CLK_INFRA_MUX_UART0_SEL, "infra_mux_uart0_sel",
infra_mux_uart0_parents, 0x0018, 0x0010, 0x0014, 0, 1),
MUX_CLR_SET(CLK_INFRA_MUX_UART1_SEL, "infra_mux_uart1_sel",
infra_mux_uart1_parents, 0x0018, 0x0010, 0x0014, 1, 1),
MUX_CLR_SET(CLK_INFRA_MUX_UART2_SEL, "infra_mux_uart2_sel",
infra_mux_uart2_parents, 0x0018, 0x0010, 0x0014, 2, 1),
MUX_CLR_SET(CLK_INFRA_MUX_SPI0_SEL, "infra_mux_spi0_sel",
infra_mux_spi0_parents, 0x0018, 0x0010, 0x0014, 4, 1),
MUX_CLR_SET(CLK_INFRA_MUX_SPI1_SEL, "infra_mux_spi1_sel",
infra_mux_spi1_parents, 0x0018, 0x0010, 0x0014, 5, 1),
MUX_CLR_SET(CLK_INFRA_MUX_SPI2_SEL, "infra_mux_spi2_sel",
infra_mux_spi0_parents, 0x0018, 0x0010, 0x0014, 6, 1),
MUX_CLR_SET(CLK_INFRA_PWM_SEL, "infra_pwm_sel",
infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 14, 2),
MUX_CLR_SET(CLK_INFRA_PWM_CK1_SEL, "infra_pwm_ck1_sel",
infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 16, 2),
MUX_CLR_SET(CLK_INFRA_PWM_CK2_SEL, "infra_pwm_ck2_sel",
infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 18, 2),
MUX_CLR_SET(CLK_INFRA_PWM_CK3_SEL, "infra_pwm_ck3_sel",
infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 20, 2),
MUX_CLR_SET(CLK_INFRA_PWM_CK4_SEL, "infra_pwm_ck4_sel",
infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 22, 2),
MUX_CLR_SET(CLK_INFRA_PWM_CK5_SEL, "infra_pwm_ck5_sel",
infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 24, 2),
MUX_CLR_SET(CLK_INFRA_PWM_CK6_SEL, "infra_pwm_ck6_sel",
infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 26, 2),
MUX_CLR_SET(CLK_INFRA_PWM_CK7_SEL, "infra_pwm_ck7_sel",
infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 28, 2),
MUX_CLR_SET(CLK_INFRA_PWM_CK8_SEL, "infra_pwm_ck8_sel",
infra_pwm_bck_parents, 0x0018, 0x0010, 0x0014, 30, 2),
/* MODULE_CLK_SEL_1 */
MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_GFMUX_TL_O_P0_SEL, "infra_pcie_gfmux_tl_o_p0_sel",
infra_pcie_gfmux_tl_ck_o_p0_parents, 0x0028, 0x0020, 0x0024, 0, 2, -1,
-1, -1),
MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_GFMUX_TL_O_P1_SEL, "infra_pcie_gfmux_tl_o_p1_sel",
infra_pcie_gfmux_tl_ck_o_p1_parents, 0x0028, 0x0020, 0x0024, 2, 2, -1,
-1, -1),
MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_GFMUX_TL_O_P2_SEL, "infra_pcie_gfmux_tl_o_p2_sel",
infra_pcie_gfmux_tl_ck_o_p2_parents, 0x0028, 0x0020, 0x0024, 4, 2, -1,
-1, -1),
MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_GFMUX_TL_O_P3_SEL, "infra_pcie_gfmux_tl_o_p3_sel",
infra_pcie_gfmux_tl_ck_o_p3_parents, 0x0028, 0x0020, 0x0024, 6, 2, -1,
-1, -1),
MUX_CLR_SET(CLK_INFRA_PCIE_GFMUX_TL_O_P0_SEL, "infra_pcie_gfmux_tl_o_p0_sel",
infra_pcie_gfmux_tl_ck_o_p0_parents, 0x0028, 0x0020, 0x0024, 0, 2),
MUX_CLR_SET(CLK_INFRA_PCIE_GFMUX_TL_O_P1_SEL, "infra_pcie_gfmux_tl_o_p1_sel",
infra_pcie_gfmux_tl_ck_o_p1_parents, 0x0028, 0x0020, 0x0024, 2, 2),
MUX_CLR_SET(CLK_INFRA_PCIE_GFMUX_TL_O_P2_SEL, "infra_pcie_gfmux_tl_o_p2_sel",
infra_pcie_gfmux_tl_ck_o_p2_parents, 0x0028, 0x0020, 0x0024, 4, 2),
MUX_CLR_SET(CLK_INFRA_PCIE_GFMUX_TL_O_P3_SEL, "infra_pcie_gfmux_tl_o_p3_sel",
infra_pcie_gfmux_tl_ck_o_p3_parents, 0x0028, 0x0020, 0x0024, 6, 2),
};
static const struct mtk_gate_regs infra0_cg_regs = {

4
drivers/clk/mediatek/clk-mt8192.c
View File

@@ -579,8 +579,8 @@ static const struct mtk_mux top_mtk_muxes[] = {
dsp7_parents, 0x050, 0x054, 0x058, 0, 3, 7, 0x004, 16),
MUX_GATE_CLR_SET_UPD(CLK_TOP_MFG_REF_SEL, "mfg_ref_sel",
mfg_ref_parents, 0x050, 0x054, 0x058, 16, 2, 23, 0x004, 18),
MUX_CLR_SET_UPD(CLK_TOP_MFG_PLL_SEL, "mfg_pll_sel",
mfg_pll_parents, 0x050, 0x054, 0x058, 18, 1, -1, -1),
MUX_CLR_SET(CLK_TOP_MFG_PLL_SEL, "mfg_pll_sel", mfg_pll_parents,
0x050, 0x054, 0x058, 18, 1),
MUX_GATE_CLR_SET_UPD(CLK_TOP_CAMTG_SEL, "camtg_sel",
camtg_parents, 0x050, 0x054, 0x058, 24, 3, 31, 0x004, 19),
/* CLK_CFG_5 */

5
drivers/clk/mediatek/clk-mux.h
View File

@@ -126,6 +126,11 @@ extern const struct clk_ops mtk_mux_gate_hwv_fenc_clr_set_upd_ops;
0, _upd_ofs, _upd, CLK_SET_RATE_PARENT, \
mtk_mux_clr_set_upd_ops)
#define MUX_CLR_SET(_id, _name, _parents, _mux_ofs, \
_mux_set_ofs, _mux_clr_ofs, _shift, _width) \
MUX_CLR_SET_UPD(_id, _name, _parents, _mux_ofs, \
_mux_set_ofs, _mux_clr_ofs, _shift, _width, 0, -1)
#define MUX_GATE_HWV_FENC_CLR_SET_UPD_FLAGS(_id, _name, _parents, \
_mux_ofs, _mux_set_ofs, _mux_clr_ofs, \
_hwv_sta_ofs, _hwv_set_ofs, _hwv_clr_ofs, \

58
drivers/clk/mmp/clk-pxa1908-apbc.c
View File

@@ -7,6 +7,7 @@
#include <dt-bindings/clock/marvell,pxa1908.h>
#include "clk.h"
#include "reset.h"
#define APBC_UART0 0x0
#define APBC_UART1 0x4
@@ -44,22 +45,25 @@ static const char * const uart_parent_names[] = {"pll1_117", "uart_pll"};
static const char * const ssp_parent_names[] = {"pll1_d16", "pll1_d48", "pll1_d24", "pll1_d12"};
static struct mmp_param_gate_clk apbc_gate_clks[] = {
{PXA1908_CLK_TWSI0, "twsi0_clk", "pll1_32", CLK_SET_RATE_PARENT, APBC_TWSI0, 0x7, 3, 0, 0, NULL},
{PXA1908_CLK_TWSI1, "twsi1_clk", "pll1_32", CLK_SET_RATE_PARENT, APBC_TWSI1, 0x7, 3, 0, 0, NULL},
{PXA1908_CLK_TWSI3, "twsi3_clk", "pll1_32", CLK_SET_RATE_PARENT, APBC_TWSI3, 0x7, 3, 0, 0, NULL},
{PXA1908_CLK_GPIO, "gpio_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_GPIO, 0x7, 3, 0, 0, NULL},
{PXA1908_CLK_KPC, "kpc_clk", "clk32", CLK_SET_RATE_PARENT, APBC_KPC, 0x7, 3, 0, MMP_CLK_GATE_NEED_DELAY, NULL},
{PXA1908_CLK_RTC, "rtc_clk", "clk32", CLK_SET_RATE_PARENT, APBC_RTC, 0x87, 0x83, 0, MMP_CLK_GATE_NEED_DELAY, NULL},
{PXA1908_CLK_TWSI0, "twsi0_clk", "pll1_32", CLK_SET_RATE_PARENT, APBC_TWSI0, 0x3, 3, 0, 0, NULL},
{PXA1908_CLK_TWSI1, "twsi1_clk", "pll1_32", CLK_SET_RATE_PARENT, APBC_TWSI1, 0x3, 3, 0, 0, NULL},
{PXA1908_CLK_TWSI3, "twsi3_clk", "pll1_32", CLK_SET_RATE_PARENT, APBC_TWSI3, 0x3, 3, 0, 0, NULL},
{PXA1908_CLK_GPIO, "gpio_clk", "vctcxo", CLK_SET_RATE_PARENT, APBC_GPIO, 0x3, 3, 0, 0, NULL},
{PXA1908_CLK_KPC, "kpc_clk", "clk32", CLK_SET_RATE_PARENT, APBC_KPC, 0x3, 3, 0, MMP_CLK_GATE_NEED_DELAY, NULL},
{PXA1908_CLK_RTC, "rtc_clk", "clk32", CLK_SET_RATE_PARENT, APBC_RTC, 0x83, 0x83, 0, MMP_CLK_GATE_NEED_DELAY, NULL},
{PXA1908_CLK_PWM1, "pwm1_clk", "pwm01_apb_share", CLK_SET_RATE_PARENT, APBC_PWM1, 0x2, 2, 0, 0, NULL},
{PXA1908_CLK_PWM3, "pwm3_clk", "pwm23_apb_share", CLK_SET_RATE_PARENT, APBC_PWM3, 0x2, 2, 0, 0, NULL},
{PXA1908_CLK_UART0, "uart0_clk", "uart0_mux", CLK_SET_RATE_PARENT, APBC_UART0, 0x3, 3, 0, 0, &uart0_lock},
{PXA1908_CLK_UART1, "uart1_clk", "uart1_mux", CLK_SET_RATE_PARENT, APBC_UART1, 0x3, 3, 0, 0, &uart1_lock},
{PXA1908_CLK_THERMAL, "thermal_clk", NULL, 0, APBC_THERMAL, 0x3, 3, 0, 0, NULL},
{PXA1908_CLK_IPC_RST, "ipc_clk", NULL, 0, APBC_IPC_RST, 0x3, 3, 0, 0, NULL},
{PXA1908_CLK_SSP0, "ssp0_clk", "ssp0_mux", 0, APBC_SSP0, 0x3, 3, 0, 0, NULL},
{PXA1908_CLK_SSP2, "ssp2_clk", "ssp2_mux", 0, APBC_SSP2, 0x3, 3, 0, 0, NULL},
};
static struct mmp_param_gate_clk apbc_gate_no_reset_clks[] = {
{PXA1908_CLK_PWM0, "pwm0_clk", "pwm01_apb_share", CLK_SET_RATE_PARENT, APBC_PWM0, 0x2, 2, 0, 0, &pwm0_lock},
{PXA1908_CLK_PWM1, "pwm1_clk", "pwm01_apb_share", CLK_SET_RATE_PARENT, APBC_PWM1, 0x6, 2, 0, 0, NULL},
{PXA1908_CLK_PWM2, "pwm2_clk", "pwm23_apb_share", CLK_SET_RATE_PARENT, APBC_PWM2, 0x2, 2, 0, 0, NULL},
{PXA1908_CLK_PWM3, "pwm3_clk", "pwm23_apb_share", CLK_SET_RATE_PARENT, APBC_PWM3, 0x6, 2, 0, 0, NULL},
{PXA1908_CLK_UART0, "uart0_clk", "uart0_mux", CLK_SET_RATE_PARENT, APBC_UART0, 0x7, 3, 0, 0, &uart0_lock},
{PXA1908_CLK_UART1, "uart1_clk", "uart1_mux", CLK_SET_RATE_PARENT, APBC_UART1, 0x7, 3, 0, 0, &uart1_lock},
{PXA1908_CLK_THERMAL, "thermal_clk", NULL, 0, APBC_THERMAL, 0x7, 3, 0, 0, NULL},
{PXA1908_CLK_IPC_RST, "ipc_clk", NULL, 0, APBC_IPC_RST, 0x7, 3, 0, 0, NULL},
{PXA1908_CLK_SSP0, "ssp0_clk", "ssp0_mux", 0, APBC_SSP0, 0x7, 3, 0, 0, NULL},
{PXA1908_CLK_SSP2, "ssp2_clk", "ssp2_mux", 0, APBC_SSP2, 0x7, 3, 0, 0, NULL},
};
static struct mmp_param_mux_clk apbc_mux_clks[] = {
@@ -89,6 +93,30 @@ static void pxa1908_apb_periph_clk_init(struct pxa1908_clk_unit *pxa_unit)
ARRAY_SIZE(apbc_mux_clks));
mmp_register_gate_clks(unit, apbc_gate_clks, pxa_unit->base,
ARRAY_SIZE(apbc_gate_clks));
mmp_register_gate_clks(unit, apbc_gate_no_reset_clks, pxa_unit->base,
ARRAY_SIZE(apbc_gate_no_reset_clks));
}
/* Taken from clk-of-pxa1928.c */
static void pxa1908_clk_reset_init(struct device_node *np,
struct pxa1908_clk_unit *pxa_unit)
{
struct mmp_clk_reset_cell *cells;
int nr_cells = ARRAY_SIZE(apbc_gate_clks);
cells = kzalloc_objs(*cells, nr_cells);
if (!cells)
return;
for (int i = 0; i < nr_cells; i++) {
cells[i].clk_id = apbc_gate_clks[i].id;
cells[i].reg = pxa_unit->base + apbc_gate_clks[i].offset;
cells[i].bits = BIT(2);
cells[i].flags = 0;
cells[i].lock = apbc_gate_clks[i].lock;
};
mmp_clk_reset_register(np, cells, nr_cells);
}
static int pxa1908_apbc_probe(struct platform_device *pdev)
@@ -107,6 +135,8 @@ static int pxa1908_apbc_probe(struct platform_device *pdev)
pxa1908_apb_periph_clk_init(pxa_unit);
pxa1908_clk_reset_init(pdev->dev.of_node, pxa_unit);
return 0;
}

31
drivers/clk/mmp/clk-pxa1908-apbcp.c
View File

@@ -7,6 +7,7 @@
#include <dt-bindings/clock/marvell,pxa1908.h>
#include "clk.h"
#include "reset.h"
#define APBCP_UART2 0x1c
#define APBCP_TWSI2 0x28
@@ -24,9 +25,9 @@ static DEFINE_SPINLOCK(uart2_lock);
static const char * const uart_parent_names[] = {"pll1_117", "uart_pll"};
static struct mmp_param_gate_clk apbcp_gate_clks[] = {
{PXA1908_CLK_UART2, "uart2_clk", "uart2_mux", CLK_SET_RATE_PARENT, APBCP_UART2, 0x7, 0x3, 0x0, 0, &uart2_lock},
{PXA1908_CLK_TWSI2, "twsi2_clk", "pll1_32", CLK_SET_RATE_PARENT, APBCP_TWSI2, 0x7, 0x3, 0x0, 0, NULL},
{PXA1908_CLK_AICER, "ripc_clk", NULL, 0, APBCP_AICER, 0x7, 0x2, 0x0, 0, NULL},
{PXA1908_CLK_UART2, "uart2_clk", "uart2_mux", CLK_SET_RATE_PARENT, APBCP_UART2, 0x3, 0x3, 0x0, 0, &uart2_lock},
{PXA1908_CLK_TWSI2, "twsi2_clk", "pll1_32", CLK_SET_RATE_PARENT, APBCP_TWSI2, 0x3, 0x3, 0x0, 0, NULL},
{PXA1908_CLK_AICER, "ripc_clk", NULL, 0, APBCP_AICER, 0x3, 0x2, 0x0, 0, NULL},
};
static struct mmp_param_mux_clk apbcp_mux_clks[] = {
@@ -43,6 +44,28 @@ static void pxa1908_apb_p_periph_clk_init(struct pxa1908_clk_unit *pxa_unit)
ARRAY_SIZE(apbcp_gate_clks));
}
/* Taken from clk-of-pxa1928.c */
static void pxa1908_clk_reset_init(struct device_node *np,
struct pxa1908_clk_unit *pxa_unit)
{
struct mmp_clk_reset_cell *cells;
int nr_cells = ARRAY_SIZE(apbcp_gate_clks);
cells = kzalloc_objs(*cells, nr_cells);
if (!cells)
return;
for (int i = 0; i < nr_cells; i++) {
cells[i].clk_id = apbcp_gate_clks[i].id;
cells[i].reg = pxa_unit->base + apbcp_gate_clks[i].offset;
cells[i].bits = BIT(2);
cells[i].flags = 0;
cells[i].lock = apbcp_gate_clks[i].lock;
};
mmp_clk_reset_register(np, cells, nr_cells);
}
static int pxa1908_apbcp_probe(struct platform_device *pdev)
{
struct pxa1908_clk_unit *pxa_unit;
@@ -59,6 +82,8 @@ static int pxa1908_apbcp_probe(struct platform_device *pdev)
pxa1908_apb_p_periph_clk_init(pxa_unit);
pxa1908_clk_reset_init(pdev->dev.of_node, pxa_unit);
return 0;
}

2
include/linux/adi-axi-common.h
View File

@@ -51,6 +51,7 @@ enum adi_axi_fpga_technology {
ADI_AXI_FPGA_TECH_SERIES7,
ADI_AXI_FPGA_TECH_ULTRASCALE,
ADI_AXI_FPGA_TECH_ULTRASCALE_PLUS,
ADI_AXI_FPGA_TECH_VERSAL,
};
enum adi_axi_fpga_family {
@@ -71,6 +72,7 @@ enum adi_axi_fpga_speed_grade {
ADI_AXI_FPGA_SPEED_2 = 20,
ADI_AXI_FPGA_SPEED_2L = 21,
ADI_AXI_FPGA_SPEED_2LV = 22,
ADI_AXI_FPGA_SPEED_2MP = 23,
ADI_AXI_FPGA_SPEED_3 = 30,
};