mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
synced 2026-05-10 11:40:19 -04:00
Merge tag 'zynqmp-dt-for-v5.16' of https://github.com/Xilinx/linux-xlnx into arm/dt
arm64: dts: ZynqMP DT changes for v5.16 - Fix issues reported by dtbs_check - Enable DMAs, DP, USB, NAND on various boards - Add description for irps5401 - Add pinctrl description - Add psgtr description for usb3, sata and DP - Start to use nvmem alias for eeprom reference - Clean up aliases list - Wire qspi and usb3.0 - Add support for zcu102-rev1.1 - Couple of minor fixes and sync patches * tag 'zynqmp-dt-for-v5.16' of https://github.com/Xilinx/linux-xlnx: (36 commits) arm64: zynqmp: Wire psgtr for zc1751-xm013 arm64: zynqmp: Enable xlnx,zynqmp-dwc3 driver for xilinx boards arm64: zynqmp: Enable gpio and qspi for zc1275-revA arm64: zynqmp: Fix serial compatible string arm64: zynqmp: Remove not documented is-dual property arm64: zynqmp: Add psgtr description to zc1751 dc1 board arm64: zynqmp: Add support for zcu102-rev1.1 board arm64: zynqmp: Remove description for 8T49N287 and si5382 chips arm64: zynqmp: Sync psgtr node location with zcu104-revA arm64: zynqmp: Add reset description for sata arm64: zynqmp: Move rtc to different location on zcu104-revA arm64: zynqmp: Wire qspi on multiple boards arm64: zynqmp: Remove information about dma clock on zcu106 arm64: zynqmp: Update rtc calibration value arm64: zynqmp: Add note about UHS mode on some boards arm64: zynqmp: Move DP nodes to the end of file on zcu106 arm64: zynqmp: Remove can aliases from zc1751 arm64: zynqmp: Add reset-on-timeout to all boards and modify default timeout value arm64: zynqmp: List reset property for ethernet phy arm64: zynqmp: Add nvmem alises for eeproms ... Link: https://lore.kernel.org/r/b1cbd05d-ab40-e1fc-4001-6cf88e1e81f9@monstr.eu Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
@@ -87,6 +87,7 @@ properties:
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- xlnx,zynqmp-zcu102-revA
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- xlnx,zynqmp-zcu102-revB
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- xlnx,zynqmp-zcu102-rev1.0
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- xlnx,zynqmp-zcu102-rev1.1
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- const: xlnx,zynqmp-zcu102
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- const: xlnx,zynqmp
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@@ -12,6 +12,7 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu100-revC.dtb
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dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-revA.dtb
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dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-revB.dtb
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dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-rev1.0.dtb
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dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu102-rev1.1.dtb
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dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu104-revA.dtb
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dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu104-revC.dtb
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dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zcu106-revA.dtb
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@@ -2,7 +2,7 @@
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/*
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* Clock specification for Xilinx ZynqMP
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*
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* (C) Copyright 2017 - 2019, Xilinx, Inc.
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* (C) Copyright 2017 - 2021, Xilinx, Inc.
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*
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* Michal Simek <michal.simek@xilinx.com>
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*/
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@@ -40,6 +40,17 @@ aux_ref_clk: aux_ref_clk {
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};
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};
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&zynqmp_firmware {
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zynqmp_clk: clock-controller {
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#clock-cells = <1>;
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compatible = "xlnx,zynqmp-clk";
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clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>,
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<&aux_ref_clk>, <>_crx_ref_clk>;
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clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk",
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"aux_ref_clk", "gt_crx_ref_clk";
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};
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};
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&can0 {
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clocks = <&zynqmp_clk CAN0_REF>, <&zynqmp_clk LPD_LSBUS>;
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};
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@@ -2,7 +2,7 @@
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/*
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* dts file for Xilinx ZynqMP ZC1232
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*
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* (C) Copyright 2017 - 2019, Xilinx, Inc.
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* (C) Copyright 2017 - 2021, Xilinx, Inc.
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*
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* Michal Simek <michal.simek@xilinx.com>
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*/
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@@ -19,6 +19,7 @@ / {
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aliases {
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serial0 = &uart0;
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serial1 = &dcc;
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spi0 = &qspi;
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};
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chosen {
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@@ -36,6 +37,19 @@ &dcc {
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status = "okay";
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};
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&qspi {
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status = "okay";
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flash@0 {
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compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x0>;
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spi-tx-bus-width = <1>;
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spi-rx-bus-width = <4>;
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spi-max-frequency = <108000000>; /* Based on DC1 spec */
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};
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};
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&sata {
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status = "okay";
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/* SATA OOB timing settings */
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@@ -2,7 +2,7 @@
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/*
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* dts file for Xilinx ZynqMP ZC1254
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*
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* (C) Copyright 2015 - 2019, Xilinx, Inc.
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* (C) Copyright 2015 - 2021, Xilinx, Inc.
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*
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* Michal Simek <michal.simek@xilinx.com>
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* Siva Durga Prasad Paladugu <sivadur@xilinx.com>
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@@ -20,6 +20,7 @@ / {
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aliases {
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serial0 = &uart0;
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serial1 = &dcc;
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spi0 = &qspi;
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};
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chosen {
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@@ -37,6 +38,19 @@ &dcc {
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status = "okay";
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};
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&qspi {
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status = "okay";
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flash@0 {
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compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x0>;
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spi-tx-bus-width = <1>;
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spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
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spi-max-frequency = <108000000>; /* Based on DC1 spec */
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};
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};
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&uart0 {
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status = "okay";
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};
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@@ -2,7 +2,7 @@
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/*
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* dts file for Xilinx ZynqMP ZC1275
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*
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* (C) Copyright 2017 - 2019, Xilinx, Inc.
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* (C) Copyright 2017 - 2021, Xilinx, Inc.
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*
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* Michal Simek <michal.simek@xilinx.com>
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* Siva Durga Prasad Paladugu <sivadur@xilinx.com>
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@@ -20,6 +20,7 @@ / {
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aliases {
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serial0 = &uart0;
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serial1 = &dcc;
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spi0 = &qspi;
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};
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chosen {
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@@ -37,6 +38,21 @@ &dcc {
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status = "okay";
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};
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&gpio {
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status = "okay";
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};
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&qspi {
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status = "okay";
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flash@0 {
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compatible = "m25p80", "jedec,spi-nor";
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reg = <0x0>;
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spi-tx-bus-width = <1>;
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spi-rx-bus-width = <4>;
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spi-max-frequency = <108000000>;
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};
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};
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&uart0 {
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status = "okay";
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};
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@@ -2,7 +2,7 @@
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/*
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* dts file for Xilinx ZynqMP zc1751-xm015-dc1
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*
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* (C) Copyright 2015 - 2019, Xilinx, Inc.
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* (C) Copyright 2015 - 2021, Xilinx, Inc.
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*
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* Michal Simek <michal.simek@xilinx.com>
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*/
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@@ -11,7 +11,9 @@
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#include "zynqmp.dtsi"
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#include "zynqmp-clk-ccf.dtsi"
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#include <dt-bindings/phy/phy.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
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/ {
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model = "ZynqMP zc1751-xm015-dc1 RevA";
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@@ -24,6 +26,8 @@ aliases {
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mmc1 = &sdhci1;
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rtc0 = &rtc;
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serial0 = &uart0;
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spi0 = &qspi;
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usb0 = &usb0;
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};
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chosen {
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@@ -35,6 +39,24 @@ memory@0 {
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device_type = "memory";
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reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
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};
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clock_si5338_0: clk27 { /* u55 SI5338-GM */
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <27000000>;
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};
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clock_si5338_2: clk26 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <26000000>;
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};
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clock_si5338_3: clk150 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <150000000>;
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};
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};
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&fpd_dma_chan1 {
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@@ -73,6 +95,8 @@ &gem3 {
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status = "okay";
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phy-handle = <&phy0>;
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phy-mode = "rgmii-id";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_gem3_default>;
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phy0: ethernet-phy@0 {
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reg = <0>;
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};
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@@ -80,12 +104,19 @@ phy0: ethernet-phy@0 {
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&gpio {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_gpio_default>;
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};
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&i2c1 {
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status = "okay";
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clock-frequency = <400000>;
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pinctrl-names = "default", "gpio";
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pinctrl-0 = <&pinctrl_i2c1_default>;
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pinctrl-1 = <&pinctrl_i2c1_gpio>;
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scl-gpios = <&gpio 36 GPIO_ACTIVE_HIGH>;
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sda-gpios = <&gpio 37 GPIO_ACTIVE_HIGH>;
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eeprom: eeprom@55 {
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compatible = "atmel,24c64"; /* 24AA64 */
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@@ -93,6 +124,236 @@ eeprom: eeprom@55 {
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};
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};
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&pinctrl0 {
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status = "okay";
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pinctrl_i2c1_default: i2c1-default {
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mux {
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groups = "i2c1_9_grp";
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function = "i2c1";
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};
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conf {
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groups = "i2c1_9_grp";
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bias-pull-up;
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slew-rate = <SLEW_RATE_SLOW>;
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power-source = <IO_STANDARD_LVCMOS18>;
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};
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};
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pinctrl_i2c1_gpio: i2c1-gpio {
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mux {
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groups = "gpio0_36_grp", "gpio0_37_grp";
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function = "gpio0";
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};
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conf {
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groups = "gpio0_36_grp", "gpio0_37_grp";
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slew-rate = <SLEW_RATE_SLOW>;
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power-source = <IO_STANDARD_LVCMOS18>;
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};
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};
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pinctrl_uart0_default: uart0-default {
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mux {
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groups = "uart0_8_grp";
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function = "uart0";
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};
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conf {
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groups = "uart0_8_grp";
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slew-rate = <SLEW_RATE_SLOW>;
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power-source = <IO_STANDARD_LVCMOS18>;
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};
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conf-rx {
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pins = "MIO34";
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bias-high-impedance;
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};
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conf-tx {
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pins = "MIO35";
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bias-disable;
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};
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};
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pinctrl_usb0_default: usb0-default {
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mux {
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groups = "usb0_0_grp";
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function = "usb0";
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};
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conf {
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groups = "usb0_0_grp";
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slew-rate = <SLEW_RATE_SLOW>;
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power-source = <IO_STANDARD_LVCMOS18>;
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};
|
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conf-rx {
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pins = "MIO52", "MIO53", "MIO55";
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bias-high-impedance;
|
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};
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|
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conf-tx {
|
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pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
|
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"MIO60", "MIO61", "MIO62", "MIO63";
|
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bias-disable;
|
||||
};
|
||||
};
|
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|
||||
pinctrl_gem3_default: gem3-default {
|
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mux {
|
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function = "ethernet3";
|
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groups = "ethernet3_0_grp";
|
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};
|
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|
||||
conf {
|
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groups = "ethernet3_0_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
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|
||||
conf-rx {
|
||||
pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74",
|
||||
"MIO75";
|
||||
bias-high-impedance;
|
||||
low-power-disable;
|
||||
};
|
||||
|
||||
conf-tx {
|
||||
pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68",
|
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"MIO69";
|
||||
bias-disable;
|
||||
low-power-enable;
|
||||
};
|
||||
|
||||
mux-mdio {
|
||||
function = "mdio3";
|
||||
groups = "mdio3_0_grp";
|
||||
};
|
||||
|
||||
conf-mdio {
|
||||
groups = "mdio3_0_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_sdhci0_default: sdhci0-default {
|
||||
mux {
|
||||
groups = "sdio0_0_grp";
|
||||
function = "sdio0";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "sdio0_0_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
mux-cd {
|
||||
groups = "sdio0_cd_0_grp";
|
||||
function = "sdio0_cd";
|
||||
};
|
||||
|
||||
conf-cd {
|
||||
groups = "sdio0_cd_0_grp";
|
||||
bias-high-impedance;
|
||||
bias-pull-up;
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
|
||||
mux-wp {
|
||||
groups = "sdio0_wp_0_grp";
|
||||
function = "sdio0_wp";
|
||||
};
|
||||
|
||||
conf-wp {
|
||||
groups = "sdio0_wp_0_grp";
|
||||
bias-high-impedance;
|
||||
bias-pull-up;
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_sdhci1_default: sdhci1-default {
|
||||
mux {
|
||||
groups = "sdio1_0_grp";
|
||||
function = "sdio1";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "sdio1_0_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
mux-cd {
|
||||
groups = "sdio1_cd_0_grp";
|
||||
function = "sdio1_cd";
|
||||
};
|
||||
|
||||
conf-cd {
|
||||
groups = "sdio1_cd_0_grp";
|
||||
bias-high-impedance;
|
||||
bias-pull-up;
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
|
||||
mux-wp {
|
||||
groups = "sdio1_wp_0_grp";
|
||||
function = "sdio1_wp";
|
||||
};
|
||||
|
||||
conf-wp {
|
||||
groups = "sdio1_wp_0_grp";
|
||||
bias-high-impedance;
|
||||
bias-pull-up;
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_gpio_default: gpio-default {
|
||||
mux {
|
||||
function = "gpio0";
|
||||
groups = "gpio0_38_grp";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "gpio0_38_grp";
|
||||
bias-disable;
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&psgtr {
|
||||
status = "okay";
|
||||
/* dp, usb3, sata */
|
||||
clocks = <&clock_si5338_0>, <&clock_si5338_2>, <&clock_si5338_3>;
|
||||
clock-names = "ref1", "ref2", "ref3";
|
||||
};
|
||||
|
||||
&qspi {
|
||||
status = "okay";
|
||||
flash@0 {
|
||||
compatible = "m25p80", "jedec,spi-nor"; /* Micron MT25QU512ABB8ESF */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x0>;
|
||||
spi-tx-bus-width = <1>;
|
||||
spi-rx-bus-width = <4>;
|
||||
spi-max-frequency = <108000000>; /* Based on DC1 spec */
|
||||
};
|
||||
};
|
||||
|
||||
&rtc {
|
||||
status = "okay";
|
||||
};
|
||||
@@ -108,25 +369,60 @@ &sata {
|
||||
ceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;
|
||||
ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
|
||||
ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
|
||||
phy-names = "sata-phy";
|
||||
phys = <&psgtr 3 PHY_TYPE_SATA 1 3>;
|
||||
};
|
||||
|
||||
/* eMMC */
|
||||
&sdhci0 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_sdhci0_default>;
|
||||
bus-width = <8>;
|
||||
xlnx,mio-bank = <0>;
|
||||
};
|
||||
|
||||
/* SD1 with level shifter */
|
||||
&sdhci1 {
|
||||
status = "okay";
|
||||
/*
|
||||
* This property should be removed for supporting UHS mode
|
||||
*/
|
||||
no-1-8-v;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_sdhci1_default>;
|
||||
xlnx,mio-bank = <1>;
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart0_default>;
|
||||
};
|
||||
|
||||
/* ULPI SMSC USB3320 */
|
||||
&usb0 {
|
||||
status = "okay";
|
||||
dr_mode = "host";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usb0_default>;
|
||||
phy-names = "usb3-phy";
|
||||
phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
|
||||
};
|
||||
|
||||
&dwc3_0 {
|
||||
status = "okay";
|
||||
dr_mode = "host";
|
||||
snps,usb3_lpm_capable;
|
||||
maximum-speed = "super-speed";
|
||||
};
|
||||
|
||||
&zynqmp_dpdma {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&zynqmp_dpsub {
|
||||
status = "okay";
|
||||
phy-names = "dp-phy0", "dp-phy1";
|
||||
phys = <&psgtr 1 PHY_TYPE_DP 0 0>,
|
||||
<&psgtr 0 PHY_TYPE_DP 1 1>;
|
||||
};
|
||||
|
||||
@@ -2,7 +2,7 @@
|
||||
/*
|
||||
* dts file for Xilinx ZynqMP zc1751-xm016-dc2
|
||||
*
|
||||
* (C) Copyright 2015 - 2019, Xilinx, Inc.
|
||||
* (C) Copyright 2015 - 2021, Xilinx, Inc.
|
||||
*
|
||||
* Michal Simek <michal.simek@xilinx.com>
|
||||
*/
|
||||
@@ -12,14 +12,13 @@
|
||||
#include "zynqmp.dtsi"
|
||||
#include "zynqmp-clk-ccf.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
|
||||
|
||||
/ {
|
||||
model = "ZynqMP zc1751-xm016-dc2 RevA";
|
||||
compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
|
||||
|
||||
aliases {
|
||||
can0 = &can0;
|
||||
can1 = &can1;
|
||||
ethernet0 = &gem2;
|
||||
i2c0 = &i2c0;
|
||||
rtc0 = &rtc;
|
||||
@@ -27,6 +26,7 @@ aliases {
|
||||
serial1 = &uart1;
|
||||
spi0 = &spi0;
|
||||
spi1 = &spi1;
|
||||
usb0 = &usb1;
|
||||
};
|
||||
|
||||
chosen {
|
||||
@@ -42,10 +42,14 @@ memory@0 {
|
||||
|
||||
&can0 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_can0_default>;
|
||||
};
|
||||
|
||||
&can1 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_can1_default>;
|
||||
};
|
||||
|
||||
&fpd_dma_chan1 {
|
||||
@@ -84,6 +88,8 @@ &gem2 {
|
||||
status = "okay";
|
||||
phy-handle = <&phy0>;
|
||||
phy-mode = "rgmii-id";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_gem2_default>;
|
||||
phy0: ethernet-phy@5 {
|
||||
reg = <5>;
|
||||
ti,rx-internal-delay = <0x8>;
|
||||
@@ -100,6 +106,11 @@ &gpio {
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
pinctrl-names = "default", "gpio";
|
||||
pinctrl-0 = <&pinctrl_i2c0_default>;
|
||||
pinctrl-1 = <&pinctrl_i2c0_gpio>;
|
||||
scl-gpios = <&gpio 6 GPIO_ACTIVE_HIGH>;
|
||||
sda-gpios = <&gpio 7 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
tca6416_u26: gpio@20 {
|
||||
compatible = "ti,tca6416";
|
||||
@@ -115,6 +126,311 @@ rtc@68 {
|
||||
};
|
||||
};
|
||||
|
||||
&nand0 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_nand0_default>;
|
||||
arasan,has-mdma;
|
||||
|
||||
nand@0 {
|
||||
reg = <0x0>;
|
||||
#address-cells = <0x2>;
|
||||
#size-cells = <0x1>;
|
||||
nand-ecc-mode = "soft";
|
||||
nand-ecc-algo = "bch";
|
||||
nand-rb = <0>;
|
||||
label = "main-storage-0";
|
||||
};
|
||||
nand@1 {
|
||||
reg = <0x1>;
|
||||
#address-cells = <0x2>;
|
||||
#size-cells = <0x1>;
|
||||
nand-ecc-mode = "soft";
|
||||
nand-ecc-algo = "bch";
|
||||
nand-rb = <0>;
|
||||
label = "main-storage-1";
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl0 {
|
||||
status = "okay";
|
||||
pinctrl_can0_default: can0-default {
|
||||
mux {
|
||||
function = "can0";
|
||||
groups = "can0_9_grp";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "can0_9_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
|
||||
conf-rx {
|
||||
pins = "MIO38";
|
||||
bias-high-impedance;
|
||||
};
|
||||
|
||||
conf-tx {
|
||||
pins = "MIO39";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_can1_default: can1-default {
|
||||
mux {
|
||||
function = "can1";
|
||||
groups = "can1_8_grp";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "can1_8_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
|
||||
conf-rx {
|
||||
pins = "MIO33";
|
||||
bias-high-impedance;
|
||||
};
|
||||
|
||||
conf-tx {
|
||||
pins = "MIO32";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_i2c0_default: i2c0-default {
|
||||
mux {
|
||||
groups = "i2c0_1_grp";
|
||||
function = "i2c0";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "i2c0_1_grp";
|
||||
bias-pull-up;
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_i2c0_gpio: i2c0-gpio {
|
||||
mux {
|
||||
groups = "gpio0_6_grp", "gpio0_7_grp";
|
||||
function = "gpio0";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "gpio0_6_grp", "gpio0_7_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_uart0_default: uart0-default {
|
||||
mux {
|
||||
groups = "uart0_10_grp";
|
||||
function = "uart0";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "uart0_10_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
|
||||
conf-rx {
|
||||
pins = "MIO42";
|
||||
bias-high-impedance;
|
||||
};
|
||||
|
||||
conf-tx {
|
||||
pins = "MIO43";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_uart1_default: uart1-default {
|
||||
mux {
|
||||
groups = "uart1_10_grp";
|
||||
function = "uart1";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "uart1_10_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
|
||||
conf-rx {
|
||||
pins = "MIO41";
|
||||
bias-high-impedance;
|
||||
};
|
||||
|
||||
conf-tx {
|
||||
pins = "MIO40";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_usb1_default: usb1-default {
|
||||
mux {
|
||||
groups = "usb1_0_grp";
|
||||
function = "usb1";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "usb1_0_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
|
||||
conf-rx {
|
||||
pins = "MIO64", "MIO65", "MIO67";
|
||||
bias-high-impedance;
|
||||
};
|
||||
|
||||
conf-tx {
|
||||
pins = "MIO66", "MIO68", "MIO69", "MIO70", "MIO71",
|
||||
"MIO72", "MIO73", "MIO74", "MIO75";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_gem2_default: gem2-default {
|
||||
mux {
|
||||
function = "ethernet2";
|
||||
groups = "ethernet2_0_grp";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "ethernet2_0_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
|
||||
conf-rx {
|
||||
pins = "MIO58", "MIO59", "MIO60", "MIO61", "MIO62",
|
||||
"MIO63";
|
||||
bias-high-impedance;
|
||||
low-power-disable;
|
||||
};
|
||||
|
||||
conf-tx {
|
||||
pins = "MIO52", "MIO53", "MIO54", "MIO55", "MIO56",
|
||||
"MIO57";
|
||||
bias-disable;
|
||||
low-power-enable;
|
||||
};
|
||||
|
||||
mux-mdio {
|
||||
function = "mdio2";
|
||||
groups = "mdio2_0_grp";
|
||||
};
|
||||
|
||||
conf-mdio {
|
||||
groups = "mdio2_0_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_nand0_default: nand0-default {
|
||||
mux {
|
||||
groups = "nand0_0_grp";
|
||||
function = "nand0";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "nand0_0_grp";
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
mux-ce {
|
||||
groups = "nand0_ce_0_grp";
|
||||
function = "nand0_ce";
|
||||
};
|
||||
|
||||
conf-ce {
|
||||
groups = "nand0_ce_0_grp";
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
mux-rb {
|
||||
groups = "nand0_rb_0_grp";
|
||||
function = "nand0_rb";
|
||||
};
|
||||
|
||||
conf-rb {
|
||||
groups = "nand0_rb_0_grp";
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
mux-dqs {
|
||||
groups = "nand0_dqs_0_grp";
|
||||
function = "nand0_dqs";
|
||||
};
|
||||
|
||||
conf-dqs {
|
||||
groups = "nand0_dqs_0_grp";
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_spi0_default: spi0-default {
|
||||
mux {
|
||||
groups = "spi0_0_grp";
|
||||
function = "spi0";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "spi0_0_grp";
|
||||
bias-disable;
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
|
||||
mux-cs {
|
||||
groups = "spi0_ss_0_grp", "spi0_ss_1_grp",
|
||||
"spi0_ss_2_grp";
|
||||
function = "spi0_ss";
|
||||
};
|
||||
|
||||
conf-cs {
|
||||
groups = "spi0_ss_0_grp", "spi0_ss_1_grp",
|
||||
"spi0_ss_2_grp";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_spi1_default: spi1-default {
|
||||
mux {
|
||||
groups = "spi1_3_grp";
|
||||
function = "spi1";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "spi1_3_grp";
|
||||
bias-disable;
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
|
||||
mux-cs {
|
||||
groups = "spi1_ss_9_grp", "spi1_ss_10_grp",
|
||||
"spi1_ss_11_grp";
|
||||
function = "spi1_ss";
|
||||
};
|
||||
|
||||
conf-cs {
|
||||
groups = "spi1_ss_9_grp", "spi1_ss_10_grp",
|
||||
"spi1_ss_11_grp";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&rtc {
|
||||
status = "okay";
|
||||
};
|
||||
@@ -122,6 +438,8 @@ &rtc {
|
||||
&spi0 {
|
||||
status = "okay";
|
||||
num-cs = <1>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_spi0_default>;
|
||||
|
||||
spi0_flash0: flash@0 {
|
||||
#address-cells = <1>;
|
||||
@@ -131,7 +449,7 @@ spi0_flash0: flash@0 {
|
||||
reg = <0>;
|
||||
|
||||
partition@0 {
|
||||
label = "data";
|
||||
label = "spi0-data";
|
||||
reg = <0x0 0x100000>;
|
||||
};
|
||||
};
|
||||
@@ -140,6 +458,8 @@ partition@0 {
|
||||
&spi1 {
|
||||
status = "okay";
|
||||
num-cs = <1>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_spi1_default>;
|
||||
|
||||
spi1_flash0: flash@0 {
|
||||
#address-cells = <1>;
|
||||
@@ -149,7 +469,7 @@ spi1_flash0: flash@0 {
|
||||
reg = <0>;
|
||||
|
||||
partition@0 {
|
||||
label = "data";
|
||||
label = "spi1-data";
|
||||
reg = <0x0 0x84000>;
|
||||
};
|
||||
};
|
||||
@@ -157,14 +477,26 @@ partition@0 {
|
||||
|
||||
/* ULPI SMSC USB3320 */
|
||||
&usb1 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usb1_default>;
|
||||
};
|
||||
|
||||
&dwc3_1 {
|
||||
status = "okay";
|
||||
dr_mode = "host";
|
||||
snps,usb3_lpm_capable;
|
||||
maximum-speed = "super-speed";
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart0_default>;
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart1_default>;
|
||||
};
|
||||
|
||||
@@ -2,7 +2,7 @@
|
||||
/*
|
||||
* dts file for Xilinx ZynqMP zc1751-xm017-dc3
|
||||
*
|
||||
* (C) Copyright 2016 - 2019, Xilinx, Inc.
|
||||
* (C) Copyright 2016 - 2021, Xilinx, Inc.
|
||||
*
|
||||
* Michal Simek <michal.simek@xilinx.com>
|
||||
*/
|
||||
@@ -11,6 +11,7 @@
|
||||
|
||||
#include "zynqmp.dtsi"
|
||||
#include "zynqmp-clk-ccf.dtsi"
|
||||
#include <dt-bindings/phy/phy.h>
|
||||
|
||||
/ {
|
||||
model = "ZynqMP zc1751-xm017-dc3 RevA";
|
||||
@@ -24,6 +25,8 @@ aliases {
|
||||
rtc0 = &rtc;
|
||||
serial0 = &uart0;
|
||||
serial1 = &uart1;
|
||||
usb0 = &usb0;
|
||||
usb1 = &usb1;
|
||||
};
|
||||
|
||||
chosen {
|
||||
@@ -35,6 +38,18 @@ memory@0 {
|
||||
device_type = "memory";
|
||||
reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
|
||||
};
|
||||
|
||||
clock_si5338_2: clk26 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <26000000>;
|
||||
};
|
||||
|
||||
clock_si5338_3: clk125 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <125000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&fpd_dma_chan1 {
|
||||
@@ -107,6 +122,20 @@ &i2c1 {
|
||||
clock-frequency = <400000>;
|
||||
};
|
||||
|
||||
/* MT29F64G08AECDBJ4-6 */
|
||||
&nand0 {
|
||||
status = "okay";
|
||||
arasan,has-mdma;
|
||||
num-cs = <2>;
|
||||
};
|
||||
|
||||
&psgtr {
|
||||
status = "okay";
|
||||
/* usb3, sata */
|
||||
clocks = <&clock_si5338_2>, <&clock_si5338_3>;
|
||||
clock-names = "ref2", "ref3";
|
||||
};
|
||||
|
||||
&rtc {
|
||||
status = "okay";
|
||||
};
|
||||
@@ -122,6 +151,8 @@ &sata {
|
||||
ceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;
|
||||
ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
|
||||
ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
|
||||
phy-names = "sata-phy";
|
||||
phys = <&psgtr 2 PHY_TYPE_SATA 0 3>;
|
||||
};
|
||||
|
||||
&sdhci1 { /* emmc with some settings */
|
||||
@@ -139,12 +170,28 @@ &uart1 {
|
||||
};
|
||||
|
||||
&usb0 {
|
||||
status = "okay";
|
||||
phy-names = "usb3-phy";
|
||||
phys = <&psgtr 0 PHY_TYPE_USB3 0 2>;
|
||||
};
|
||||
|
||||
&dwc3_0 {
|
||||
status = "okay";
|
||||
dr_mode = "host";
|
||||
snps,usb3_lpm_capable;
|
||||
maximum-speed = "super-speed";
|
||||
};
|
||||
|
||||
/* ULPI SMSC USB3320 */
|
||||
&usb1 {
|
||||
status = "okay";
|
||||
dr_mode = "host";
|
||||
phy-names = "usb3-phy";
|
||||
phys = <&psgtr 3 PHY_TYPE_USB3 1 2>;
|
||||
};
|
||||
|
||||
&dwc3_1 {
|
||||
status = "okay";
|
||||
dr_mode = "host";
|
||||
snps,usb3_lpm_capable;
|
||||
maximum-speed = "super-speed";
|
||||
};
|
||||
|
||||
@@ -2,7 +2,7 @@
|
||||
/*
|
||||
* dts file for Xilinx ZynqMP zc1751-xm018-dc4
|
||||
*
|
||||
* (C) Copyright 2015 - 2019, Xilinx, Inc.
|
||||
* (C) Copyright 2015 - 2021, Xilinx, Inc.
|
||||
*
|
||||
* Michal Simek <michal.simek@xilinx.com>
|
||||
*/
|
||||
@@ -26,6 +26,7 @@ aliases {
|
||||
rtc0 = &rtc;
|
||||
serial0 = &uart0;
|
||||
serial1 = &uart1;
|
||||
spi0 = &qspi;
|
||||
};
|
||||
|
||||
chosen {
|
||||
@@ -161,6 +162,19 @@ &i2c1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&qspi {
|
||||
status = "okay";
|
||||
flash@0 {
|
||||
compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x0>;
|
||||
spi-tx-bus-width = <1>;
|
||||
spi-rx-bus-width = <4>; /* also DUAL configuration possible */
|
||||
spi-max-frequency = <108000000>; /* Based on DC1 spec */
|
||||
};
|
||||
};
|
||||
|
||||
&rtc {
|
||||
status = "okay";
|
||||
};
|
||||
@@ -176,3 +190,11 @@ &uart1 {
|
||||
&watchdog0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&zynqmp_dpdma {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&zynqmp_dpsub {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
@@ -2,7 +2,7 @@
|
||||
/*
|
||||
* dts file for Xilinx ZynqMP zc1751-xm019-dc5
|
||||
*
|
||||
* (C) Copyright 2015 - 2019, Xilinx, Inc.
|
||||
* (C) Copyright 2015 - 2021, Xilinx, Inc.
|
||||
*
|
||||
* Siva Durga Prasad <siva.durga.paladugu@xilinx.com>
|
||||
* Michal Simek <michal.simek@xilinx.com>
|
||||
@@ -13,6 +13,7 @@
|
||||
#include "zynqmp.dtsi"
|
||||
#include "zynqmp-clk-ccf.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
|
||||
|
||||
/ {
|
||||
model = "ZynqMP zc1751-xm019-dc5 RevA";
|
||||
@@ -74,6 +75,8 @@ &gem1 {
|
||||
status = "okay";
|
||||
phy-handle = <&phy0>;
|
||||
phy-mode = "rgmii-id";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_gem1_default>;
|
||||
phy0: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
@@ -85,41 +88,366 @@ &gpio {
|
||||
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default", "gpio";
|
||||
pinctrl-0 = <&pinctrl_i2c0_default>;
|
||||
pinctrl-1 = <&pinctrl_i2c0_gpio>;
|
||||
scl-gpios = <&gpio 74 GPIO_ACTIVE_HIGH>;
|
||||
sda-gpios = <&gpio 75 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default", "gpio";
|
||||
pinctrl-0 = <&pinctrl_i2c1_default>;
|
||||
pinctrl-1 = <&pinctrl_i2c1_gpio>;
|
||||
scl-gpios = <&gpio 76 GPIO_ACTIVE_HIGH>;
|
||||
sda-gpios = <&gpio 77 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
};
|
||||
|
||||
&pinctrl0 {
|
||||
status = "okay";
|
||||
pinctrl_i2c0_default: i2c0-default {
|
||||
mux {
|
||||
groups = "i2c0_18_grp";
|
||||
function = "i2c0";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "i2c0_18_grp";
|
||||
bias-pull-up;
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_i2c0_gpio: i2c0-gpio {
|
||||
mux {
|
||||
groups = "gpio0_74_grp", "gpio0_75_grp";
|
||||
function = "gpio0";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "gpio0_74_grp", "gpio0_75_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_i2c1_default: i2c1-default {
|
||||
mux {
|
||||
groups = "i2c1_19_grp";
|
||||
function = "i2c1";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "i2c1_19_grp";
|
||||
bias-pull-up;
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_i2c1_gpio: i2c1-gpio {
|
||||
mux {
|
||||
groups = "gpio0_76_grp", "gpio0_77_grp";
|
||||
function = "gpio0";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "gpio0_76_grp", "gpio0_77_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_uart0_default: uart0-default {
|
||||
mux {
|
||||
groups = "uart0_17_grp";
|
||||
function = "uart0";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "uart0_17_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
|
||||
conf-rx {
|
||||
pins = "MIO70";
|
||||
bias-high-impedance;
|
||||
};
|
||||
|
||||
conf-tx {
|
||||
pins = "MIO71";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_uart1_default: uart1-default {
|
||||
mux {
|
||||
groups = "uart1_18_grp";
|
||||
function = "uart1";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "uart1_18_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
|
||||
conf-rx {
|
||||
pins = "MIO73";
|
||||
bias-high-impedance;
|
||||
};
|
||||
|
||||
conf-tx {
|
||||
pins = "MIO72";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_gem1_default: gem1-default {
|
||||
mux {
|
||||
function = "ethernet1";
|
||||
groups = "ethernet1_0_grp";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "ethernet1_0_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
|
||||
conf-rx {
|
||||
pins = "MIO44", "MIO45", "MIO46", "MIO47", "MIO48",
|
||||
"MIO49";
|
||||
bias-high-impedance;
|
||||
low-power-disable;
|
||||
};
|
||||
|
||||
conf-tx {
|
||||
pins = "MIO38", "MIO39", "MIO40", "MIO41", "MIO42",
|
||||
"MIO43";
|
||||
bias-disable;
|
||||
low-power-enable;
|
||||
};
|
||||
|
||||
mux-mdio {
|
||||
function = "mdio1";
|
||||
groups = "mdio1_0_grp";
|
||||
};
|
||||
|
||||
conf-mdio {
|
||||
groups = "mdio1_0_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_sdhci0_default: sdhci0-default {
|
||||
mux {
|
||||
groups = "sdio0_0_grp";
|
||||
function = "sdio0";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "sdio0_0_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
mux-cd {
|
||||
groups = "sdio0_cd_0_grp";
|
||||
function = "sdio0_cd";
|
||||
};
|
||||
|
||||
conf-cd {
|
||||
groups = "sdio0_cd_0_grp";
|
||||
bias-high-impedance;
|
||||
bias-pull-up;
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
|
||||
mux-wp {
|
||||
groups = "sdio0_wp_0_grp";
|
||||
function = "sdio0_wp";
|
||||
};
|
||||
|
||||
conf-wp {
|
||||
groups = "sdio0_wp_0_grp";
|
||||
bias-high-impedance;
|
||||
bias-pull-up;
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_watchdog0_default: watchdog0-default {
|
||||
mux-clk {
|
||||
groups = "swdt0_clk_1_grp";
|
||||
function = "swdt0_clk";
|
||||
};
|
||||
|
||||
conf-clk {
|
||||
groups = "swdt0_clk_1_grp";
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
mux-rst {
|
||||
groups = "swdt0_rst_1_grp";
|
||||
function = "swdt0_rst";
|
||||
};
|
||||
|
||||
conf-rst {
|
||||
groups = "swdt0_rst_1_grp";
|
||||
bias-disable;
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_ttc0_default: ttc0-default {
|
||||
mux-clk {
|
||||
groups = "ttc0_clk_0_grp";
|
||||
function = "ttc0_clk";
|
||||
};
|
||||
|
||||
conf-clk {
|
||||
groups = "ttc0_clk_0_grp";
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
mux-wav {
|
||||
groups = "ttc0_wav_0_grp";
|
||||
function = "ttc0_wav";
|
||||
};
|
||||
|
||||
conf-wav {
|
||||
groups = "ttc0_wav_0_grp";
|
||||
bias-disable;
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_ttc1_default: ttc1-default {
|
||||
mux-clk {
|
||||
groups = "ttc1_clk_0_grp";
|
||||
function = "ttc1_clk";
|
||||
};
|
||||
|
||||
conf-clk {
|
||||
groups = "ttc1_clk_0_grp";
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
mux-wav {
|
||||
groups = "ttc1_wav_0_grp";
|
||||
function = "ttc1_wav";
|
||||
};
|
||||
|
||||
conf-wav {
|
||||
groups = "ttc1_wav_0_grp";
|
||||
bias-disable;
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_ttc2_default: ttc2-default {
|
||||
mux-clk {
|
||||
groups = "ttc2_clk_0_grp";
|
||||
function = "ttc2_clk";
|
||||
};
|
||||
|
||||
conf-clk {
|
||||
groups = "ttc2_clk_0_grp";
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
mux-wav {
|
||||
groups = "ttc2_wav_0_grp";
|
||||
function = "ttc2_wav";
|
||||
};
|
||||
|
||||
conf-wav {
|
||||
groups = "ttc2_wav_0_grp";
|
||||
bias-disable;
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_ttc3_default: ttc3-default {
|
||||
mux-clk {
|
||||
groups = "ttc3_clk_0_grp";
|
||||
function = "ttc3_clk";
|
||||
};
|
||||
|
||||
conf-clk {
|
||||
groups = "ttc3_clk_0_grp";
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
mux-wav {
|
||||
groups = "ttc3_wav_0_grp";
|
||||
function = "ttc3_wav";
|
||||
};
|
||||
|
||||
conf-wav {
|
||||
groups = "ttc3_wav_0_grp";
|
||||
bias-disable;
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&sdhci0 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_sdhci0_default>;
|
||||
no-1-8-v;
|
||||
xlnx,mio-bank = <0>;
|
||||
};
|
||||
|
||||
&ttc0 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_ttc0_default>;
|
||||
};
|
||||
|
||||
&ttc1 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_ttc1_default>;
|
||||
};
|
||||
|
||||
&ttc2 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_ttc2_default>;
|
||||
};
|
||||
|
||||
&ttc3 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_ttc3_default>;
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart0_default>;
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart1_default>;
|
||||
};
|
||||
|
||||
&watchdog0 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_watchdog0_default>;
|
||||
};
|
||||
|
||||
@@ -2,7 +2,7 @@
|
||||
/*
|
||||
* dts file for Xilinx ZynqMP ZCU100 revC
|
||||
*
|
||||
* (C) Copyright 2016 - 2019, Xilinx, Inc.
|
||||
* (C) Copyright 2016 - 2021, Xilinx, Inc.
|
||||
*
|
||||
* Michal Simek <michal.simek@xilinx.com>
|
||||
* Nathalie Chan King Choy
|
||||
@@ -15,6 +15,7 @@
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
|
||||
#include <dt-bindings/phy/phy.h>
|
||||
|
||||
/ {
|
||||
@@ -29,6 +30,8 @@ aliases {
|
||||
serial2 = &dcc;
|
||||
spi0 = &spi0;
|
||||
spi1 = &spi1;
|
||||
usb0 = &usb0;
|
||||
usb1 = &usb1;
|
||||
mmc0 = &sdhci0;
|
||||
mmc1 = &sdhci1;
|
||||
};
|
||||
@@ -110,13 +113,13 @@ ina226 {
|
||||
io-channels = <&u35 0>, <&u35 1>, <&u35 2>, <&u35 3>;
|
||||
};
|
||||
|
||||
si5335a_0: clk26 {
|
||||
si5335_0: si5335_0 { /* clk0_usb - u23 */
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <26000000>;
|
||||
};
|
||||
|
||||
si5335a_1: clk27 {
|
||||
si5335_1: si5335_1 { /* clk1_dp - u23 */
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <27000000>;
|
||||
@@ -160,6 +163,11 @@ &gpio {
|
||||
|
||||
&i2c1 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default", "gpio";
|
||||
pinctrl-0 = <&pinctrl_i2c1_default>;
|
||||
pinctrl-1 = <&pinctrl_i2c1_gpio>;
|
||||
scl-gpios = <&gpio 4 GPIO_ACTIVE_HIGH>;
|
||||
sda-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>;
|
||||
clock-frequency = <100000>;
|
||||
i2c-mux@75 { /* u11 */
|
||||
compatible = "nxp,pca9548";
|
||||
@@ -237,10 +245,225 @@ i2csw_7: i2c@7 {
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl0 {
|
||||
status = "okay";
|
||||
pinctrl_i2c1_default: i2c1-default {
|
||||
mux {
|
||||
groups = "i2c1_1_grp";
|
||||
function = "i2c1";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "i2c1_1_grp";
|
||||
bias-pull-up;
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_i2c1_gpio: i2c1-gpio {
|
||||
mux {
|
||||
groups = "gpio0_4_grp", "gpio0_5_grp";
|
||||
function = "gpio0";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "gpio0_4_grp", "gpio0_5_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_sdhci0_default: sdhci0-default {
|
||||
mux {
|
||||
groups = "sdio0_3_grp";
|
||||
function = "sdio0";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "sdio0_3_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
mux-cd {
|
||||
groups = "sdio0_cd_0_grp";
|
||||
function = "sdio0_cd";
|
||||
};
|
||||
|
||||
conf-cd {
|
||||
groups = "sdio0_cd_0_grp";
|
||||
bias-high-impedance;
|
||||
bias-pull-up;
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_sdhci1_default: sdhci1-default {
|
||||
mux {
|
||||
groups = "sdio1_2_grp";
|
||||
function = "sdio1";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "sdio1_2_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_spi0_default: spi0-default {
|
||||
mux {
|
||||
groups = "spi0_3_grp";
|
||||
function = "spi0";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "spi0_3_grp";
|
||||
bias-disable;
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
|
||||
mux-cs {
|
||||
groups = "spi0_ss_9_grp";
|
||||
function = "spi0_ss";
|
||||
};
|
||||
|
||||
conf-cs {
|
||||
groups = "spi0_ss_9_grp";
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
pinctrl_spi1_default: spi1-default {
|
||||
mux {
|
||||
groups = "spi1_0_grp";
|
||||
function = "spi1";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "spi1_0_grp";
|
||||
bias-disable;
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
|
||||
mux-cs {
|
||||
groups = "spi1_ss_0_grp";
|
||||
function = "spi1_ss";
|
||||
};
|
||||
|
||||
conf-cs {
|
||||
groups = "spi1_ss_0_grp";
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
pinctrl_uart0_default: uart0-default {
|
||||
mux {
|
||||
groups = "uart0_0_grp";
|
||||
function = "uart0";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "uart0_0_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
|
||||
conf-rx {
|
||||
pins = "MIO3";
|
||||
bias-high-impedance;
|
||||
};
|
||||
|
||||
conf-tx {
|
||||
pins = "MIO2";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_uart1_default: uart1-default {
|
||||
mux {
|
||||
groups = "uart1_0_grp";
|
||||
function = "uart1";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "uart1_0_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
|
||||
conf-rx {
|
||||
pins = "MIO1";
|
||||
bias-high-impedance;
|
||||
};
|
||||
|
||||
conf-tx {
|
||||
pins = "MIO0";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_usb0_default: usb0-default {
|
||||
mux {
|
||||
groups = "usb0_0_grp";
|
||||
function = "usb0";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "usb0_0_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
|
||||
conf-rx {
|
||||
pins = "MIO52", "MIO53", "MIO55";
|
||||
bias-high-impedance;
|
||||
};
|
||||
|
||||
conf-tx {
|
||||
pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
|
||||
"MIO60", "MIO61", "MIO62", "MIO63";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_usb1_default: usb1-default {
|
||||
mux {
|
||||
groups = "usb1_0_grp";
|
||||
function = "usb1";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "usb1_0_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
|
||||
conf-rx {
|
||||
pins = "MIO64", "MIO65", "MIO67";
|
||||
bias-high-impedance;
|
||||
};
|
||||
|
||||
conf-tx {
|
||||
pins = "MIO66", "MIO68", "MIO69", "MIO70", "MIO71",
|
||||
"MIO72", "MIO73", "MIO74", "MIO75";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&psgtr {
|
||||
status = "okay";
|
||||
/* usb3, dps */
|
||||
clocks = <&si5335a_0>, <&si5335a_1>;
|
||||
/* usb3, dp */
|
||||
clocks = <&si5335_0>, <&si5335_1>;
|
||||
clock-names = "ref0", "ref1";
|
||||
};
|
||||
|
||||
@@ -253,12 +476,16 @@ &sdhci0 {
|
||||
status = "okay";
|
||||
no-1-8-v;
|
||||
disable-wp;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_sdhci0_default>;
|
||||
xlnx,mio-bank = <0>;
|
||||
};
|
||||
|
||||
&sdhci1 {
|
||||
status = "okay";
|
||||
bus-width = <0x4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_sdhci1_default>;
|
||||
xlnx,mio-bank = <0>;
|
||||
non-removable;
|
||||
disable-wp;
|
||||
@@ -279,16 +506,22 @@ &spi0 { /* Low Speed connector */
|
||||
status = "okay";
|
||||
label = "LS-SPI0";
|
||||
num-cs = <1>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_spi0_default>;
|
||||
};
|
||||
|
||||
&spi1 { /* High Speed connector */
|
||||
status = "okay";
|
||||
label = "HS-SPI1";
|
||||
num-cs = <1>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_spi1_default>;
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart0_default>;
|
||||
bluetooth {
|
||||
compatible = "ti,wl1831-st";
|
||||
enable-gpios = <&gpio 8 GPIO_ACTIVE_HIGH>;
|
||||
@@ -297,19 +530,38 @@ bluetooth {
|
||||
|
||||
&uart1 {
|
||||
status = "okay";
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart1_default>;
|
||||
};
|
||||
|
||||
/* ULPI SMSC USB3320 */
|
||||
&usb0 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usb0_default>;
|
||||
phy-names = "usb3-phy";
|
||||
phys = <&psgtr 2 PHY_TYPE_USB3 0 0>;
|
||||
};
|
||||
|
||||
&dwc3_0 {
|
||||
status = "okay";
|
||||
dr_mode = "peripheral";
|
||||
maximum-speed = "super-speed";
|
||||
};
|
||||
|
||||
/* ULPI SMSC USB3320 */
|
||||
&usb1 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usb1_default>;
|
||||
phy-names = "usb3-phy";
|
||||
phys = <&psgtr 3 PHY_TYPE_USB3 1 0>;
|
||||
};
|
||||
|
||||
&dwc3_1 {
|
||||
status = "okay";
|
||||
dr_mode = "host";
|
||||
maximum-speed = "super-speed";
|
||||
};
|
||||
|
||||
&watchdog0 {
|
||||
|
||||
15
arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.1.dts
Normal file
15
arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.1.dts
Normal file
@@ -0,0 +1,15 @@
|
||||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* dts file for Xilinx ZynqMP ZCU102 Rev1.1
|
||||
*
|
||||
* (C) Copyright 2016 - 2020, Xilinx, Inc.
|
||||
*
|
||||
* Michal Simek <michal.simek@xilinx.com>
|
||||
*/
|
||||
|
||||
#include "zynqmp-zcu102-rev1.0.dts"
|
||||
|
||||
/ {
|
||||
model = "ZynqMP ZCU102 Rev1.1";
|
||||
compatible = "xlnx,zynqmp-zcu102-rev1.1", "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
|
||||
};
|
||||
@@ -2,7 +2,7 @@
|
||||
/*
|
||||
* dts file for Xilinx ZynqMP ZCU102 RevA
|
||||
*
|
||||
* (C) Copyright 2015 - 2019, Xilinx, Inc.
|
||||
* (C) Copyright 2015 - 2021, Xilinx, Inc.
|
||||
*
|
||||
* Michal Simek <michal.simek@xilinx.com>
|
||||
*/
|
||||
@@ -13,6 +13,7 @@
|
||||
#include "zynqmp-clk-ccf.dtsi"
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
|
||||
#include <dt-bindings/phy/phy.h>
|
||||
|
||||
/ {
|
||||
@@ -24,10 +25,13 @@ aliases {
|
||||
i2c0 = &i2c0;
|
||||
i2c1 = &i2c1;
|
||||
mmc0 = &sdhci1;
|
||||
nvmem0 = &eeprom;
|
||||
rtc0 = &rtc;
|
||||
serial0 = &uart0;
|
||||
serial1 = &uart1;
|
||||
serial2 = &dcc;
|
||||
spi0 = &qspi;
|
||||
usb0 = &usb0;
|
||||
};
|
||||
|
||||
chosen {
|
||||
@@ -150,6 +154,8 @@ refhdmi: refhdmi {
|
||||
|
||||
&can1 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_can1_default>;
|
||||
};
|
||||
|
||||
&dcc {
|
||||
@@ -192,22 +198,32 @@ &gem3 {
|
||||
status = "okay";
|
||||
phy-handle = <&phy0>;
|
||||
phy-mode = "rgmii-id";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_gem3_default>;
|
||||
phy0: ethernet-phy@21 {
|
||||
reg = <21>;
|
||||
ti,rx-internal-delay = <0x8>;
|
||||
ti,tx-internal-delay = <0xa>;
|
||||
ti,fifo-depth = <0x1>;
|
||||
ti,dp83867-rxctrl-strap-quirk;
|
||||
/* reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; */
|
||||
};
|
||||
};
|
||||
|
||||
&gpio {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_gpio_default>;
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
pinctrl-names = "default", "gpio";
|
||||
pinctrl-0 = <&pinctrl_i2c0_default>;
|
||||
pinctrl-1 = <&pinctrl_i2c0_gpio>;
|
||||
scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;
|
||||
sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
tca6416_u97: gpio@20 {
|
||||
compatible = "ti,tca6416";
|
||||
@@ -451,7 +467,6 @@ max15303@20 { /* u8 */
|
||||
status = "disabled"; /* unreachable */
|
||||
reg = <0x20>;
|
||||
};
|
||||
|
||||
max20751@72 { /* u95 */
|
||||
compatible = "maxim,max20751";
|
||||
reg = <0x72>;
|
||||
@@ -468,6 +483,11 @@ max20751@73 { /* u96 */
|
||||
&i2c1 {
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
pinctrl-names = "default", "gpio";
|
||||
pinctrl-0 = <&pinctrl_i2c1_default>;
|
||||
pinctrl-1 = <&pinctrl_i2c1_gpio>;
|
||||
scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;
|
||||
sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
/* PL i2c via PCA9306 - u45 */
|
||||
i2c-mux@74 { /* u34 */
|
||||
@@ -642,6 +662,269 @@ i2c@7 {
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl0 {
|
||||
status = "okay";
|
||||
pinctrl_i2c0_default: i2c0-default {
|
||||
mux {
|
||||
groups = "i2c0_3_grp";
|
||||
function = "i2c0";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "i2c0_3_grp";
|
||||
bias-pull-up;
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_i2c0_gpio: i2c0-gpio {
|
||||
mux {
|
||||
groups = "gpio0_14_grp", "gpio0_15_grp";
|
||||
function = "gpio0";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "gpio0_14_grp", "gpio0_15_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_i2c1_default: i2c1-default {
|
||||
mux {
|
||||
groups = "i2c1_4_grp";
|
||||
function = "i2c1";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "i2c1_4_grp";
|
||||
bias-pull-up;
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_i2c1_gpio: i2c1-gpio {
|
||||
mux {
|
||||
groups = "gpio0_16_grp", "gpio0_17_grp";
|
||||
function = "gpio0";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "gpio0_16_grp", "gpio0_17_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_uart0_default: uart0-default {
|
||||
mux {
|
||||
groups = "uart0_4_grp";
|
||||
function = "uart0";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "uart0_4_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
|
||||
conf-rx {
|
||||
pins = "MIO18";
|
||||
bias-high-impedance;
|
||||
};
|
||||
|
||||
conf-tx {
|
||||
pins = "MIO19";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_uart1_default: uart1-default {
|
||||
mux {
|
||||
groups = "uart1_5_grp";
|
||||
function = "uart1";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "uart1_5_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
|
||||
conf-rx {
|
||||
pins = "MIO21";
|
||||
bias-high-impedance;
|
||||
};
|
||||
|
||||
conf-tx {
|
||||
pins = "MIO20";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_usb0_default: usb0-default {
|
||||
mux {
|
||||
groups = "usb0_0_grp";
|
||||
function = "usb0";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "usb0_0_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
|
||||
conf-rx {
|
||||
pins = "MIO52", "MIO53", "MIO55";
|
||||
bias-high-impedance;
|
||||
};
|
||||
|
||||
conf-tx {
|
||||
pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
|
||||
"MIO60", "MIO61", "MIO62", "MIO63";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_gem3_default: gem3-default {
|
||||
mux {
|
||||
function = "ethernet3";
|
||||
groups = "ethernet3_0_grp";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "ethernet3_0_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
|
||||
conf-rx {
|
||||
pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74",
|
||||
"MIO75";
|
||||
bias-high-impedance;
|
||||
low-power-disable;
|
||||
};
|
||||
|
||||
conf-tx {
|
||||
pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68",
|
||||
"MIO69";
|
||||
bias-disable;
|
||||
low-power-enable;
|
||||
};
|
||||
|
||||
mux-mdio {
|
||||
function = "mdio3";
|
||||
groups = "mdio3_0_grp";
|
||||
};
|
||||
|
||||
conf-mdio {
|
||||
groups = "mdio3_0_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_can1_default: can1-default {
|
||||
mux {
|
||||
function = "can1";
|
||||
groups = "can1_6_grp";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "can1_6_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
|
||||
conf-rx {
|
||||
pins = "MIO25";
|
||||
bias-high-impedance;
|
||||
};
|
||||
|
||||
conf-tx {
|
||||
pins = "MIO24";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_sdhci1_default: sdhci1-default {
|
||||
mux {
|
||||
groups = "sdio1_0_grp";
|
||||
function = "sdio1";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "sdio1_0_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
mux-cd {
|
||||
groups = "sdio1_cd_0_grp";
|
||||
function = "sdio1_cd";
|
||||
};
|
||||
|
||||
conf-cd {
|
||||
groups = "sdio1_cd_0_grp";
|
||||
bias-high-impedance;
|
||||
bias-pull-up;
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
|
||||
mux-wp {
|
||||
groups = "sdio1_wp_0_grp";
|
||||
function = "sdio1_wp";
|
||||
};
|
||||
|
||||
conf-wp {
|
||||
groups = "sdio1_wp_0_grp";
|
||||
bias-high-impedance;
|
||||
bias-pull-up;
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_gpio_default: gpio-default {
|
||||
mux-sw {
|
||||
function = "gpio0";
|
||||
groups = "gpio0_22_grp", "gpio0_23_grp";
|
||||
};
|
||||
|
||||
conf-sw {
|
||||
groups = "gpio0_22_grp", "gpio0_23_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
|
||||
mux-msp {
|
||||
function = "gpio0";
|
||||
groups = "gpio0_13_grp", "gpio0_38_grp";
|
||||
};
|
||||
|
||||
conf-msp {
|
||||
groups = "gpio0_13_grp", "gpio0_38_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
|
||||
conf-pull-up {
|
||||
pins = "MIO22", "MIO23";
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
conf-pull-none {
|
||||
pins = "MIO13", "MIO38";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pcie {
|
||||
status = "okay";
|
||||
};
|
||||
@@ -653,6 +936,19 @@ &psgtr {
|
||||
clock-names = "ref0", "ref1", "ref2", "ref3";
|
||||
};
|
||||
|
||||
&qspi {
|
||||
status = "okay";
|
||||
flash@0 {
|
||||
compatible = "m25p80", "jedec,spi-nor"; /* 16MB + 16MB */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x0>;
|
||||
spi-tx-bus-width = <1>;
|
||||
spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
|
||||
spi-max-frequency = <108000000>; /* Based on DC1 spec */
|
||||
};
|
||||
};
|
||||
|
||||
&rtc {
|
||||
status = "okay";
|
||||
};
|
||||
@@ -675,22 +971,42 @@ &sata {
|
||||
/* SD1 with level shifter */
|
||||
&sdhci1 {
|
||||
status = "okay";
|
||||
/*
|
||||
* 1.0 revision has level shifter and this property should be
|
||||
* removed for supporting UHS mode
|
||||
*/
|
||||
no-1-8-v;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_sdhci1_default>;
|
||||
xlnx,mio-bank = <1>;
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart0_default>;
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart1_default>;
|
||||
};
|
||||
|
||||
/* ULPI SMSC USB3320 */
|
||||
&usb0 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usb0_default>;
|
||||
phy-names = "usb3-phy";
|
||||
phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
|
||||
};
|
||||
|
||||
&dwc3_0 {
|
||||
status = "okay";
|
||||
dr_mode = "host";
|
||||
snps,usb3_lpm_capable;
|
||||
maximum-speed = "super-speed";
|
||||
};
|
||||
|
||||
&watchdog0 {
|
||||
|
||||
@@ -2,7 +2,7 @@
|
||||
/*
|
||||
* dts file for Xilinx ZynqMP ZCU102 RevB
|
||||
*
|
||||
* (C) Copyright 2016 - 2018, Xilinx, Inc.
|
||||
* (C) Copyright 2016 - 2021, Xilinx, Inc.
|
||||
*
|
||||
* Michal Simek <michal.simek@xilinx.com>
|
||||
*/
|
||||
@@ -22,6 +22,7 @@ phyc: ethernet-phy@c {
|
||||
ti,tx-internal-delay = <0xa>;
|
||||
ti,fifo-depth = <0x1>;
|
||||
ti,dp83867-rxctrl-strap-quirk;
|
||||
/* reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; */
|
||||
};
|
||||
/* Cleanup from RevA */
|
||||
/delete-node/ ethernet-phy@21;
|
||||
|
||||
@@ -2,7 +2,7 @@
|
||||
/*
|
||||
* dts file for Xilinx ZynqMP ZCU104
|
||||
*
|
||||
* (C) Copyright 2017 - 2019, Xilinx, Inc.
|
||||
* (C) Copyright 2017 - 2021, Xilinx, Inc.
|
||||
*
|
||||
* Michal Simek <michal.simek@xilinx.com>
|
||||
*/
|
||||
@@ -12,6 +12,7 @@
|
||||
#include "zynqmp.dtsi"
|
||||
#include "zynqmp-clk-ccf.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
|
||||
#include <dt-bindings/phy/phy.h>
|
||||
|
||||
/ {
|
||||
@@ -22,10 +23,13 @@ aliases {
|
||||
ethernet0 = &gem3;
|
||||
i2c0 = &i2c1;
|
||||
mmc0 = &sdhci1;
|
||||
nvmem0 = &eeprom;
|
||||
rtc0 = &rtc;
|
||||
serial0 = &uart0;
|
||||
serial1 = &uart1;
|
||||
serial2 = &dcc;
|
||||
spi0 = &qspi;
|
||||
usb0 = &usb0;
|
||||
};
|
||||
|
||||
chosen {
|
||||
@@ -59,16 +63,52 @@ clock_8t49n287_3: clk27 {
|
||||
|
||||
&can1 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_can1_default>;
|
||||
};
|
||||
|
||||
&dcc {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fpd_dma_chan1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fpd_dma_chan2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fpd_dma_chan3 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fpd_dma_chan4 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fpd_dma_chan5 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fpd_dma_chan6 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fpd_dma_chan7 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fpd_dma_chan8 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gem3 {
|
||||
status = "okay";
|
||||
phy-handle = <&phy0>;
|
||||
phy-mode = "rgmii-id";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_gem3_default>;
|
||||
phy0: ethernet-phy@c {
|
||||
reg = <0xc>;
|
||||
ti,rx-internal-delay = <0x8>;
|
||||
@@ -85,6 +125,11 @@ &gpio {
|
||||
&i2c1 {
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
pinctrl-names = "default", "gpio";
|
||||
pinctrl-0 = <&pinctrl_i2c1_default>;
|
||||
pinctrl-1 = <&pinctrl_i2c1_gpio>;
|
||||
scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;
|
||||
sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
/* Another connection to this bus via PL i2c via PCA9306 - u45 */
|
||||
i2c-mux@74 { /* u34 */
|
||||
@@ -104,7 +149,7 @@ i2c@0 {
|
||||
* 512B - 768B address 0x56
|
||||
* 768B - 1024B address 0x57
|
||||
*/
|
||||
eeprom@54 { /* u23 */
|
||||
eeprom: eeprom@54 { /* u23 */
|
||||
compatible = "atmel,24c08";
|
||||
reg = <0x54>;
|
||||
#address-cells = <1>;
|
||||
@@ -116,20 +161,20 @@ i2c@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <1>;
|
||||
clock_8t49n287: clock-generator@6c { /* 8T49N287 - u182 */
|
||||
reg = <0x6c>;
|
||||
};
|
||||
/* 8T49N287 - u182 */
|
||||
};
|
||||
|
||||
i2c@2 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <2>;
|
||||
irps5401_43: irps54012@43 { /* IRPS5401 - u175 */
|
||||
reg = <0x43>;
|
||||
irps5401_43: irps5401@43 { /* IRPS5401 - u175 */
|
||||
compatible = "infineon,irps5401";
|
||||
reg = <0x43>; /* pmbus / i2c 0x13 */
|
||||
};
|
||||
irps5401_4d: irps54012@4d { /* IRPS5401 - u180 */
|
||||
reg = <0x4d>;
|
||||
irps5401_44: irps5401@44 { /* IRPS5401 - u180 */
|
||||
compatible = "infineon,irps5401";
|
||||
reg = <0x44>; /* pmbus / i2c 0x14 */
|
||||
};
|
||||
};
|
||||
|
||||
@@ -173,8 +218,202 @@ i2c@7 {
|
||||
};
|
||||
};
|
||||
|
||||
&rtc {
|
||||
&pinctrl0 {
|
||||
status = "okay";
|
||||
|
||||
pinctrl_can1_default: can1-default {
|
||||
mux {
|
||||
function = "can1";
|
||||
groups = "can1_6_grp";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "can1_6_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
drive-strength = <12>;
|
||||
};
|
||||
|
||||
conf-rx {
|
||||
pins = "MIO25";
|
||||
bias-high-impedance;
|
||||
};
|
||||
|
||||
conf-tx {
|
||||
pins = "MIO24";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_i2c1_default: i2c1-default {
|
||||
mux {
|
||||
groups = "i2c1_4_grp";
|
||||
function = "i2c1";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "i2c1_4_grp";
|
||||
bias-pull-up;
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
drive-strength = <12>;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_i2c1_gpio: i2c1-gpio {
|
||||
mux {
|
||||
groups = "gpio0_16_grp", "gpio0_17_grp";
|
||||
function = "gpio0";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "gpio0_16_grp", "gpio0_17_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
drive-strength = <12>;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_gem3_default: gem3-default {
|
||||
mux {
|
||||
function = "ethernet3";
|
||||
groups = "ethernet3_0_grp";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "ethernet3_0_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
drive-strength = <12>;
|
||||
};
|
||||
|
||||
conf-rx {
|
||||
pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74",
|
||||
"MIO75";
|
||||
bias-high-impedance;
|
||||
low-power-disable;
|
||||
};
|
||||
|
||||
conf-tx {
|
||||
pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68",
|
||||
"MIO69";
|
||||
bias-disable;
|
||||
low-power-enable;
|
||||
};
|
||||
|
||||
mux-mdio {
|
||||
function = "mdio3";
|
||||
groups = "mdio3_0_grp";
|
||||
};
|
||||
|
||||
conf-mdio {
|
||||
groups = "mdio3_0_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_sdhci1_default: sdhci1-default {
|
||||
mux {
|
||||
groups = "sdio1_0_grp";
|
||||
function = "sdio1";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "sdio1_0_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
bias-disable;
|
||||
drive-strength = <12>;
|
||||
};
|
||||
|
||||
mux-cd {
|
||||
groups = "sdio1_cd_0_grp";
|
||||
function = "sdio1_cd";
|
||||
};
|
||||
|
||||
conf-cd {
|
||||
groups = "sdio1_cd_0_grp";
|
||||
bias-high-impedance;
|
||||
bias-pull-up;
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_uart0_default: uart0-default {
|
||||
mux {
|
||||
groups = "uart0_4_grp";
|
||||
function = "uart0";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "uart0_4_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
drive-strength = <12>;
|
||||
};
|
||||
|
||||
conf-rx {
|
||||
pins = "MIO18";
|
||||
bias-high-impedance;
|
||||
};
|
||||
|
||||
conf-tx {
|
||||
pins = "MIO19";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_uart1_default: uart1-default {
|
||||
mux {
|
||||
groups = "uart1_5_grp";
|
||||
function = "uart1";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "uart1_5_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
drive-strength = <12>;
|
||||
};
|
||||
|
||||
conf-rx {
|
||||
pins = "MIO21";
|
||||
bias-high-impedance;
|
||||
};
|
||||
|
||||
conf-tx {
|
||||
pins = "MIO20";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_usb0_default: usb0-default {
|
||||
mux {
|
||||
groups = "usb0_0_grp";
|
||||
function = "usb0";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "usb0_0_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
drive-strength = <12>;
|
||||
};
|
||||
|
||||
conf-rx {
|
||||
pins = "MIO52", "MIO53", "MIO55";
|
||||
bias-high-impedance;
|
||||
};
|
||||
|
||||
conf-tx {
|
||||
pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
|
||||
"MIO60", "MIO61", "MIO62", "MIO63";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&psgtr {
|
||||
@@ -184,6 +423,23 @@ &psgtr {
|
||||
clock-names = "ref1", "ref2", "ref3";
|
||||
};
|
||||
|
||||
&qspi {
|
||||
status = "okay";
|
||||
flash@0 {
|
||||
compatible = "m25p80", "jedec,spi-nor"; /* n25q512a 128MiB */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x0>;
|
||||
spi-tx-bus-width = <1>;
|
||||
spi-rx-bus-width = <4>;
|
||||
spi-max-frequency = <108000000>; /* Based on DC1 spec */
|
||||
};
|
||||
};
|
||||
|
||||
&rtc {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sata {
|
||||
status = "okay";
|
||||
/* SATA OOB timing settings */
|
||||
@@ -203,22 +459,38 @@ &sata {
|
||||
&sdhci1 {
|
||||
status = "okay";
|
||||
no-1-8-v;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_sdhci1_default>;
|
||||
xlnx,mio-bank = <1>;
|
||||
disable-wp;
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart0_default>;
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart1_default>;
|
||||
};
|
||||
|
||||
/* ULPI SMSC USB3320 */
|
||||
&usb0 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usb0_default>;
|
||||
phy-names = "usb3-phy";
|
||||
phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
|
||||
};
|
||||
|
||||
&dwc3_0 {
|
||||
status = "okay";
|
||||
dr_mode = "host";
|
||||
snps,usb3_lpm_capable;
|
||||
maximum-speed = "super-speed";
|
||||
};
|
||||
|
||||
&watchdog0 {
|
||||
|
||||
@@ -2,7 +2,7 @@
|
||||
/*
|
||||
* dts file for Xilinx ZynqMP ZCU104
|
||||
*
|
||||
* (C) Copyright 2017 - 2020, Xilinx, Inc.
|
||||
* (C) Copyright 2017 - 2021, Xilinx, Inc.
|
||||
*
|
||||
* Michal Simek <michal.simek@xilinx.com>
|
||||
*/
|
||||
@@ -12,6 +12,7 @@
|
||||
#include "zynqmp.dtsi"
|
||||
#include "zynqmp-clk-ccf.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
|
||||
#include <dt-bindings/phy/phy.h>
|
||||
|
||||
/ {
|
||||
@@ -22,10 +23,13 @@ aliases {
|
||||
ethernet0 = &gem3;
|
||||
i2c0 = &i2c1;
|
||||
mmc0 = &sdhci1;
|
||||
nvmem0 = &eeprom;
|
||||
rtc0 = &rtc;
|
||||
serial0 = &uart0;
|
||||
serial1 = &uart1;
|
||||
serial2 = &dcc;
|
||||
spi0 = &qspi;
|
||||
usb0 = &usb0;
|
||||
};
|
||||
|
||||
chosen {
|
||||
@@ -64,6 +68,8 @@ clock_8t49n287_3: clk27 {
|
||||
|
||||
&can1 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_can1_default>;
|
||||
};
|
||||
|
||||
&dcc {
|
||||
@@ -106,6 +112,8 @@ &gem3 {
|
||||
status = "okay";
|
||||
phy-handle = <&phy0>;
|
||||
phy-mode = "rgmii-id";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_gem3_default>;
|
||||
phy0: ethernet-phy@c {
|
||||
reg = <0xc>;
|
||||
ti,rx-internal-delay = <0x8>;
|
||||
@@ -122,6 +130,11 @@ &gpio {
|
||||
&i2c1 {
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
pinctrl-names = "default", "gpio";
|
||||
pinctrl-0 = <&pinctrl_i2c1_default>;
|
||||
pinctrl-1 = <&pinctrl_i2c1_gpio>;
|
||||
scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;
|
||||
sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
tca6416_u97: gpio@20 {
|
||||
compatible = "ti,tca6416";
|
||||
@@ -172,9 +185,7 @@ i2c@1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <1>;
|
||||
clock_8t49n287: clock-generator@6c { /* 8T49N287 - u182 */
|
||||
reg = <0x6c>;
|
||||
};
|
||||
/* 8T49N287 - u182 */
|
||||
};
|
||||
|
||||
i2c@2 {
|
||||
@@ -219,18 +230,202 @@ i2c@7 {
|
||||
};
|
||||
};
|
||||
|
||||
&qspi {
|
||||
&pinctrl0 {
|
||||
status = "okay";
|
||||
flash@0 {
|
||||
compatible = "m25p80", "jedec,spi-nor"; /* n25q512a 128MiB */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x0>;
|
||||
};
|
||||
};
|
||||
|
||||
&rtc {
|
||||
status = "okay";
|
||||
pinctrl_can1_default: can1-default {
|
||||
mux {
|
||||
function = "can1";
|
||||
groups = "can1_6_grp";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "can1_6_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
drive-strength = <12>;
|
||||
};
|
||||
|
||||
conf-rx {
|
||||
pins = "MIO25";
|
||||
bias-high-impedance;
|
||||
};
|
||||
|
||||
conf-tx {
|
||||
pins = "MIO24";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_i2c1_default: i2c1-default {
|
||||
mux {
|
||||
groups = "i2c1_4_grp";
|
||||
function = "i2c1";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "i2c1_4_grp";
|
||||
bias-pull-up;
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
drive-strength = <12>;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_i2c1_gpio: i2c1-gpio {
|
||||
mux {
|
||||
groups = "gpio0_16_grp", "gpio0_17_grp";
|
||||
function = "gpio0";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "gpio0_16_grp", "gpio0_17_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
drive-strength = <12>;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_gem3_default: gem3-default {
|
||||
mux {
|
||||
function = "ethernet3";
|
||||
groups = "ethernet3_0_grp";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "ethernet3_0_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
drive-strength = <12>;
|
||||
};
|
||||
|
||||
conf-rx {
|
||||
pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74",
|
||||
"MIO75";
|
||||
bias-high-impedance;
|
||||
low-power-disable;
|
||||
};
|
||||
|
||||
conf-tx {
|
||||
pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68",
|
||||
"MIO69";
|
||||
bias-disable;
|
||||
low-power-enable;
|
||||
};
|
||||
|
||||
mux-mdio {
|
||||
function = "mdio3";
|
||||
groups = "mdio3_0_grp";
|
||||
};
|
||||
|
||||
conf-mdio {
|
||||
groups = "mdio3_0_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_sdhci1_default: sdhci1-default {
|
||||
mux {
|
||||
groups = "sdio1_0_grp";
|
||||
function = "sdio1";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "sdio1_0_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
bias-disable;
|
||||
drive-strength = <12>;
|
||||
};
|
||||
|
||||
mux-cd {
|
||||
groups = "sdio1_cd_0_grp";
|
||||
function = "sdio1_cd";
|
||||
};
|
||||
|
||||
conf-cd {
|
||||
groups = "sdio1_cd_0_grp";
|
||||
bias-high-impedance;
|
||||
bias-pull-up;
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_uart0_default: uart0-default {
|
||||
mux {
|
||||
groups = "uart0_4_grp";
|
||||
function = "uart0";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "uart0_4_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
drive-strength = <12>;
|
||||
};
|
||||
|
||||
conf-rx {
|
||||
pins = "MIO18";
|
||||
bias-high-impedance;
|
||||
};
|
||||
|
||||
conf-tx {
|
||||
pins = "MIO19";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_uart1_default: uart1-default {
|
||||
mux {
|
||||
groups = "uart1_5_grp";
|
||||
function = "uart1";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "uart1_5_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
drive-strength = <12>;
|
||||
};
|
||||
|
||||
conf-rx {
|
||||
pins = "MIO21";
|
||||
bias-high-impedance;
|
||||
};
|
||||
|
||||
conf-tx {
|
||||
pins = "MIO20";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_usb0_default: usb0-default {
|
||||
mux {
|
||||
groups = "usb0_0_grp";
|
||||
function = "usb0";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "usb0_0_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
drive-strength = <12>;
|
||||
};
|
||||
|
||||
conf-rx {
|
||||
pins = "MIO52", "MIO53", "MIO55";
|
||||
bias-high-impedance;
|
||||
};
|
||||
|
||||
conf-tx {
|
||||
pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
|
||||
"MIO60", "MIO61", "MIO62", "MIO63";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&psgtr {
|
||||
@@ -240,6 +435,23 @@ &psgtr {
|
||||
clock-names = "ref1", "ref2", "ref3";
|
||||
};
|
||||
|
||||
&qspi {
|
||||
status = "okay";
|
||||
flash@0 {
|
||||
compatible = "m25p80", "jedec,spi-nor"; /* n25q512a 128MiB */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x0>;
|
||||
spi-tx-bus-width = <1>;
|
||||
spi-rx-bus-width = <4>;
|
||||
spi-max-frequency = <108000000>; /* Based on DC1 spec */
|
||||
};
|
||||
};
|
||||
|
||||
&rtc {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sata {
|
||||
status = "okay";
|
||||
/* SATA OOB timing settings */
|
||||
@@ -259,22 +471,38 @@ &sata {
|
||||
&sdhci1 {
|
||||
status = "okay";
|
||||
no-1-8-v;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_sdhci1_default>;
|
||||
xlnx,mio-bank = <1>;
|
||||
disable-wp;
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart0_default>;
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart1_default>;
|
||||
};
|
||||
|
||||
/* ULPI SMSC USB3320 */
|
||||
&usb0 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usb0_default>;
|
||||
phy-names = "usb3-phy";
|
||||
phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
|
||||
};
|
||||
|
||||
&dwc3_0 {
|
||||
status = "okay";
|
||||
dr_mode = "host";
|
||||
snps,usb3_lpm_capable;
|
||||
maximum-speed = "super-speed";
|
||||
};
|
||||
|
||||
&watchdog0 {
|
||||
|
||||
@@ -2,7 +2,7 @@
|
||||
/*
|
||||
* dts file for Xilinx ZynqMP ZCU106
|
||||
*
|
||||
* (C) Copyright 2016 - 2019, Xilinx, Inc.
|
||||
* (C) Copyright 2016 - 2021, Xilinx, Inc.
|
||||
*
|
||||
* Michal Simek <michal.simek@xilinx.com>
|
||||
*/
|
||||
@@ -13,6 +13,7 @@
|
||||
#include "zynqmp-clk-ccf.dtsi"
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
|
||||
#include <dt-bindings/phy/phy.h>
|
||||
|
||||
/ {
|
||||
@@ -24,10 +25,13 @@ aliases {
|
||||
i2c0 = &i2c0;
|
||||
i2c1 = &i2c1;
|
||||
mmc0 = &sdhci1;
|
||||
nvmem0 = &eeprom;
|
||||
rtc0 = &rtc;
|
||||
serial0 = &uart0;
|
||||
serial1 = &uart1;
|
||||
serial2 = &dcc;
|
||||
spi0 = &qspi;
|
||||
usb0 = &usb0;
|
||||
};
|
||||
|
||||
chosen {
|
||||
@@ -150,24 +154,14 @@ refhdmi: refhdmi {
|
||||
|
||||
&can1 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_can1_default>;
|
||||
};
|
||||
|
||||
&dcc {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&zynqmp_dpdma {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&zynqmp_dpsub {
|
||||
status = "okay";
|
||||
phy-names = "dp-phy0", "dp-phy1";
|
||||
phys = <&psgtr 1 PHY_TYPE_DP 0 3>,
|
||||
<&psgtr 0 PHY_TYPE_DP 1 3>;
|
||||
};
|
||||
|
||||
/* fpd_dma clk 667MHz, lpd_dma 500MHz */
|
||||
&fpd_dma_chan1 {
|
||||
status = "okay";
|
||||
};
|
||||
@@ -204,6 +198,8 @@ &gem3 {
|
||||
status = "okay";
|
||||
phy-handle = <&phy0>;
|
||||
phy-mode = "rgmii-id";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_gem3_default>;
|
||||
phy0: ethernet-phy@c {
|
||||
reg = <0xc>;
|
||||
ti,rx-internal-delay = <0x8>;
|
||||
@@ -215,11 +211,18 @@ phy0: ethernet-phy@c {
|
||||
|
||||
&gpio {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_gpio_default>;
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
pinctrl-names = "default", "gpio";
|
||||
pinctrl-0 = <&pinctrl_i2c0_default>;
|
||||
pinctrl-1 = <&pinctrl_i2c0_gpio>;
|
||||
scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;
|
||||
sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
tca6416_u97: gpio@20 {
|
||||
compatible = "ti,tca6416";
|
||||
@@ -478,6 +481,11 @@ max20751@73 { /* u96 */
|
||||
&i2c1 {
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
pinctrl-names = "default", "gpio";
|
||||
pinctrl-0 = <&pinctrl_i2c1_default>;
|
||||
pinctrl-1 = <&pinctrl_i2c1_gpio>;
|
||||
scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;
|
||||
sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
/* PL i2c via PCA9306 - u45 */
|
||||
i2c-mux@74 { /* u34 */
|
||||
@@ -652,6 +660,269 @@ i2c@7 {
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl0 {
|
||||
status = "okay";
|
||||
pinctrl_i2c0_default: i2c0-default {
|
||||
mux {
|
||||
groups = "i2c0_3_grp";
|
||||
function = "i2c0";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "i2c0_3_grp";
|
||||
bias-pull-up;
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_i2c0_gpio: i2c0-gpio {
|
||||
mux {
|
||||
groups = "gpio0_14_grp", "gpio0_15_grp";
|
||||
function = "gpio0";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "gpio0_14_grp", "gpio0_15_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_i2c1_default: i2c1-default {
|
||||
mux {
|
||||
groups = "i2c1_4_grp";
|
||||
function = "i2c1";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "i2c1_4_grp";
|
||||
bias-pull-up;
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_i2c1_gpio: i2c1-gpio {
|
||||
mux {
|
||||
groups = "gpio0_16_grp", "gpio0_17_grp";
|
||||
function = "gpio0";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "gpio0_16_grp", "gpio0_17_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_uart0_default: uart0-default {
|
||||
mux {
|
||||
groups = "uart0_4_grp";
|
||||
function = "uart0";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "uart0_4_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
|
||||
conf-rx {
|
||||
pins = "MIO18";
|
||||
bias-high-impedance;
|
||||
};
|
||||
|
||||
conf-tx {
|
||||
pins = "MIO19";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_uart1_default: uart1-default {
|
||||
mux {
|
||||
groups = "uart1_5_grp";
|
||||
function = "uart1";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "uart1_5_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
|
||||
conf-rx {
|
||||
pins = "MIO21";
|
||||
bias-high-impedance;
|
||||
};
|
||||
|
||||
conf-tx {
|
||||
pins = "MIO20";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_usb0_default: usb0-default {
|
||||
mux {
|
||||
groups = "usb0_0_grp";
|
||||
function = "usb0";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "usb0_0_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
|
||||
conf-rx {
|
||||
pins = "MIO52", "MIO53", "MIO55";
|
||||
bias-high-impedance;
|
||||
};
|
||||
|
||||
conf-tx {
|
||||
pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
|
||||
"MIO60", "MIO61", "MIO62", "MIO63";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_gem3_default: gem3-default {
|
||||
mux {
|
||||
function = "ethernet3";
|
||||
groups = "ethernet3_0_grp";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "ethernet3_0_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
|
||||
conf-rx {
|
||||
pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74",
|
||||
"MIO75";
|
||||
bias-high-impedance;
|
||||
low-power-disable;
|
||||
};
|
||||
|
||||
conf-tx {
|
||||
pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68",
|
||||
"MIO69";
|
||||
bias-disable;
|
||||
low-power-enable;
|
||||
};
|
||||
|
||||
mux-mdio {
|
||||
function = "mdio3";
|
||||
groups = "mdio3_0_grp";
|
||||
};
|
||||
|
||||
conf-mdio {
|
||||
groups = "mdio3_0_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_can1_default: can1-default {
|
||||
mux {
|
||||
function = "can1";
|
||||
groups = "can1_6_grp";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "can1_6_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
|
||||
conf-rx {
|
||||
pins = "MIO25";
|
||||
bias-high-impedance;
|
||||
};
|
||||
|
||||
conf-tx {
|
||||
pins = "MIO24";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_sdhci1_default: sdhci1-default {
|
||||
mux {
|
||||
groups = "sdio1_0_grp";
|
||||
function = "sdio1";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "sdio1_0_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
mux-cd {
|
||||
groups = "sdio1_cd_0_grp";
|
||||
function = "sdio1_cd";
|
||||
};
|
||||
|
||||
conf-cd {
|
||||
groups = "sdio1_cd_0_grp";
|
||||
bias-high-impedance;
|
||||
bias-pull-up;
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
|
||||
mux-wp {
|
||||
groups = "sdio1_wp_0_grp";
|
||||
function = "sdio1_wp";
|
||||
};
|
||||
|
||||
conf-wp {
|
||||
groups = "sdio1_wp_0_grp";
|
||||
bias-high-impedance;
|
||||
bias-pull-up;
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_gpio_default: gpio-default {
|
||||
mux {
|
||||
function = "gpio0";
|
||||
groups = "gpio0_22_grp", "gpio0_23_grp";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "gpio0_22_grp", "gpio0_23_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
|
||||
mux-msp {
|
||||
function = "gpio0";
|
||||
groups = "gpio0_13_grp", "gpio0_38_grp";
|
||||
};
|
||||
|
||||
conf-msp {
|
||||
groups = "gpio0_13_grp", "gpio0_38_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
|
||||
conf-pull-up {
|
||||
pins = "MIO22";
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
conf-pull-none {
|
||||
pins = "MIO13", "MIO23", "MIO38";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&psgtr {
|
||||
status = "okay";
|
||||
/* nc, sata, usb3, dp */
|
||||
@@ -659,6 +930,19 @@ &psgtr {
|
||||
clock-names = "ref1", "ref2", "ref3";
|
||||
};
|
||||
|
||||
&qspi {
|
||||
status = "okay";
|
||||
flash@0 {
|
||||
compatible = "m25p80", "jedec,spi-nor"; /* 16MB + 16MB */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x0>;
|
||||
spi-tx-bus-width = <1>;
|
||||
spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
|
||||
spi-max-frequency = <108000000>; /* Based on DC1 spec */
|
||||
};
|
||||
};
|
||||
|
||||
&rtc {
|
||||
status = "okay";
|
||||
};
|
||||
@@ -681,24 +965,54 @@ &sata {
|
||||
/* SD1 with level shifter */
|
||||
&sdhci1 {
|
||||
status = "okay";
|
||||
/*
|
||||
* This property should be removed for supporting UHS mode
|
||||
*/
|
||||
no-1-8-v;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_sdhci1_default>;
|
||||
xlnx,mio-bank = <1>;
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart0_default>;
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart1_default>;
|
||||
};
|
||||
|
||||
/* ULPI SMSC USB3320 */
|
||||
&usb0 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usb0_default>;
|
||||
phy-names = "usb3-phy";
|
||||
phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
|
||||
};
|
||||
|
||||
&dwc3_0 {
|
||||
status = "okay";
|
||||
dr_mode = "host";
|
||||
snps,usb3_lpm_capable;
|
||||
maximum-speed = "super-speed";
|
||||
};
|
||||
|
||||
&watchdog0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&zynqmp_dpdma {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&zynqmp_dpsub {
|
||||
status = "okay";
|
||||
phy-names = "dp-phy0", "dp-phy1";
|
||||
phys = <&psgtr 1 PHY_TYPE_DP 0 3>,
|
||||
<&psgtr 0 PHY_TYPE_DP 1 3>;
|
||||
};
|
||||
|
||||
@@ -2,7 +2,7 @@
|
||||
/*
|
||||
* dts file for Xilinx ZynqMP ZCU111
|
||||
*
|
||||
* (C) Copyright 2017 - 2019, Xilinx, Inc.
|
||||
* (C) Copyright 2017 - 2021, Xilinx, Inc.
|
||||
*
|
||||
* Michal Simek <michal.simek@xilinx.com>
|
||||
*/
|
||||
@@ -13,6 +13,7 @@
|
||||
#include "zynqmp-clk-ccf.dtsi"
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
|
||||
#include <dt-bindings/phy/phy.h>
|
||||
|
||||
/ {
|
||||
@@ -24,9 +25,12 @@ aliases {
|
||||
i2c0 = &i2c0;
|
||||
i2c1 = &i2c1;
|
||||
mmc0 = &sdhci1;
|
||||
nvmem0 = &eeprom;
|
||||
rtc0 = &rtc;
|
||||
serial0 = &uart0;
|
||||
serial1 = &dcc;
|
||||
spi0 = &qspi;
|
||||
usb0 = &usb0;
|
||||
};
|
||||
|
||||
chosen {
|
||||
@@ -166,6 +170,8 @@ &gem3 {
|
||||
status = "okay";
|
||||
phy-handle = <&phy0>;
|
||||
phy-mode = "rgmii-id";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_gem3_default>;
|
||||
phy0: ethernet-phy@c {
|
||||
reg = <0xc>;
|
||||
ti,rx-internal-delay = <0x8>;
|
||||
@@ -177,11 +183,18 @@ phy0: ethernet-phy@c {
|
||||
|
||||
&gpio {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_gpio_default>;
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
pinctrl-names = "default", "gpio";
|
||||
pinctrl-0 = <&pinctrl_i2c0_default>;
|
||||
pinctrl-1 = <&pinctrl_i2c0_gpio>;
|
||||
scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;
|
||||
sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
tca6416_u22: gpio@20 {
|
||||
compatible = "ti,tca6416";
|
||||
@@ -326,13 +339,16 @@ i2c@2 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <2>;
|
||||
irps5401_43: irps54012@43 { /* IRPS5401 - u53 check these */
|
||||
irps5401_43: irps5401@43 { /* IRPS5401 - u53 check these */
|
||||
compatible = "infineon,irps5401";
|
||||
reg = <0x43>;
|
||||
};
|
||||
irps5401_44: irps54012@44 { /* IRPS5401 - u55 */
|
||||
irps5401_44: irps5401@44 { /* IRPS5401 - u55 */
|
||||
compatible = "infineon,irps5401";
|
||||
reg = <0x44>;
|
||||
};
|
||||
irps5401_45: irps54012@45 { /* IRPS5401 - u57 */
|
||||
irps5401_45: irps5401@45 { /* IRPS5401 - u57 */
|
||||
compatible = "infineon,irps5401";
|
||||
reg = <0x45>;
|
||||
};
|
||||
/* u68 IR38064 +0 */
|
||||
@@ -354,6 +370,11 @@ i2c@3 {
|
||||
&i2c1 {
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
pinctrl-names = "default", "gpio";
|
||||
pinctrl-0 = <&pinctrl_i2c1_default>;
|
||||
pinctrl-1 = <&pinctrl_i2c1_gpio>;
|
||||
scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;
|
||||
sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
i2c-mux@74 { /* u26 */
|
||||
compatible = "nxp,pca9548";
|
||||
@@ -455,9 +476,7 @@ i2c@4 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <4>;
|
||||
si5382: clock-generator@69 { /* SI5382 - u48 */
|
||||
reg = <0x69>;
|
||||
};
|
||||
/* SI5382 - u48 */
|
||||
};
|
||||
i2c@5 {
|
||||
#address-cells = <1>;
|
||||
@@ -542,13 +561,230 @@ i2c@7 {
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl0 {
|
||||
status = "okay";
|
||||
pinctrl_i2c0_default: i2c0-default {
|
||||
mux {
|
||||
groups = "i2c0_3_grp";
|
||||
function = "i2c0";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "i2c0_3_grp";
|
||||
bias-pull-up;
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_i2c0_gpio: i2c0-gpio {
|
||||
mux {
|
||||
groups = "gpio0_14_grp", "gpio0_15_grp";
|
||||
function = "gpio0";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "gpio0_14_grp", "gpio0_15_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_i2c1_default: i2c1-default {
|
||||
mux {
|
||||
groups = "i2c1_4_grp";
|
||||
function = "i2c1";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "i2c1_4_grp";
|
||||
bias-pull-up;
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_i2c1_gpio: i2c1-gpio {
|
||||
mux {
|
||||
groups = "gpio0_16_grp", "gpio0_17_grp";
|
||||
function = "gpio0";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "gpio0_16_grp", "gpio0_17_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_uart0_default: uart0-default {
|
||||
mux {
|
||||
groups = "uart0_4_grp";
|
||||
function = "uart0";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "uart0_4_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
|
||||
conf-rx {
|
||||
pins = "MIO18";
|
||||
bias-high-impedance;
|
||||
};
|
||||
|
||||
conf-tx {
|
||||
pins = "MIO19";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_usb0_default: usb0-default {
|
||||
mux {
|
||||
groups = "usb0_0_grp";
|
||||
function = "usb0";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "usb0_0_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
|
||||
conf-rx {
|
||||
pins = "MIO52", "MIO53", "MIO55";
|
||||
bias-high-impedance;
|
||||
};
|
||||
|
||||
conf-tx {
|
||||
pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
|
||||
"MIO60", "MIO61", "MIO62", "MIO63";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_gem3_default: gem3-default {
|
||||
mux {
|
||||
function = "ethernet3";
|
||||
groups = "ethernet3_0_grp";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "ethernet3_0_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
|
||||
conf-rx {
|
||||
pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74",
|
||||
"MIO75";
|
||||
bias-high-impedance;
|
||||
low-power-disable;
|
||||
};
|
||||
|
||||
conf-tx {
|
||||
pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68",
|
||||
"MIO69";
|
||||
bias-disable;
|
||||
low-power-enable;
|
||||
};
|
||||
|
||||
mux-mdio {
|
||||
function = "mdio3";
|
||||
groups = "mdio3_0_grp";
|
||||
};
|
||||
|
||||
conf-mdio {
|
||||
groups = "mdio3_0_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_sdhci1_default: sdhci1-default {
|
||||
mux {
|
||||
groups = "sdio1_0_grp";
|
||||
function = "sdio1";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "sdio1_0_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
bias-disable;
|
||||
};
|
||||
|
||||
mux-cd {
|
||||
groups = "sdio1_cd_0_grp";
|
||||
function = "sdio1_cd";
|
||||
};
|
||||
|
||||
conf-cd {
|
||||
groups = "sdio1_cd_0_grp";
|
||||
bias-high-impedance;
|
||||
bias-pull-up;
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl_gpio_default: gpio-default {
|
||||
mux {
|
||||
function = "gpio0";
|
||||
groups = "gpio0_22_grp", "gpio0_23_grp";
|
||||
};
|
||||
|
||||
conf {
|
||||
groups = "gpio0_22_grp", "gpio0_23_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
|
||||
mux-msp {
|
||||
function = "gpio0";
|
||||
groups = "gpio0_13_grp", "gpio0_38_grp";
|
||||
};
|
||||
|
||||
conf-msp {
|
||||
groups = "gpio0_13_grp", "gpio0_38_grp";
|
||||
slew-rate = <SLEW_RATE_SLOW>;
|
||||
power-source = <IO_STANDARD_LVCMOS18>;
|
||||
};
|
||||
|
||||
conf-pull-up {
|
||||
pins = "MIO22";
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
conf-pull-none {
|
||||
pins = "MIO13", "MIO23", "MIO38";
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&psgtr {
|
||||
status = "okay";
|
||||
/* nc, sata, usb3, dp */
|
||||
clocks = <&si5341 0 3>, <&si5341 0 2>, <&si5341 0 0>;
|
||||
/* nc, dp, usb3, sata */
|
||||
clocks = <&si5341 0 0>, <&si5341 0 2>, <&si5341 0 3>;
|
||||
clock-names = "ref1", "ref2", "ref3";
|
||||
};
|
||||
|
||||
&qspi {
|
||||
status = "okay";
|
||||
flash@0 {
|
||||
compatible = "m25p80", "jedec,spi-nor"; /* 16MB + 16MB */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x0>;
|
||||
spi-tx-bus-width = <1>;
|
||||
spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
|
||||
spi-max-frequency = <108000000>; /* Based on DC1 spec */
|
||||
};
|
||||
};
|
||||
|
||||
&rtc {
|
||||
status = "okay";
|
||||
};
|
||||
@@ -565,24 +801,42 @@ &sata {
|
||||
ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
|
||||
ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
|
||||
phy-names = "sata-phy";
|
||||
phys = <&psgtr 3 PHY_TYPE_SATA 1 1>;
|
||||
phys = <&psgtr 3 PHY_TYPE_SATA 1 3>;
|
||||
};
|
||||
|
||||
/* SD1 with level shifter */
|
||||
&sdhci1 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_sdhci1_default>;
|
||||
disable-wp;
|
||||
/*
|
||||
* This property should be removed for supporting UHS mode
|
||||
*/
|
||||
no-1-8-v;
|
||||
xlnx,mio-bank = <1>;
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart0_default>;
|
||||
};
|
||||
|
||||
/* ULPI SMSC USB3320 */
|
||||
&usb0 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usb0_default>;
|
||||
phy-names = "usb3-phy";
|
||||
phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
|
||||
};
|
||||
|
||||
&dwc3_0 {
|
||||
status = "okay";
|
||||
dr_mode = "host";
|
||||
snps,usb3_lpm_capable;
|
||||
maximum-speed = "super-speed";
|
||||
};
|
||||
|
||||
&zynqmp_dpdma {
|
||||
|
||||
@@ -2,7 +2,7 @@
|
||||
/*
|
||||
* dts file for Xilinx ZynqMP
|
||||
*
|
||||
* (C) Copyright 2014 - 2019, Xilinx, Inc.
|
||||
* (C) Copyright 2014 - 2021, Xilinx, Inc.
|
||||
*
|
||||
* Michal Simek <michal.simek@xilinx.com>
|
||||
*
|
||||
@@ -156,21 +156,6 @@ zynqmp_power: zynqmp-power {
|
||||
mbox-names = "tx", "rx";
|
||||
};
|
||||
|
||||
zynqmp_clk: clock-controller {
|
||||
#clock-cells = <1>;
|
||||
compatible = "xlnx,zynqmp-clk";
|
||||
clocks = <&pss_ref_clk>,
|
||||
<&video_clk>,
|
||||
<&pss_alt_ref_clk>,
|
||||
<&aux_ref_clk>,
|
||||
<>_crx_ref_clk>;
|
||||
clock-names = "pss_ref_clk",
|
||||
"video_clk",
|
||||
"pss_alt_ref_clk",
|
||||
"aux_ref_clk",
|
||||
"gt_crx_ref_clk";
|
||||
};
|
||||
|
||||
nvmem_firmware {
|
||||
compatible = "xlnx,zynqmp-nvmem-fw";
|
||||
#address-cells = <1>;
|
||||
@@ -193,6 +178,11 @@ zynqmp_reset: reset-controller {
|
||||
compatible = "xlnx,zynqmp-reset";
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
pinctrl0: pinctrl {
|
||||
compatible = "xlnx,zynqmp-pinctrl";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@@ -245,6 +235,7 @@ can1: can@ff070000 {
|
||||
|
||||
cci: cci@fd6e0000 {
|
||||
compatible = "arm,cci-400";
|
||||
status = "disabled";
|
||||
reg = <0x0 0xfd6e0000 0x0 0x9000>;
|
||||
ranges = <0x0 0x0 0xfd6e0000 0x10000>;
|
||||
#address-cells = <1>;
|
||||
@@ -630,6 +621,8 @@ pcie: pcie@fd0e0000 {
|
||||
<0x0 0x0 0x0 0x2 &pcie_intc 0x2>,
|
||||
<0x0 0x0 0x0 0x3 &pcie_intc 0x3>,
|
||||
<0x0 0x0 0x0 0x4 &pcie_intc 0x4>;
|
||||
#stream-id-cells = <1>;
|
||||
iommus = <&smmu 0x4d0>;
|
||||
power-domains = <&zynqmp_firmware PD_PCIE>;
|
||||
pcie_intc: legacy-interrupt-controller {
|
||||
interrupt-controller;
|
||||
@@ -670,7 +663,7 @@ rtc: rtc@ffa60000 {
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 26 4>, <0 27 4>;
|
||||
interrupt-names = "alarm", "sec";
|
||||
calibration = <0x8000>;
|
||||
calibration = <0x7FFF>;
|
||||
};
|
||||
|
||||
sata: ahci@fd0c0000 {
|
||||
@@ -680,6 +673,7 @@ sata: ahci@fd0c0000 {
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 133 4>;
|
||||
power-domains = <&zynqmp_firmware PD_SATA>;
|
||||
resets = <&zynqmp_reset ZYNQMP_RESET_SATA>;
|
||||
#stream-id-cells = <4>;
|
||||
iommus = <&smmu 0x4c0>, <&smmu 0x4c1>,
|
||||
<&smmu 0x4c2>, <&smmu 0x4c3>;
|
||||
@@ -792,7 +786,7 @@ ttc3: timer@ff140000 {
|
||||
};
|
||||
|
||||
uart0: serial@ff000000 {
|
||||
compatible = "cdns,uart-r1p12", "xlnx,xuartps";
|
||||
compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12";
|
||||
status = "disabled";
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 21 4>;
|
||||
@@ -802,7 +796,7 @@ uart0: serial@ff000000 {
|
||||
};
|
||||
|
||||
uart1: serial@ff010000 {
|
||||
compatible = "cdns,uart-r1p12", "xlnx,xuartps";
|
||||
compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12";
|
||||
status = "disabled";
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 22 4>;
|
||||
@@ -811,24 +805,58 @@ uart1: serial@ff010000 {
|
||||
power-domains = <&zynqmp_firmware PD_UART_1>;
|
||||
};
|
||||
|
||||
usb0: usb@fe200000 {
|
||||
compatible = "snps,dwc3";
|
||||
usb0: usb@ff9d0000 {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
status = "disabled";
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 65 4>;
|
||||
reg = <0x0 0xfe200000 0x0 0x40000>;
|
||||
clock-names = "clk_xin", "clk_ahb";
|
||||
compatible = "xlnx,zynqmp-dwc3";
|
||||
reg = <0x0 0xff9d0000 0x0 0x100>;
|
||||
clock-names = "bus_clk", "ref_clk";
|
||||
power-domains = <&zynqmp_firmware PD_USB_0>;
|
||||
resets = <&zynqmp_reset ZYNQMP_RESET_USB0_CORERESET>,
|
||||
<&zynqmp_reset ZYNQMP_RESET_USB0_HIBERRESET>,
|
||||
<&zynqmp_reset ZYNQMP_RESET_USB0_APB>;
|
||||
reset-names = "usb_crst", "usb_hibrst", "usb_apbrst";
|
||||
ranges;
|
||||
|
||||
dwc3_0: usb@fe200000 {
|
||||
compatible = "snps,dwc3";
|
||||
reg = <0x0 0xfe200000 0x0 0x40000>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupt-names = "dwc_usb3", "otg";
|
||||
interrupts = <0 65 4>, <0 69 4>;
|
||||
#stream-id-cells = <1>;
|
||||
iommus = <&smmu 0x860>;
|
||||
snps,quirk-frame-length-adjustment = <0x20>;
|
||||
/* dma-coherent; */
|
||||
};
|
||||
};
|
||||
|
||||
usb1: usb@fe300000 {
|
||||
compatible = "snps,dwc3";
|
||||
usb1: usb@ff9e0000 {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
status = "disabled";
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 70 4>;
|
||||
reg = <0x0 0xfe300000 0x0 0x40000>;
|
||||
clock-names = "clk_xin", "clk_ahb";
|
||||
compatible = "xlnx,zynqmp-dwc3";
|
||||
reg = <0x0 0xff9e0000 0x0 0x100>;
|
||||
clock-names = "bus_clk", "ref_clk";
|
||||
power-domains = <&zynqmp_firmware PD_USB_1>;
|
||||
resets = <&zynqmp_reset ZYNQMP_RESET_USB1_CORERESET>,
|
||||
<&zynqmp_reset ZYNQMP_RESET_USB1_HIBERRESET>,
|
||||
<&zynqmp_reset ZYNQMP_RESET_USB1_APB>;
|
||||
reset-names = "usb_crst", "usb_hibrst", "usb_apbrst";
|
||||
ranges;
|
||||
|
||||
dwc3_1: usb@fe300000 {
|
||||
compatible = "snps,dwc3";
|
||||
reg = <0x0 0xfe300000 0x0 0x40000>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupt-names = "dwc_usb3", "otg";
|
||||
interrupts = <0 70 4>, <0 74 4>;
|
||||
#stream-id-cells = <1>;
|
||||
iommus = <&smmu 0x861>;
|
||||
snps,quirk-frame-length-adjustment = <0x20>;
|
||||
/* dma-coherent; */
|
||||
};
|
||||
};
|
||||
|
||||
watchdog0: watchdog@fd4d0000 {
|
||||
@@ -837,7 +865,8 @@ watchdog0: watchdog@fd4d0000 {
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <0 113 1>;
|
||||
reg = <0x0 0xfd4d0000 0x0 0x1000>;
|
||||
timeout-sec = <10>;
|
||||
timeout-sec = <60>;
|
||||
reset-on-timeout;
|
||||
};
|
||||
|
||||
lpd_watchdog: watchdog@ff150000 {
|
||||
|
||||
Reference in New Issue
Block a user