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Merge tag 'imx-dt64-6.13' of https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into soc/dt

Browse Source 
i.MX arm64 device tree changes for 6.13:

- New device support: Boundary Device Nitrogen8MP, Kontron OSM-S i.MX8MP
  SoM and BL carrier board, Verdin Ivy carrier board, DHCOM SoM on DRC02
  and PicoITX, Gateworks GW82XX-2X, etc.
- A series from Carlos Song to add LPSPI alias for i.MX8 and i.MX9 SoCs
- A couple of changes from Ciprian Marian Costea to improve S32G uSDHC
  and SD/eMMC support
- A couple of changes from Francesco Dolcini to improve SD regulator
  startup delay for Verdin devices
- A bunch of changes from Frank Li to add I3C overlay for imx93-9x9-qsb,
  enable PCIe and SATA for imx8qm-mek, add various devices for imx8qxp-mek,
  fix dt-schema warnings, etc.
- A series from João Paulo Gonçalves to improve i.MX8 Apalis and i.MX8M
  Verdin board support
- A set of changes from Laurentiu Mihalcea to enable dsp node for rproc
  usage in audio subsystem
- A set of changes from Peng Fan to improve i.MX95 support, adding SCMI,
  thermal zone, cooling device, idle states, etc.
- A series from Richard Zhu to add PCIe and SATA support for imx8dxl-evk
- A series from Shengjiu Wang to enable audio features on imx93-9x9-qsb
  and imx8ulp-evk board
- Other small and random changes

* tag 'imx-dt64-6.13' of https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (92 commits)
  arm64: dts: freescale: imx8mp-verdin: Fix SD regulator startup delay
  arm64: dts: freescale: imx8mm-verdin: Fix SD regulator startup delay
  arm64: dts: imx8mp-verdin: add single-master property to all i2c nodes
  arm64: dts: imx8mm-verdin: add single-master property to all i2c nodes
  arm64: dts: imx95: Add missing vendor string to SCMI property
  arm64: dts: imx8mp-navqp: Add HDMI support
  arm64: dts: imx8qm-ss-hsio: fix PCI and SATA clock indices
  arm64: dts: imx8qm-ss-hsio: fix interrupt-map indent under pci* nodes
  arm64: dts: imx8qxp-mek: replace hardcode 0 with IMX_LPCG_CLK_0
  arm64: dts: imx8mn-tqma8mqnl-mba8mx-usbot: fix coexistence of output-low and output-high in GPIO
  arm64: dts: layerscape: remove en25s64 and only keep jedec,spi-nor compatible string
  arm64: dts: imx8mp-kontron-dl: change touchscreen power-supply to AVDD28-supply
  arm64: dts: imx8mp: Add Boundary Device Nitrogen8MP Universal SMARC Carrier Board
  arm64: dts: imx8: move samsung,burst-clock-frequency to imx8mn and imx8mm mba8mx board file
  arm64: dts: mba8mx: remove undocumented 'data-lanes' at panel
  arm64: dts: imx: Add i.MX8M Plus Gateworks GW82XX-2X support
  arm64: dts: imx8ulp-evk: Add spdif sound card support
  arm64: dts: imx8ulp-evk: Add bt-sco sound card support
  arm64: dts: imx8ulp: Add audio device nodes
  arm64: dts: imx8qm-mek: enable dsp node for rproc usage
  ...

Link: https://lore.kernel.org/r/20241104090055.1881860-5-shawnguo2@yeah.net
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
2024-11-12 22:39:16 +01:00
parent 430851a9de 6c5789c9d2
commit cdc9f8bdf7
90 changed files with 8095 additions and 109 deletions
Download Patch File Download Diff File Expand all files Collapse all files

25
arch/arm64/boot/dts/freescale/Makefile
View File

@@ -136,10 +136,12 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw7903.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw7904.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-nonwifi-dahlia.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-nonwifi-dev.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-nonwifi-ivy.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-nonwifi-mallow.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-nonwifi-yavia.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-dahlia.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-dev.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-ivy.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-mallow.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-yavia.dtb
@@ -167,12 +169,22 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-beacon-kit.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-data-modul-edm-sbc.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-debix-model-a.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-debix-som-a-bmb-08.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-dhcom-drc02.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-dhcom-pdk2.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-dhcom-pdk3.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-dhcom-picoitx.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-icore-mx8mp-edimm2.2.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-iota2-lumpy.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-kontron-bl-osm-s.dtb
imx8mp-kontron-dl-dtbs += imx8mp-kontron-bl-osm-s.dtb imx8mp-kontron-dl.dtbo
dtb-$(CONFIG_ARCH_MXC) += imx8mp-kontron-dl.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-kontron-smarc-eval-carrier.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-msc-sm2s-ep1.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-navqp.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-nitrogen-smarc-universal-board.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-rdk.dtb
imx8mp-phyboard-pollux-rdk-no-eth-dtbs += imx8mp-phyboard-pollux-rdk.dtb imx8mp-phycore-no-eth.dtbo
dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-rdk-no-eth.dtb
@@ -187,17 +199,22 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-gw72xx-2x.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-gw73xx-2x.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-gw74xx.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-gw75xx-2x.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-gw82xx-2x.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-nonwifi-dahlia.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-nonwifi-dev.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-nonwifi-ivy.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-nonwifi-mallow.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-nonwifi-yavia.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-wifi-dahlia.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-wifi-dev.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-wifi-ivy.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-wifi-mallow.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-wifi-yavia.dtb
imx8mp-evk-mx8-dlvds-lcd1-dtbs += imx8mp-evk.dtb imx8mp-evk-mx8-dlvds-lcd1.dtbo
imx8mp-evk-pcie-ep-dtbs += imx8mp-evk.dtb imx8mp-evk-pcie-ep.dtbo
dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk-mx8-dlvds-lcd1.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk-pcie-ep.dtb
imx8mp-tqma8mpql-mba8mpxl-lvds-dtbs += imx8mp-tqma8mpql-mba8mpxl.dtb imx8mp-tqma8mpql-mba8mpxl-lvds.dtbo
imx8mp-tqma8mpql-mba8mpxl-lvds-g133han01-dtbs += imx8mp-tqma8mpql-mba8mpxl.dtb imx8mp-tqma8mpql-mba8mpxl-lvds-g133han01.dtbo
@@ -240,6 +257,10 @@ dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8qxp-tqma8xqp-mba8xx.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8ulp-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx93-9x9-qsb.dtb
imx93-9x9-qsb-i3c-dtbs += imx93-9x9-qsb.dtb imx93-9x9-qsb-i3c.dtbo
dtb-$(CONFIG_ARCH_MXC) += imx93-9x9-qsb-i3c.dtb
dtb-$(CONFIG_ARCH_MXC) += imx93-11x11-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx93-14x14-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx93-kontron-bl-osm-s.dtb
@@ -249,6 +270,10 @@ dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba93xxla.dtb
dtb-$(CONFIG_ARCH_MXC) += imx93-var-som-symphony.dtb
dtb-$(CONFIG_ARCH_MXC) += imx95-19x19-evk.dtb
imx8mm-kontron-dl-dtbs := imx8mm-kontron-bl.dtb imx8mm-kontron-dl.dtbo
dtb-$(CONFIG_ARCH_MXC) += imx8mm-kontron-dl.dtb
imx8mm-venice-gw72xx-0x-imx219-dtbs := imx8mm-venice-gw72xx-0x.dtb imx8mm-venice-gw72xx-0x-imx219.dtbo
imx8mm-venice-gw72xx-0x-rpidsi-dtbs := imx8mm-venice-gw72xx-0x.dtb imx8mm-venice-gw72xx-0x-rpidsi.dtbo
imx8mm-venice-gw72xx-0x-rs232-rts-dtbs := imx8mm-venice-gw72xx-0x.dtb imx8mm-venice-gw72xx-0x-rs232-rts.dtbo

2
arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts
View File

@@ -87,7 +87,7 @@ flash@1 {
flash@2 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "en25s64", "jedec,spi-nor";
compatible = "jedec,spi-nor";
spi-cpol;
spi-cpha;
reg = <2>;

2
arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var3-ads2.dts
View File

@@ -19,8 +19,6 @@ / {
pwm-fan {
compatible = "pwm-fan";
cooling-min-state = <0>;
cooling-max-state = <3>;
#cooling-cells = <2>;
pwms = <&sl28cpld_pwm0 0 4000000>;
cooling-levels = <1 128 192 255>;

2
arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts
View File

@@ -69,7 +69,7 @@ flash@1 {
flash@2 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "en25s64", "jedec,spi-nor";
compatible = "jedec,spi-nor";
spi-cpol;
spi-cpha;
reg = <2>;

3
arch/arm64/boot/dts/freescale/fsl-lx2160a-cex7.dtsi
View File

@@ -94,9 +94,6 @@ i2c@1 {
fan-temperature-ctrlr@18 {
compatible = "ti,amc6821";
reg = <0x18>;
cooling-min-state = <0>;
cooling-max-state = <9>;
#cooling-cells = <2>;
};
};

169
arch/arm64/boot/dts/freescale/fsl-lx2160a-rev2.dtsi Normal file
View File

@@ -0,0 +1,169 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
//
// Device Tree file for LX2160 REV2
//
// Copyright 2025 NXP
/dts-v1/;
#include "fsl-lx2160a.dtsi"
&pcie1 {
compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie";
reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
0x80 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "regs", "config";
ranges = <0x81000000 0x0 0x00000000 0x80 0x00010000 0x0 0x00010000
0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>;
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "intr";
/delete-property/ apio-wins;
/delete-property/ ppio-wins;
};
&pcie2 {
compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie";
reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
0x88 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "regs", "config";
ranges = <0x81000000 0x0 0x00000000 0x88 0x00010000 0x0 0x00010000
0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>;
interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "intr";
/delete-property/ apio-wins;
/delete-property/ ppio-wins;
};
&pcie3 {
compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie";
reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
0x90 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "regs", "config";
ranges = <0x81000000 0x0 0x00000000 0x90 0x00010000 0x0 0x00010000
0x82000000 0x0 0x40000000 0x90 0x40000000 0x0 0x40000000>;
interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "intr";
/delete-property/ apio-wins;
/delete-property/ ppio-wins;
};
&pcie4 {
compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie";
reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */
0x98 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "regs", "config";
ranges = <0x81000000 0x0 0x00000000 0x98 0x00010000 0x0 0x00010000
0x82000000 0x0 0x40000000 0x98 0x40000000 0x0 0x40000000>;
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "intr";
/delete-property/ apio-wins;
/delete-property/ ppio-wins;
};
&pcie5 {
compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie";
reg = <0x00 0x03800000 0x0 0x00100000 /* controller registers */
0xa0 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "regs", "config";
ranges = <0x81000000 0x0 0x00000000 0xa0 0x00010000 0x0 0x00010000
0x82000000 0x0 0x40000000 0xa0 0x40000000 0x0 0x40000000>;
interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "intr";
/delete-property/ apio-wins;
/delete-property/ ppio-wins;
};
&pcie6 {
compatible = "fsl,lx2160ar2-pcie", "fsl,ls2088a-pcie";
reg = <0x00 0x03900000 0x0 0x00100000 /* controller registers */
0xa8 0x00000000 0x0 0x00002000>; /* configuration space */
reg-names = "regs", "config";
ranges = <0x81000000 0x0 0x00000000 0xa8 0x00010000 0x0 0x00010000
0x82000000 0x0 0x40000000 0xa8 0x40000000 0x0 0x40000000>;
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "intr";
/delete-property/ apio-wins;
/delete-property/ ppio-wins;
};
&soc {
pcie_ep1: pcie-ep@3400000 {
compatible = "fsl,lx2160ar2-pcie-ep";
reg = <0x00 0x03400000 0x0 0x00100000
0x80 0x00000000 0x8 0x00000000>;
reg-names = "regs", "addr_space";
num-ob-windows = <8>;
num-ib-windows = <8>;
status = "disabled";
};
pcie_ep2: pcie-ep@3500000 {
compatible = "fsl,lx2160ar2-pcie-ep";
reg = <0x00 0x03500000 0x0 0x00100000
0x88 0x00000000 0x8 0x00000000>;
reg-names = "regs", "addr_space";
num-ob-windows = <8>;
num-ib-windows = <8>;
status = "disabled";
};
pcie_ep3: pcie-ep@3600000 {
compatible = "fsl,lx2160ar2-pcie-ep";
reg = <0x00 0x03600000 0x0 0x00100000
0x90 0x00000000 0x8 0x00000000>;
reg-names = "regs", "addr_space";
num-ob-windows = <256>;
num-ib-windows = <24>;
status = "disabled";
};
pcie_ep4: pcie-ep@3700000 {
compatible = "fsl,lx2160ar2-pcie-ep";
reg = <0x00 0x03700000 0x0 0x00100000
0x98 0x00000000 0x8 0x00000000>;
reg-names = "regs", "addr_space";
num-ob-windows = <8>;
num-ib-windows = <8>;
status = "disabled";
};
pcie_ep5: pcie-ep@3800000 {
compatible = "fsl,lx2160ar2-pcie-ep";
reg = <0x00 0x03800000 0x0 0x00100000
0xa0 0x00000000 0x8 0x00000000>;
reg-names = "regs", "addr_space";
num-ob-windows = <256>;
num-ib-windows = <24>;
status = "disabled";
};
pcie_ep6: pcie-ep@3900000 {
compatible = "fsl,lx2160ar2-pcie-ep";
reg = <0x00 0x03900000 0x0 0x00100000
0xa8 0x00000000 0x8 0x00000000>;
reg-names = "regs", "addr_space";
num-ob-windows = <8>;
num-ib-windows = <8>;
status = "disabled";
};
};

2
arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
View File

@@ -614,7 +614,7 @@ cluster2-3-crit {
};
};
soc {
soc: soc {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;

69
arch/arm64/boot/dts/freescale/imx8-apalis-eval-v1.2.dtsi
View File

@@ -51,6 +51,40 @@ reg_can2: regulator-can2 {
regulator-name = "5V_SW_CAN2";
startup-delay-us = <10000>;
};
sound-carrier {
compatible = "simple-audio-card";
simple-audio-card,bitclock-master = <&codec_dai>;
simple-audio-card,format = "i2s";
simple-audio-card,frame-master = <&codec_dai>;
simple-audio-card,name = "apalis-nau8822";
simple-audio-card,routing =
"Headphones", "LHP",
"Headphones", "RHP",
"Speaker", "LSPK",
"Speaker", "RSPK",
"Line Out", "AUXOUT1",
"Line Out", "AUXOUT2",
"LAUX", "Line In",
"RAUX", "Line In",
"LMICP", "Mic In",
"RMICP", "Mic In";
simple-audio-card,widgets =
"Headphones", "Headphones",
"Line Out", "Line Out",
"Speaker", "Speaker",
"Microphone", "Mic In",
"Line", "Line In";
codec_dai: simple-audio-card,codec {
sound-dai = <&nau8822_1a>;
system-clock-frequency = <12288000>;
};
simple-audio-card,cpu {
sound-dai = <&sai0>;
};
};
};
/* Apalis CAN1 */
@@ -69,6 +103,13 @@ &flexcan2 {
&i2c2 {
status = "okay";
/* Audio Codec */
nau8822_1a: audio-codec@1a {
compatible = "nuvoton,nau8822";
reg = <0x1a>;
#sound-dai-cells = <0>;
};
/* Power/Current Measurement Sensor */
hwmon@40 {
compatible = "ti,ina219";
@@ -87,6 +128,18 @@ eeprom@57 {
};
};
&sai0 {
assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>,
<&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>,
<&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>,
<&sai0_lpcg IMX_LPCG_CLK_0>;
assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai0>;
#sound-dai-cells = <0>;
status = "okay";
};
/* Apalis MMC1 */
&usdhc2 {
pinctrl-0 = <&pinctrl_usdhc2_4bit>, <&pinctrl_mmc1_cd>;
@@ -105,6 +158,15 @@ &usdhc3 {
};
&iomuxc {
pinctrl-0 = <&pinctrl_cam1_gpios>,
<&pinctrl_esai0_gpios>, <&pinctrl_fec2_gpios>,
<&pinctrl_gpio3>, <&pinctrl_gpio4>, <&pinctrl_gpio_keys>,
<&pinctrl_gpio_usbh_oc_n>, <&pinctrl_lpuart1ctrl>,
<&pinctrl_lvds0_i2c0_gpio>, <&pinctrl_lvds1_i2c0_gpios>,
<&pinctrl_mipi_dsi_0_1_en>, <&pinctrl_mipi_dsi1_gpios>,
<&pinctrl_mlb_gpios>, <&pinctrl_qspi1a_gpios>,
<&pinctrl_sata1_act>, <&pinctrl_sim0_gpios>,
<&pinctrl_usdhc1_gpios>;
pinctrl_enable_3v3_mmc: enable3v3mmcgrp {
fsl,pins = <IMX8QM_USDHC1_DATA4_LSIO_GPIO5_IO19 0x00000021>; /* MXM3_148 */
@@ -121,4 +183,11 @@ pinctrl_enable_can1_power: enablecan1powergrp {
pinctrl_enable_can2_power: enablecan2powergrp {
fsl,pins = <IMX8QM_USDHC1_DATA6_LSIO_GPIO5_IO21 0x00000021>; /* MXM3_156 */
};
pinctrl_sai0: sai0grp {
fsl,pins = <IMX8QM_SAI1_RXC_AUD_SAI0_TXD 0xc600006c>, /* MXM3_196 */
<IMX8QM_SPI0_CS1_AUD_SAI0_TXC 0xc600004c>, /* MXM3_200 */
<IMX8QM_SAI1_RXFS_AUD_SAI0_RXD 0xc600004c>, /* MXM3_202 */
<IMX8QM_SPI2_CS1_AUD_SAI0_TXFS 0xc600004c>; /* MXM3_204 */
};
};

31
arch/arm64/boot/dts/freescale/imx8-apalis-eval.dtsi
View File

@@ -22,9 +22,13 @@ &adc1 {
status = "okay";
};
/* TODO: Audio Mixer */
&amix {
status = "okay";
};
/* TODO: Asynchronous Sample Rate Converter (ASRC) */
&asrc0 {
status = "okay";
};
/* TODO: Display Controller */
@@ -104,13 +108,25 @@ &lsio_pwm3 {
/* TODO: Apalis BKL1_PWM */
/* TODO: Apalis DAP1 */
/* Apalis DAP1 */
&sai1 {
status = "okay";
};
/* TODO: Apalis Analogue Audio */
&sai5 {
status = "okay";
};
&sai5_lpcg {
status = "okay";
};
/* TODO: Apalis SATA1 */
/* TODO: Apalis SPDIF1 */
/* Apalis SPDIF1 */
&spdif0 {
status = "okay";
};
/* TODO: Apalis USBH2, Apalis USBH3 and on-module Wi-Fi via on-module HSIC Hub */
@@ -119,4 +135,7 @@ &usbotg1 {
status = "okay";
};
/* TODO: Apalis USBH4 SuperSpeed */
/* Apalis USBH4 SuperSpeed */
&usbotg3_cdns3 {
status = "okay";
};

31
arch/arm64/boot/dts/freescale/imx8-apalis-ixora-v1.1.dtsi
View File

@@ -62,9 +62,13 @@ &adc1 {
status = "okay";
};
/* TODO: Audio Mixer */
&amix {
status = "okay";
};
/* TODO: Asynchronous Sample Rate Converter (ASRC) */
&asrc0 {
status = "okay";
};
/* TODO: Display Controller */
@@ -191,13 +195,25 @@ &lsio_pwm3 {
/* TODO: Apalis BKL1_PWM */
/* TODO: Apalis DAP1 */
/* Apalis DAP1 */
&sai1 {
status = "okay";
};
/* TODO: Apalis Analogue Audio */
&sai5 {
status = "okay";
};
&sai5_lpcg {
status = "okay";
};
/* TODO: Apalis SATA1 */
/* TODO: Apalis SPDIF1 */
/* Apalis SPDIF1 */
&spdif0 {
status = "okay";
};
/* TODO: Apalis USBH2, Apalis USBH3 and on-module Wi-Fi via on-module HSIC Hub */
@@ -206,7 +222,10 @@ &usbotg1 {
status = "okay";
};
/* TODO: Apalis USBH4 SuperSpeed */
/* Apalis USBH4 SuperSpeed */
&usbotg3_cdns3 {
status = "okay";
};
/* Apalis MMC1 */
&usdhc2 {

31
arch/arm64/boot/dts/freescale/imx8-apalis-ixora-v1.2.dtsi
View File

@@ -94,9 +94,13 @@ &adc1 {
status = "okay";
};
/* TODO: Audio Mixer */
&amix {
status = "okay";
};
/* TODO: Asynchronous Sample Rate Converter (ASRC) */
&asrc0 {
status = "okay";
};
/* TODO: Display Controller */
@@ -240,13 +244,25 @@ &lsio_pwm3 {
/* TODO: Apalis BKL1_PWM */
/* TODO: Apalis DAP1 */
/* Apalis DAP1 */
&sai1 {
status = "okay";
};
/* TODO: Apalis Analogue Audio */
&sai5 {
status = "okay";
};
&sai5_lpcg {
status = "okay";
};
/* TODO: Apalis SATA1 */
/* TODO: Apalis SPDIF1 */
/* Apalis SPDIF1 */
&spdif0 {
status = "okay";
};
/* TODO: Apalis USBH2, Apalis USBH3 and on-module Wi-Fi via on-module HSIC Hub */
@@ -255,7 +271,10 @@ &usbotg1 {
status = "okay";
};
/* TODO: Apalis USBH4 SuperSpeed */
/* Apalis USBH4 SuperSpeed */
&usbotg3_cdns3 {
status = "okay";
};
/* Apalis MMC1 */
&usdhc2 {

135
arch/arm64/boot/dts/freescale/imx8-apalis-v1.1.dtsi
View File

@@ -126,6 +126,13 @@ reg_usb_phy: regulator-usb-hsic1 {
regulator-name = "usb-phy-dummy";
};
reg_vref_1v8: regulator-vref-1v8 {
compatible = "regulator-fixed";
regulator-name = "+V1.8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
@@ -198,11 +205,32 @@ linux,cma {
};
};
/* TODO: Apalis Analogue Audio */
sound {
compatible = "simple-audio-card";
simple-audio-card,bitclock-master = <&dailink_master>;
simple-audio-card,format = "i2s";
simple-audio-card,frame-master = <&dailink_master>;
simple-audio-card,name = "apalis-imx8qm";
simple-audio-card,cpu {
sound-dai = <&sai1>;
};
dailink_master: simple-audio-card,codec {
sound-dai = <&sgtl5000>;
};
};
/* TODO: HDMI Audio */
/* TODO: Apalis SPDIF1 */
/* Apalis SPDIF1 */
sound-spdif {
compatible = "fsl,imx-audio-spdif";
model = "imx-spdif";
spdif-controller = <&spdif0>;
spdif-in;
spdif-out;
};
touchscreen: touchscreen {
compatible = "toradex,vf50-touchscreen";
@@ -227,6 +255,10 @@ touchscreen: touchscreen {
};
&asrc0 {
fsl,asrc-rate = <48000>;
};
&adc0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_adc0>;
@@ -239,6 +271,30 @@ &adc1 {
/* TODO: Asynchronous Sample Rate Converter (ASRC) */
&cpu_alert0 {
temperature = <95000>;
};
&cpu_alert1 {
temperature = <95000>;
};
&cpu_crit0 {
temperature = <105000>;
};
&cpu_crit1 {
temperature = <105000>;
};
&drc_alert0 {
temperature = <95000>;
};
&drc_crit0 {
temperature = <105000>;
};
/* Apalis ETH1 */
&fec1 {
pinctrl-names = "default", "sleep";
@@ -285,6 +341,22 @@ &flexcan3 {
/* TODO: Apalis HDMI1 */
&gpu_alert0 {
temperature = <95000>;
};
&gpu_alert1 {
temperature = <95000>;
};
&gpu_crit0 {
temperature = <105000>;
};
&gpu_crit1 {
temperature = <105000>;
};
/* On-module I2C */
&i2c1 {
pinctrl-names = "default";
@@ -294,8 +366,6 @@ &i2c1 {
clock-frequency = <100000>;
status = "okay";
/* TODO: Audio Codec */
/* USB3503A */
usb-hub@8 {
compatible = "smsc,usb3503a";
@@ -308,6 +378,24 @@ usb-hub@8 {
refclk-frequency = <25000000>;
reset-gpios = <&lsio_gpio1 2 GPIO_ACTIVE_LOW>;
};
/* On Module Audio Codec */
sgtl5000: audio-codec@a {
compatible = "fsl,sgtl5000";
reg = <0x0a>;
assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>,
<&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>,
<&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>,
<&mclkout0_lpcg IMX_LPCG_CLK_0>;
assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>;
clocks = <&mclkout0_lpcg IMX_LPCG_CLK_0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sgtl5000>;
#sound-dai-cells = <0>;
VDDA-supply = <&reg_module_3v3_avdd>;
VDDD-supply = <&reg_vref_1v8>;
VDDIO-supply = <&reg_module_3v3>;
};
};
/* Apalis I2C1 */
@@ -689,19 +777,48 @@ &mu2_m0 {
/* TODO: Apalis BKL1_PWM */
/* TODO: Apalis DAP1 */
/* TODO: Analogue Audio */
/* Apalis DAP1 */
&sai1 {
assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>,
<&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>,
<&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>,
<&sai1_lpcg IMX_LPCG_CLK_0>;
assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai1>;
#sound-dai-cells = <0>;
status = "okay";
};
/* TODO: Apalis SATA1 */
/* TODO: Apalis SPDIF1 */
/* Apalis SPDIF1 */
&spdif0 {
assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>,
<&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>,
<&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>;
assigned-clock-rates = <786432000>, <49152000>, <12288000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spdif0>;
status = "okay";
};
/* TODO: Thermal Zones */
/* TODO: Apalis USBH2, Apalis USBH3 and on-module Wi-Fi via on-module HSIC Hub */
/* TODO: Apalis USBH4 */
/* Apalis USBH4 */
&usb3_phy {
status = "okay";
};
&usbotg3 {
status = "okay";
};
&usbotg3_cdns3 {
dr_mode = "host";
};
/* Apalis USBO1 */
&usbphy1 {

19
arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi
View File

@@ -431,22 +431,19 @@ dsp_ram_lpcg: clock-controller@59590000 {
};
dsp: dsp@596e8000 {
compatible = "fsl,imx8qxp-dsp";
compatible = "fsl,imx8qxp-hifi4";
reg = <0x596e8000 0x88000>;
clocks = <&dsp_lpcg IMX_LPCG_CLK_5>,
<&dsp_ram_lpcg IMX_LPCG_CLK_4>,
<&dsp_lpcg IMX_LPCG_CLK_7>;
clock-names = "ipg", "ocram", "core";
power-domains = <&pd IMX_SC_R_MU_13A>,
<&pd IMX_SC_R_MU_13B>,
<&pd IMX_SC_R_DSP>,
<&pd IMX_SC_R_DSP_RAM>;
mbox-names = "txdb0", "txdb1",
"rxdb0", "rxdb1";
mboxes = <&lsio_mu13 2 0>,
<&lsio_mu13 2 1>,
<&lsio_mu13 3 0>,
<&lsio_mu13 3 1>;
power-domains = <&pd IMX_SC_R_MU_13B>,
<&pd IMX_SC_R_MU_2A>;
mbox-names = "tx", "rx", "rxdb";
mboxes = <&lsio_mu13 0 0>,
<&lsio_mu13 1 0>,
<&lsio_mu13 3 0>;
firmware-name = "imx/dsp/hifi4.bin";
status = "disabled";
};

2
arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi
View File

@@ -350,7 +350,7 @@ dma_apbh: dma-controller@5b810000 {
power-domains = <&pd IMX_SC_R_NAND>;
};
gpmi: nand-controller@5b812000{
gpmi: nand-controller@5b812000 {
compatible = "fsl,imx8qxp-gpmi-nand";
reg = <0x5b812000 0x2000>, <0x5b814000 0x2000>;
reg-names = "gpmi-nand", "bch";

123
arch/arm64/boot/dts/freescale/imx8-ss-hsio.dtsi Normal file
View File

@@ -0,0 +1,123 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2024 NXP
*
* Richard Zhu <hongxing.zhu@nxp.com>
*/
#include <dt-bindings/phy/phy.h>
hsio_axi_clk: clock-hsio-axi {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <400000000>;
clock-output-names = "hsio_axi_clk";
};
hsio_per_clk: clock-hsio-per {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <133333333>;
clock-output-names = "hsio_per_clk";
};
hsio_refa_clk: clock-hsio-refa {
compatible = "gpio-gate-clock";
clocks = <&xtal100m>;
#clock-cells = <0>;
enable-gpios = <&lsio_gpio4 27 GPIO_ACTIVE_LOW>;
};
hsio_refb_clk: clock-hsio-refb {
compatible = "gpio-gate-clock";
clocks = <&xtal100m>;
#clock-cells = <0>;
enable-gpios = <&lsio_gpio4 1 GPIO_ACTIVE_LOW>;
};
xtal100m: clock-xtal100m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
clock-output-names = "xtal_100MHz";
};
hsio_subsys: bus@5f000000 {
compatible = "simple-bus";
ranges = <0x5f000000 0x0 0x5f000000 0x01000000>,
<0x80000000 0x0 0x70000000 0x10000000>;
#address-cells = <1>;
#size-cells = <1>;
dma-ranges = <0x80000000 0 0x80000000 0x80000000>;
pcieb: pcie@5f010000 {
compatible = "fsl,imx8q-pcie";
reg = <0x5f010000 0x10000>,
<0x8ff00000 0x80000>;
reg-names = "dbi", "config";
ranges = <0x81000000 0 0x00000000 0x8ff80000 0 0x00010000>,
<0x82000000 0 0x80000000 0x80000000 0 0x0ff00000>;
#interrupt-cells = <1>;
interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi";
#address-cells = <3>;
#size-cells = <2>;
clocks = <&pcieb_lpcg IMX_LPCG_CLK_6>,
<&pcieb_lpcg IMX_LPCG_CLK_4>,
<&pcieb_lpcg IMX_LPCG_CLK_5>;
clock-names = "dbi", "mstr", "slv";
bus-range = <0x00 0xff>;
device_type = "pci";
interrupt-map = <0 0 0 1 &gic 0 105 4>,
<0 0 0 2 &gic 0 106 4>,
<0 0 0 3 &gic 0 107 4>,
<0 0 0 4 &gic 0 108 4>;
interrupt-map-mask = <0 0 0 0x7>;
num-lanes = <1>;
num-viewport = <4>;
power-domains = <&pd IMX_SC_R_PCIE_B>;
fsl,max-link-speed = <3>;
status = "disabled";
};
pcieb_lpcg: clock-controller@5f060000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x5f060000 0x10000>;
clocks = <&hsio_axi_clk>, <&hsio_axi_clk>, <&hsio_axi_clk>;
#clock-cells = <1>;
clock-indices = <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>, <IMX_LPCG_CLK_6>;
clock-output-names = "hsio_pcieb_mstr_axi_clk",
"hsio_pcieb_slv_axi_clk",
"hsio_pcieb_dbi_axi_clk";
power-domains = <&pd IMX_SC_R_PCIE_B>;
};
phyx1_crr1_lpcg: clock-controller@5f0b0000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x5f0b0000 0x10000>;
clocks = <&hsio_per_clk>;
#clock-cells = <1>;
clock-indices = <IMX_LPCG_CLK_4>;
clock-output-names = "hsio_phyx1_per_clk";
power-domains = <&pd IMX_SC_R_SERDES_1>;
};
pcieb_crr3_lpcg: clock-controller@5f0d0000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x5f0d0000 0x10000>;
clocks = <&hsio_per_clk>;
#clock-cells = <1>;
clock-indices = <IMX_LPCG_CLK_4>;
clock-output-names = "hsio_pcieb_per_clk";
power-domains = <&pd IMX_SC_R_PCIE_B>;
};
misc_crr5_lpcg: clock-controller@5f0f0000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x5f0f0000 0x10000>;
clocks = <&hsio_per_clk>;
#clock-cells = <1>;
clock-indices = <IMX_LPCG_CLK_4>;
clock-output-names = "hsio_misc_per_clk";
power-domains = <&pd IMX_SC_R_HSIO_GPIO>;
};
};

33
arch/arm64/boot/dts/freescale/imx8dxl-evk.dts
View File

@@ -182,6 +182,15 @@ mii_select: regulator-4 {
regulator-always-on;
};
reg_pcieb: regulator-pcieb {
compatible = "regulator-fixed";
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3300000>;
regulator-name = "reg_pcieb";
gpio = <&pca6416_1 13 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
bt_sco_codec: audio-codec-bt {
compatible = "linux,bt-sco";
#sound-dai-cells = <1>;
@@ -567,6 +576,12 @@ &flexcan3 {
status = "okay";
};
&hsio_phy {
fsl,hsio-cfg = "pciea-x2-pcieb";
fsl,refclk-pad-mode = "output";
status = "okay";
};
&cm40_intmux {
status = "disabled";
};
@@ -585,6 +600,16 @@ &lsio_gpio5 {
status = "okay";
};
&pcieb {
phys = <&hsio_phy 0 PHY_TYPE_PCIE 0>;
phy-names = "pcie-phy";
pinctrl-0 = <&pinctrl_pcieb>;
pinctrl-names = "default";
reset-gpio = <&lsio_gpio4 0 GPIO_ACTIVE_LOW>;
vpcie-supply = <&reg_pcieb>;
status = "okay";
};
&sai0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai0>;
@@ -868,6 +893,14 @@ IMX8DXL_UART1_CTS_B_ADMA_UART1_CTS_B 0x06000020
>;
};
pinctrl_pcieb: pcieagrp {
fsl,pins = <
IMX8DXL_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00 0x06000021
IMX8DXL_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01 0x06000021
IMX8DXL_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02 0x04000021
>;
};
pinctrl_sai0: sai0grp {
fsl,pins = <
IMX8DXL_SPI0_CS0_ADMA_SAI0_RXD 0x06000060

4
arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi
View File

@@ -138,6 +138,10 @@ &gpmi {
interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
};
&usbphy1 {
compatible = "fsl,imx8dxl-usbphy", "fsl,imx7ulp-usbphy";
};
&usdhc1 {
compatible = "fsl,imx8dxl-usdhc", "fsl,imx8qxp-usdhc";
interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;

51
arch/arm64/boot/dts/freescale/imx8dxl-ss-hsio.dtsi Normal file
View File

@@ -0,0 +1,51 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2024 NXP
*/
&hsio_subsys {
phyx1_lpcg: clock-controller@5f090000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x5f090000 0x10000>;
clocks = <&hsio_refb_clk>, <&hsio_per_clk>,
<&hsio_per_clk>, <&hsio_per_clk>;
#clock-cells = <1>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
<IMX_LPCG_CLK_2>, <IMX_LPCG_CLK_4>;
clock-output-names = "hsio_phyx1_pclk",
"hsio_phyx1_epcs_tx_clk",
"hsio_phyx1_epcs_rx_clk",
"hsio_phyx1_apb_clk";
power-domains = <&pd IMX_SC_R_SERDES_1>;
};
hsio_phy: phy@5f1a0000 {
compatible = "fsl,imx8qxp-hsio";
reg = <0x5f1a0000 0x10000>,
<0x5f120000 0x10000>,
<0x5f140000 0x10000>,
<0x5f160000 0x10000>;
reg-names = "reg", "phy", "ctrl", "misc";
clocks = <&phyx1_lpcg IMX_LPCG_CLK_0>,
<&phyx1_lpcg IMX_LPCG_CLK_4>,
<&phyx1_crr1_lpcg IMX_LPCG_CLK_4>,
<&pcieb_crr3_lpcg IMX_LPCG_CLK_4>,
<&misc_crr5_lpcg IMX_LPCG_CLK_4>;
clock-names = "pclk0", "apb_pclk0", "phy0_crr", "ctl0_crr",
"misc_crr";
#phy-cells = <3>;
power-domains = <&pd IMX_SC_R_SERDES_1>;
status = "disabled";
};
};
&pcieb {
#interrupt-cells = <1>;
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi";
interrupt-map = <0 0 0 1 &gic 0 47 4>,
<0 0 0 2 &gic 0 48 4>,
<0 0 0 3 &gic 0 49 4>,
<0 0 0 4 &gic 0 50 4>;
interrupt-map-mask = <0 0 0 0x7>;
};

6
arch/arm64/boot/dts/freescale/imx8dxl.dtsi
View File

@@ -30,6 +30,10 @@ aliases {
gpio6 = &lsio_gpio6;
gpio7 = &lsio_gpio7;
mu1 = &lsio_mu1;
spi0 = &lpspi0;
spi1 = &lpspi1;
spi2 = &lpspi2;
spi3 = &lpspi3;
};
cpus: cpus {
@@ -237,12 +241,14 @@ xtal24m: clock-xtal24m {
#include "imx8-ss-conn.dtsi"
#include "imx8-ss-ddr.dtsi"
#include "imx8-ss-lsio.dtsi"
#include "imx8-ss-hsio.dtsi"
};
#include "imx8dxl-ss-adma.dtsi"
#include "imx8dxl-ss-conn.dtsi"
#include "imx8dxl-ss-lsio.dtsi"
#include "imx8dxl-ss-ddr.dtsi"
#include "imx8dxl-ss-hsio.dtsi"
&cm40_intmux {
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,

335
arch/arm64/boot/dts/freescale/imx8mm-emtop-baseboard.dts
View File

@@ -1,6 +1,9 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2023 Emtop Embedded Solutions
*
* Author: Himanshu Bhavani <himanshu.bhavani@siliconsignals.io>
* Author: Tarang Raval <tarang.raval@siliconsignals.io>
*/
/dts-v1/;
@@ -11,6 +14,113 @@ / {
model = "Emtop Embedded Solutions i.MX8M Mini Baseboard V1";
compatible = "ees,imx8mm-emtop-baseboard", "ees,imx8mm-emtop-som",
"fsl,imx8mm";
connector {
compatible = "usb-c-connector";
label = "USB-C";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb_otg>;
id-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
port {
high_speed_ep: endpoint {
remote-endpoint = <&usb_hs_ep>;
};
};
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_led>;
led-1 {
label = "buzzer";
gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
};
osc_can: clock-osc-can {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <16000000>;
clock-output-names = "osc-can";
};
reg_audio: regulator-audio {
compatible = "regulator-fixed";
regulator-name = "wm8904_supply";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
reg_wifi_vmmc: regulator-wifi-vmmc {
compatible = "regulator-fixed";
regulator-name = "vmmc";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio2 10 GPIO_ACTIVE_HIGH>;
enable-active-high;
startup-delay-us = <100>;
off-on-delay-us = <20000>;
};
sound-wm8904 {
compatible = "simple-audio-card";
simple-audio-card,bitclock-master = <&dailink_master>;
simple-audio-card,format = "i2s";
simple-audio-card,frame-master = <&dailink_master>;
simple-audio-card,name = "wm8904-audio";
simple-audio-card,mclk-fs = <256>;
simple-audio-card,routing =
"Headphone Jack", "HPOUTL",
"Headphone Jack", "HPOUTR",
"IN2L", "Line In Jack",
"IN2R", "Line In Jack",
"Headphone Jack", "MICBIAS",
"IN1L", "Headphone Jack";
simple-audio-card,widgets =
"Microphone","Headphone Jack",
"Headphone", "Headphone Jack",
"Line", "Line In Jack";
dailink_master: simple-audio-card,codec {
sound-dai = <&wm8904>;
};
simple-audio-card,cpu {
sound-dai = <&sai3>;
};
};
sound-spdif {
compatible = "fsl,imx-audio-spdif";
model = "imx-spdif";
spdif-controller = <&spdif1>;
spdif-out;
spdif-in;
};
};
/* CAN BUS */
&ecspi2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi2>;
status = "okay";
can: can@0 {
compatible = "microchip,mcp2515";
reg = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_canbus>;
clocks = <&osc_can>;
interrupt-parent = <&gpio1>;
interrupts = <14 IRQ_TYPE_LEVEL_HIGH>;
spi-max-frequency = <10000000>;
};
};
&fec1 {
@@ -40,7 +150,135 @@ vddio: vddio-regulator {
};
};
&i2c3 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
status = "okay";
wm8904: audio-codec@1a {
compatible = "wlf,wm8904";
reg = <0x1a>;
#sound-dai-cells = <0>;
clocks = <&clk IMX8MM_CLK_SAI3_ROOT>;
clock-names = "mclk";
DCVDD-supply = <&reg_audio>;
DBVDD-supply = <&reg_audio>;
AVDD-supply = <&reg_audio>;
CPVDD-supply = <&reg_audio>;
MICVDD-supply = <&reg_audio>;
};
rtc@32 {
compatible = "epson,rx8025";
reg = <0x32>;
};
};
/* AUDIO */
&sai3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai3>;
assigned-clocks = <&clk IMX8MM_CLK_SAI3>;
assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
assigned-clock-rates = <24576000>;
status = "okay";
};
&spdif1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spdif1>;
assigned-clocks = <&clk IMX8MM_CLK_SPDIF1>;
assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
assigned-clock-rates = <24576000>;
clocks = <&clk IMX8MM_CLK_AUDIO_AHB>, <&clk IMX8MM_CLK_24M>,
<&clk IMX8MM_CLK_SPDIF1>, <&clk IMX8MM_CLK_DUMMY>,
<&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>,
<&clk IMX8MM_CLK_AUDIO_AHB>, <&clk IMX8MM_CLK_DUMMY>,
<&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>,
<&clk IMX8MM_AUDIO_PLL1_OUT>, <&clk IMX8MM_AUDIO_PLL2_OUT>;
clock-names = "core", "rxtx0", "rxtx1", "rxtx2", "rxtx3",
"rxtx4", "rxtx5", "rxtx6", "rxtx7", "spba", "pll8k", "pll11k";
status = "okay";
};
/* USBOTG */
&usbotg1 {
dr_mode = "otg";
usb-role-switch;
status = "okay";
port {
usb_hs_ep: endpoint {
remote-endpoint = <&high_speed_ep>;
};
};
};
&usbotg2 {
dr_mode = "host";
status = "okay";
};
/* Wifi */
&usdhc1 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>;
bus-width = <4>;
vmmc-supply = <&reg_wifi_vmmc>;
cap-power-off-card;
keep-power-in-suspend;
non-removable;
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
wifi: wifi@1 {
compatible = "brcm,bcm4329-fmac";
reg = <1>;
interrupt-parent = <&gpio2>;
interrupts = <9 IRQ_TYPE_LEVEL_LOW>;
interrupt-names = "host-wake";
};
};
/* SD-card */
&usdhc2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
bus-width = <4>;
status = "okay";
};
&iomuxc {
pinctrl_canbus: canbusgrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x14
>;
};
pinctrl_ecspi2: ecspi2grp {
fsl,pins = <
MX8MM_IOMUXC_ECSPI2_SS0_ECSPI2_SS0 0x82
MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x82
MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x82
MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x82
>;
};
pinctrl_usb_otg: usbotggrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x140 /* otg_id */
MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x19 /* otg_vbus */
>;
};
pinctrl_fec1: fec1grp {
fsl,pins = <
MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
@@ -60,4 +298,101 @@ MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
>;
};
pinctrl_sai3: sai3grp {
fsl,pins = <
MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6
MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6
MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6
MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6
MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6
>;
};
pinctrl_spdif1: spdif1grp {
fsl,pins = <
MX8MM_IOMUXC_SPDIF_TX_SPDIF1_OUT 0xd6
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190
MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0
MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0
MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0
MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0
MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0
>;
};
pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp{
fsl,pins = <
MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194
MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4
MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4
MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4
MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4
MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4
>;
};
pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
fsl,pins = <
MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196
MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6
MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6
MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6
MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6
MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6
>;
};
pinctrl_usdhc1_gpio: usdhc1-gpiogrp {
fsl,pins = <
MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x41 /* wl_reg_on */
MX8MM_IOMUXC_SD1_DATA7_GPIO2_IO9 0x41 /* wl_host_wake */
MX8MM_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x141 /* LP0: 32KHz */
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
>;
};
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
fsl,pins = <
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
>;
};
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
fsl,pins = <
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
>;
};
};

131
arch/arm64/boot/dts/freescale/imx8mm-kontron-bl.dts
View File

@@ -25,6 +25,17 @@ osc_can: clock-osc-can {
clock-output-names = "osc-can";
};
hdmi-out {
compatible = "hdmi-connector";
type = "a";
port {
hdmi_in_conn: endpoint {
remote-endpoint = <&bridge_out_conn>;
};
};
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
@@ -132,6 +143,86 @@ ethphy: ethernet-phy@0 {
};
};
&gpio4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio4>;
dsi_mux_sel_hdmi: dsi-mux-sel-hdmi-hog {
gpio-hog;
gpios = <14 GPIO_ACTIVE_HIGH>;
output-high;
line-name = "dsi-mux-sel";
};
dsi_mux_sel_lvds: dsi-mux-sel-lvds-hog {
gpio-hog;
gpios = <14 GPIO_ACTIVE_HIGH>;
output-low;
line-name = "dsi-mux-sel";
status = "disabled";
};
dsi-mux-oe-hog {
gpio-hog;
gpios = <15 GPIO_ACTIVE_LOW>;
output-high;
line-name = "dsi-mux-oe";
};
};
&i2c3 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
status = "okay";
lvds: bridge@2c {
compatible = "ti,sn65dsi84";
reg = <0x2c>;
enable-gpios = <&gpio4 26 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sn65dsi84>;
status = "disabled";
};
hdmi: hdmi@39 {
compatible = "adi,adv7535";
reg = <0x39>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_adv7535>;
adi,dsi-lanes = <4>;
interrupt-parent = <&gpio4>;
interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
a2vdd-supply = <&reg_vdd_1v8>;
avdd-supply = <&reg_vdd_1v8>;
dvdd-supply = <&reg_vdd_1v8>;
pvdd-supply = <&reg_vdd_1v8>;
v1p2-supply = <&reg_vdd_1v8>;
v3p3-supply = <&reg_vdd_3v3>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
bridge_in_dsi_hdmi: endpoint {
remote-endpoint = <&mipi_dsi_out>;
};
};
port@1 {
reg = <1>;
bridge_out_conn: endpoint {
remote-endpoint = <&hdmi_in_conn>;
};
};
};
};
};
&i2c4 {
clock-frequency = <100000>;
pinctrl-names = "default";
@@ -144,6 +235,19 @@ rx8900: rtc@32 {
};
};
&lcdif {
status = "okay";
};
&mipi_dsi {
samsung,esc-clock-frequency = <54000000>;
status = "okay";
};
&mipi_dsi_out {
remote-endpoint = <&bridge_in_dsi_hdmi>;
};
&pwm2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm2>;
@@ -207,6 +311,12 @@ &iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio>;
pinctrl_adv7535: adv7535grp {
fsl,pins = <
MX8MM_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x19
>;
};
pinctrl_can: cangrp {
fsl,pins = <
MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x19
@@ -277,6 +387,20 @@ MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x19
>;
};
pinctrl_gpio4: gpio4grp {
fsl,pins = <
MX8MM_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x19
MX8MM_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x19
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x40000083
MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x40000083
>;
};
pinctrl_i2c4: i2c4grp {
fsl,pins = <
MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x40000083
@@ -290,6 +414,13 @@ MX8MM_IOMUXC_SPDIF_RX_PWM2_OUT 0x19
>;
};
pinctrl_sn65dsi84: sn65dsi84grp {
fsl,pins = <
MX8MM_IOMUXC_SAI2_TXD0_GPIO4_IO26 0x19
MX8MM_IOMUXC_SD2_WP_GPIO2_IO20 0x19
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX8MM_IOMUXC_SAI2_RXC_UART1_DCE_RX 0x0

189
arch/arm64/boot/dts/freescale/imx8mm-kontron-dl.dtso Normal file
View File

@@ -0,0 +1,189 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2024 Kontron Electronics GmbH
*/
/dts-v1/;
/plugin/;
#include <dt-bindings/gpio/gpio.h>
#include "imx8mm-pinfunc.h"
&{/} {
compatible = "kontron,imx8mm-bl", "kontron,imx8mm-sl", "fsl,imx8mm";
backlight: backlight {
compatible = "pwm-backlight";
pwms = <&pwm1 0 50000 0>;
brightness-levels = <0 100>;
num-interpolated-steps = <100>;
default-brightness-level = <100>;
};
panel {
compatible = "jenson,bl-jt60050-01a", "panel-lvds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_panel>;
backlight = <&backlight>;
data-mapping = "vesa-24";
enable-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>;
height-mm = <86>;
width-mm = <154>;
panel-timing {
clock-frequency = <51200000>;
hactive = <1024>;
vactive = <600>;
hsync-len = <1>;
hfront-porch = <160>;
hback-porch = <160>;
vsync-len = <1>;
vfront-porch = <12>;
vback-porch = <23>;
};
port {
panel_out_bridge: endpoint {
remote-endpoint = <&bridge_out_panel>;
};
};
};
};
&dsi_mux_sel_hdmi {
status = "disabled";
};
&dsi_mux_sel_lvds {
status = "okay";
};
&mipi_dsi_out {
remote-endpoint = <&bridge_in_dsi_lvds>;
};
&gpio3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio3>;
panel-rst-hog {
gpio-hog;
gpios = <20 GPIO_ACTIVE_HIGH>;
output-high;
line-name = "panel-reset";
};
panel-stby-hog {
gpio-hog;
gpios = <21 GPIO_ACTIVE_HIGH>;
output-high;
line-name = "panel-standby";
};
panel-hinv-hog {
gpio-hog;
gpios = <24 GPIO_ACTIVE_HIGH>;
output-high;
line-name = "panel-horizontal-invert";
};
panel-vinv-hog {
gpio-hog;
gpios = <25 GPIO_ACTIVE_HIGH>;
output-low;
line-name = "panel-vertical-invert";
};
};
&hdmi {
status = "disabled";
};
&i2c2 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
touchscreen@5d {
compatible = "goodix,gt928";
reg = <0x5d>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_touch>;
interrupt-parent = <&gpio3>;
interrupts = <22 8>;
reset-gpios = <&gpio3 23 0>;
irq-gpios = <&gpio3 22 0>;
};
};
&lvds {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
bridge_in_dsi_lvds: endpoint {
remote-endpoint = <&mipi_dsi_out>;
data-lanes = <1 2>;
};
};
port@2 {
reg = <2>;
bridge_out_panel: endpoint {
remote-endpoint = <&panel_out_bridge>;
};
};
};
};
&pwm1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm1>;
status = "okay";
};
&iomuxc {
pinctrl_gpio3: gpio3grp {
fsl,pins = <
MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x19
MX8MM_IOMUXC_SAI5_RXC_GPIO3_IO20 0x19
MX8MM_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x19
MX8MM_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x19
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x40000083
MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x40000083
>;
};
pinctrl_panel: panelgrp {
fsl,pins = <
MX8MM_IOMUXC_SAI5_RXFS_GPIO3_IO19 0x19
>;
};
pinctrl_pwm1: pwm1grp {
fsl,pins = <
MX8MM_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT 0x6
>;
};
pinctrl_touch: touchgrp {
fsl,pins = <
MX8MM_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x19
MX8MM_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x19
>;
};
};

5
arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx.dts
View File

@@ -75,6 +75,11 @@ expander2: gpio@27 {
};
};
&mipi_dsi {
samsung,burst-clock-frequency = <891000000>;
samsung,esc-clock-frequency = <20000000>;
};
&pcie_phy {
fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
fsl,clkreq-unsupported;

7
arch/arm64/boot/dts/freescale/imx8mm-venice-gw700x.dtsi
View File

@@ -9,6 +9,11 @@
#include <dt-bindings/net/ti-dp83867.h>
/ {
aliases {
rtc0 = &gsc_rtc;
rtc1 = &snvs_rtc;
};
memory@40000000 {
device_type = "memory";
reg = <0x0 0x40000000 0 0x80000000>;
@@ -292,7 +297,7 @@ eeprom@53 {
pagesize = <16>;
};
rtc@68 {
gsc_rtc: rtc@68 {
compatible = "dallas,ds1672";
reg = <0x68>;
};

4
arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-rs232-rts.dtso
View File

@@ -15,10 +15,6 @@
/dts-v1/;
/plugin/;
&{/} {
compatible = "gw,imx8mm-gw73xx-0x";
};
&gpio4 {
rs485-en-hog {
gpio-hog;

4
arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-rs422.dtso
View File

@@ -18,10 +18,6 @@
/dts-v1/;
/plugin/;
&{/} {
compatible = "gw,imx8mm-gw73xx-0x";
};
&gpio4 {
rs485-en-hog {
gpio-hog;

4
arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x-rs485.dtso
View File

@@ -18,10 +18,6 @@
/dts-v1/;
/plugin/;
&{/} {
compatible = "gw,imx8mm-gw73xx-0x";
};
&gpio4 {
rs485-en-hog {
gpio-hog;

16
arch/arm64/boot/dts/freescale/imx8mm-venice-gw75xx.dtsi
View File

@@ -116,6 +116,16 @@ &i2c2 {
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
accelerometer@19 {
compatible = "st,lis2de12";
reg = <0x19>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_accel>;
interrupt-parent = <&gpio5>;
interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
st,drdy-int-pin = <1>;
};
eeprom@52 {
compatible = "atmel,24c32";
reg = <0x52>;
@@ -198,6 +208,12 @@ MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x40000040 /* GPIOC */
>;
};
pinctrl_accel: accelgrp {
fsl,pins = <
MX8MM_IOMUXC_ECSPI1_MISO_GPIO5_IO8 0x159
>;
};
pinctrl_gpio_leds: gpioledgrp {
fsl,pins = <
MX8MM_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x6 /* LEDG */

4
arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts
View File

@@ -22,6 +22,8 @@ aliases {
ethernet2 = &lan2;
ethernet3 = &lan3;
ethernet4 = &lan4;
rtc0 = &gsc_rtc;
rtc1 = &snvs_rtc;
usb0 = &usbotg1;
usb1 = &usbotg2;
};
@@ -497,7 +499,7 @@ eeprom@53 {
pagesize = <16>;
};
rtc@68 {
gsc_rtc: rtc@68 {
compatible = "dallas,ds1672";
reg = <0x68>;
};

4
arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts
View File

@@ -19,6 +19,8 @@ / {
aliases {
ethernet1 = &eth1;
rtc0 = &gsc_rtc;
rtc1 = &snvs_rtc;
usb0 = &usbotg1;
usb1 = &usbotg2;
};
@@ -564,7 +566,7 @@ eeprom@53 {
pagesize = <16>;
};
rtc@68 {
gsc_rtc: rtc@68 {
compatible = "dallas,ds1672";
reg = <0x68>;
};

4
arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts
View File

@@ -18,6 +18,8 @@ / {
aliases {
ethernet0 = &fec1;
rtc0 = &gsc_rtc;
rtc1 = &snvs_rtc;
usb0 = &usbotg1;
};
@@ -394,7 +396,7 @@ eeprom@53 {
pagesize = <16>;
};
rtc@68 {
gsc_rtc: rtc@68 {
compatible = "dallas,ds1672";
reg = <0x68>;
};

7
arch/arm64/boot/dts/freescale/imx8mm-venice-gw7904.dts
View File

@@ -16,6 +16,11 @@ / {
model = "Gateworks Venice GW7904 i.MX8MM board";
compatible = "gateworks,imx8mm-gw7904", "fsl,imx8mm";
aliases {
rtc0 = &gsc_rtc;
rtc1 = &snvs_rtc;
};
chosen {
stdout-path = &uart2;
};
@@ -438,7 +443,7 @@ eeprom@53 {
pagesize = <16>;
};
rtc@68 {
gsc_rtc: rtc@68 {
compatible = "dallas,ds1672";
reg = <0x68>;
};

471
arch/arm64/boot/dts/freescale/imx8mm-verdin-ivy.dtsi Normal file
View File

@@ -0,0 +1,471 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright 2024 Toradex
*
* Common dtsi for Verdin IMX8MM SoM on Ivy carrier board
*
* https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx-8m-mini-nano
* https://www.toradex.com/products/carrier-board/ivy-carrier-board
*/
#include <dt-bindings/mux/mux.h>
#include <dt-bindings/leds/common.h>
/ {
/* AIN1 Voltage w/o AIN1_MODE gpio control */
ain1_voltage_unmanaged: voltage-divider-ain1 {
compatible = "voltage-divider";
#io-channel-cells = <1>;
io-channels = <&ivy_adc1 0>;
full-ohms = <19>;
output-ohms = <1>;
};
/* AIN1 Current w/o AIN1_MODE gpio control */
ain1_current_unmanaged: current-sense-shunt-ain1 {
compatible = "current-sense-shunt";
#io-channel-cells = <0>;
io-channels = <&ivy_adc1 1>;
shunt-resistor-micro-ohms = <100000000>;
};
/* AIN1_MODE - SODIMM 216 */
ain1_mode_mux_ctrl: mux-controller-0 {
compatible = "gpio-mux";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio5>;
#mux-control-cells = <0>;
mux-gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>;
};
ain1-voltage {
compatible = "io-channel-mux";
channels = "ain1_voltage", "";
io-channels = <&ain1_voltage_unmanaged 0>;
io-channel-names = "parent";
mux-controls = <&ain1_mode_mux_ctrl>;
settle-time-us = <1000>;
};
ain1-current {
compatible = "io-channel-mux";
channels = "", "ain1_current";
io-channels = <&ain1_current_unmanaged>;
io-channel-names = "parent";
mux-controls = <&ain1_mode_mux_ctrl>;
settle-time-us = <1000>;
};
/* AIN2 Voltage w/o AIN2_MODE gpio control */
ain2_voltage_unmanaged: voltage-divider-ain2 {
compatible = "voltage-divider";
#io-channel-cells = <1>;
io-channels = <&ivy_adc2 0>;
full-ohms = <19>;
output-ohms = <1>;
};
/* AIN2 Current w/o AIN2_MODE gpio control */
ain2_current_unmanaged: current-sense-shunt-ain2 {
compatible = "current-sense-shunt";
#io-channel-cells = <0>;
io-channels = <&ivy_adc2 1>;
shunt-resistor-micro-ohms = <100000000>;
};
/* AIN2_MODE - SODIMM 218 */
ain2_mode_mux_ctrl: mux-controller-1 {
compatible = "gpio-mux";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio6>;
#mux-control-cells = <0>;
mux-gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>;
};
ain2-voltage {
compatible = "io-channel-mux";
channels = "ain2_voltage", "";
io-channels = <&ain2_voltage_unmanaged 0>;
io-channel-names = "parent";
mux-controls = <&ain2_mode_mux_ctrl>;
settle-time-us = <1000>;
};
ain2-current {
compatible = "io-channel-mux";
channels = "", "ain2_current";
io-channels = <&ain2_current_unmanaged>;
io-channel-names = "parent";
mux-controls = <&ain2_mode_mux_ctrl>;
settle-time-us = <1000>;
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ivy_leds>;
/* D7 Blue - SODIMM 30 - LEDs.GPIO1 */
led-0 {
color = <LED_COLOR_ID_BLUE>;
default-state = "off";
function = LED_FUNCTION_STATUS;
function-enumerator = <1>;
gpios = <&gpio4 25 GPIO_ACTIVE_HIGH>;
};
/* D7 Green - SODIMM 32 - LEDs.GPIO2 */
led-1 {
color = <LED_COLOR_ID_GREEN>;
default-state = "off";
function = LED_FUNCTION_STATUS;
function-enumerator = <1>;
gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>;
};
/* D7 Red - SODIMM 34 - LEDs.GPIO3 */
led-2 {
color = <LED_COLOR_ID_RED>;
default-state = "off";
function = LED_FUNCTION_STATUS;
function-enumerator = <1>;
gpios = <&gpio4 26 GPIO_ACTIVE_HIGH>;
};
/* D8 Blue - SODIMM 36 - LEDs.GPIO4 */
led-3 {
color = <LED_COLOR_ID_BLUE>;
default-state = "off";
function = LED_FUNCTION_STATUS;
function-enumerator = <2>;
gpios = <&gpio4 23 GPIO_ACTIVE_HIGH>;
};
/* D8 Green - SODIMM 54 - LEDs.GPIO5 */
led-4 {
color = <LED_COLOR_ID_GREEN>;
default-state = "off";
function = LED_FUNCTION_STATUS;
function-enumerator = <2>;
gpios = <&gpio3 1 GPIO_ACTIVE_HIGH>;
};
/* D8 Red - SODIMM 44 - LEDs.GPIO6 */
led-5 {
color = <LED_COLOR_ID_RED>;
default-state = "off";
function = LED_FUNCTION_STATUS;
function-enumerator = <2>;
gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>;
};
/* D9 Blue - SODIMM 46 - LEDs.GPIO7 */
led-6 {
color = <LED_COLOR_ID_BLUE>;
default-state = "off";
function = LED_FUNCTION_STATUS;
function-enumerator = <3>;
gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>;
};
/* D9 Red - SODIMM 48 - LEDs.GPIO8 */
led-7 {
color = <LED_COLOR_ID_RED>;
default-state = "off";
function = LED_FUNCTION_STATUS;
function-enumerator = <3>;
gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>;
};
};
reg_3v2_ain1: regulator-3v2-ain1 {
compatible = "regulator-fixed";
regulator-max-microvolt = <3200000>;
regulator-min-microvolt = <3200000>;
regulator-name = "+3V2_AIN1";
};
reg_3v2_ain2: regulator-3v2-ain2 {
compatible = "regulator-fixed";
regulator-max-microvolt = <3200000>;
regulator-min-microvolt = <3200000>;
regulator-name = "+3V2_AIN2";
};
/* Ivy Power Supply Input Voltage */
ivy-input-voltage {
compatible = "voltage-divider";
/* Verdin ADC_1 */
io-channels = <&verdin_som_adc 7>;
full-ohms = <204700>; /* 200k + 4.7k */
output-ohms = <4700>;
};
ivy-5v-voltage {
compatible = "voltage-divider";
/* Verdin ADC_2 */
io-channels = <&verdin_som_adc 6>;
full-ohms = <39000>; /* 27k + 12k */
output-ohms = <12000>;
};
ivy-3v3-voltage {
compatible = "voltage-divider";
/* Verdin ADC_3 */
io-channels = <&verdin_som_adc 5>;
full-ohms = <54000>; /* 27k + 27k */
output-ohms = <27000>;
};
ivy-1v8-voltage {
compatible = "voltage-divider";
/* Verdin ADC_4 */
io-channels = <&verdin_som_adc 4>;
full-ohms = <39000>; /* 12k + 27k */
output-ohms = <27000>;
};
};
/* Verdin SPI_1 */
&ecspi2 {
pinctrl-0 = <&pinctrl_ecspi2>,
<&pinctrl_gpio1>,
<&pinctrl_gpio4>;
cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>,
<&gpio3 4 GPIO_ACTIVE_LOW>,
<&gpio5 27 GPIO_ACTIVE_LOW>;
status = "okay";
tpm@1 {
compatible = "infineon,slb9670", "tcg,tpm_tis-spi";
reg = <1>;
spi-max-frequency = <18500000>;
};
fram@2 {
compatible = "fujitsu,mb85rs256", "atmel,at25";
reg = <2>;
address-width = <16>;
size = <32768>;
spi-max-frequency = <33000000>;
pagesize = <1>;
};
};
/* EEPROM on Ivy */
&eeprom_carrier_board {
status = "okay";
};
/* Verdin ETH_1 */
&fec1 {
status = "okay";
};
&gpio3 {
gpio-line-names =
"", /* 0 */
"",
"REL3", /* SODIMM 64 */
"",
"",
"",
"DIG_1", /* SODIMM 56 */
"DIG_2", /* SODIMM 58 */
"REL1", /* SODIMM 60 */
"REL2", /* SODIMM 62 */
"", /* 10 */
"",
"",
"",
"REL4", /* SODIMM 66 */
"",
"",
"",
"",
"",
"", /* 20 */
"",
"",
"",
"",
"";
};
&gpio5 {
gpio-line-names =
"", /* 0 */
"",
"",
"",
"",
"GPIO2", /* Verdin GPIO_2 - SODIMM 208 */
"",
"",
"",
"",
"", /* 10 */
"",
"",
"",
"",
"",
"",
"",
"",
"",
"", /* 20 */
"",
"",
"",
"",
"",
"GPIO3", /* Verdin GPIO_3 - SODIMM 210 */
"",
"",
"";
};
/* Temperature sensor on Ivy */
&hwmon_temp {
compatible = "ti,tmp1075";
status = "okay";
};
/* Verdin I2C_4 CSI */
&i2c3 {
status = "okay";
ivy_adc1: adc@40 {
compatible = "ti,ads1119";
reg = <0x40>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio7>;
interrupt-parent = <&gpio1>;
interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
avdd-supply = <&reg_3v2_ain1>;
dvdd-supply = <&reg_3v2_ain1>;
vref-supply = <&reg_3v2_ain1>;
#address-cells = <1>;
#io-channel-cells = <1>;
#size-cells = <0>;
/* AIN1 0-33V Voltage Input */
channel@0 {
reg = <0>;
diff-channels = <0 1>;
};
/* AIN1 0-20mA Current Input */
channel@1 {
reg = <1>;
diff-channels = <2 3>;
};
};
ivy_adc2: adc@41 {
compatible = "ti,ads1119";
reg = <0x41>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio8>;
interrupt-parent = <&gpio1>;
interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
avdd-supply = <&reg_3v2_ain2>;
dvdd-supply = <&reg_3v2_ain2>;
vref-supply = <&reg_3v2_ain2>;
#address-cells = <1>;
#io-channel-cells = <1>;
#size-cells = <0>;
/* AIN2 0-33V Voltage Input */
channel@0 {
reg = <0>;
diff-channels = <0 1>;
};
/* AIN2 0-20mA Current Input */
channel@1 {
reg = <1>;
diff-channels = <2 3>;
};
};
};
/* Verdin I2C_1 */
&i2c4 {
status = "okay";
};
/* Verdin PCIE_1 */
&pcie0 {
status = "okay";
};
&pcie_phy {
status = "okay";
};
/* Verdin UART_3 */
&uart1 {
status = "okay";
};
/* Verdin UART_1 */
&uart2 {
status = "okay";
};
/* Verdin UART_2 */
&uart3 {
linux,rs485-enabled-at-boot-time;
rs485-rx-during-tx;
status = "okay";
};
/* Verdin USB_1*/
&usbotg1 {
status = "okay";
};
/* Verdin USB_2 */
&usbotg2 {
status = "okay";
};
/* Verdin SD_1 */
&usdhc2 {
status = "okay";
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio2>, <&pinctrl_gpio3>,
<&pinctrl_ivy_dig_inputs>, <&pinctrl_ivy_relays>;
pinctrl_ivy_dig_inputs: ivydiginputsgrp {
fsl,pins =
<MX8MM_IOMUXC_NAND_DATA00_GPIO3_IO6 0x96>, /* SODIMM 56 */
<MX8MM_IOMUXC_NAND_DATA01_GPIO3_IO7 0x96>; /* SODIMM 58 */
};
pinctrl_ivy_leds: ivyledsgrp {
fsl,pins =
<MX8MM_IOMUXC_SAI2_TXC_GPIO4_IO25 0x16>, /* SODIMM 30 */
<MX8MM_IOMUXC_SAI2_TXFS_GPIO4_IO24 0x16>, /* SODIMM 32 */
<MX8MM_IOMUXC_SAI2_TXD0_GPIO4_IO26 0x16>, /* SODIMM 34 */
<MX8MM_IOMUXC_SAI2_RXD0_GPIO4_IO23 0x16>, /* SODIMM 36 */
<MX8MM_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x16>, /* SODIMM 44 */
<MX8MM_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x16>, /* SODIMM 46 */
<MX8MM_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x16>, /* SODIMM 48 */
<MX8MM_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x16>; /* SODIMM 54 */
};
pinctrl_ivy_relays: ivyrelaysgrp {
fsl,pins =
<MX8MM_IOMUXC_NAND_DATA02_GPIO3_IO8 0x16>, /* SODIMM 60 */
<MX8MM_IOMUXC_NAND_DATA03_GPIO3_IO9 0x16>, /* SODIMM 62 */
<MX8MM_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x16>, /* SODIMM 64 */
<MX8MM_IOMUXC_NAND_DQS_GPIO3_IO14 0x16>; /* SODIMM 66 */
};
};

18
arch/arm64/boot/dts/freescale/imx8mm-verdin-nonwifi-ivy.dts Normal file
View File

@@ -0,0 +1,18 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright 2024 Toradex
*/
/dts-v1/;
#include "imx8mm-verdin.dtsi"
#include "imx8mm-verdin-nonwifi.dtsi"
#include "imx8mm-verdin-ivy.dtsi"
/ {
model = "Toradex Verdin iMX8M Mini on Ivy";
compatible = "toradex,verdin-imx8mm-nonwifi-ivy",
"toradex,verdin-imx8mm-nonwifi",
"toradex,verdin-imx8mm",
"fsl,imx8mm";
};

18
arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi-ivy.dts Normal file
View File

@@ -0,0 +1,18 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright 2024 Toradex
*/
/dts-v1/;
#include "imx8mm-verdin.dtsi"
#include "imx8mm-verdin-wifi.dtsi"
#include "imx8mm-verdin-ivy.dtsi"
/ {
model = "Toradex Verdin iMX8M Mini WB on Ivy";
compatible = "toradex,verdin-imx8mm-wifi-ivy",
"toradex,verdin-imx8mm-wifi",
"toradex,verdin-imx8mm",
"fsl,imx8mm";
};

9
arch/arm64/boot/dts/freescale/imx8mm-verdin.dtsi
View File

@@ -162,7 +162,7 @@ reg_usdhc2_vmmc: regulator-usdhc2 {
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3300000>;
regulator-name = "+V3.3_SD";
startup-delay-us = <2000>;
startup-delay-us = <20000>;
};
reserved-memory {
@@ -367,6 +367,7 @@ &i2c1 {
pinctrl-1 = <&pinctrl_i2c1_gpio>;
scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
single-master;
status = "okay";
pca9450: pmic@25 {
@@ -483,11 +484,12 @@ rtc_i2c: rtc@32 {
reg = <0x32>;
};
adc@49 {
verdin_som_adc: adc@49 {
compatible = "ti,ads1015";
reg = <0x49>;
#address-cells = <1>;
#size-cells = <0>;
#io-channel-cells = <1>;
/* Verdin I2C_1 (ADC_4 - ADC_3) */
channel@0 {
@@ -561,6 +563,7 @@ &i2c2 {
pinctrl-1 = <&pinctrl_i2c2_gpio>;
scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
single-master;
status = "disabled";
};
@@ -574,6 +577,7 @@ &i2c3 {
pinctrl-1 = <&pinctrl_i2c3_gpio>;
scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
single-master;
};
/* Verdin I2C_1 */
@@ -584,6 +588,7 @@ &i2c4 {
pinctrl-1 = <&pinctrl_i2c4_gpio>;
scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
single-master;
gpio_expander_21: gpio-expander@21 {
compatible = "nxp,pcal6416";

8
arch/arm64/boot/dts/freescale/imx8mm.dtsi
View File

@@ -1375,9 +1375,11 @@ pcie0: pcie@33800000 {
pcie0_ep: pcie-ep@33800000 {
compatible = "fsl,imx8mm-pcie-ep";
reg = <0x33800000 0x400000>,
<0x18000000 0x8000000>;
reg-names = "dbi", "addr_space";
reg = <0x33800000 0x100000>,
<0x18000000 0x8000000>,
<0x33900000 0x100000>,
<0x33b00000 0x100000>;
reg-names = "dbi", "addr_space", "dbi2", "atu";
num-lanes = <1>;
interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "dma";

29
arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl-mba8mx-usbotg.dtso
View File

@@ -29,12 +29,37 @@ usb_dr_connector: endpoint {
};
};
/*
* rst_usb_hub_hog and sel_usb_hub_hog have property 'output-high',
* dt overlay don't support /delete-property/. Both 'output-low' and
* 'output-high' will be exist under hog nodes if overlay file set
* 'output-low'. Workaround is disable these hog and create new hog with
* 'output-low'.
*/
&rst_usb_hub_hog {
output-low;
status = "disabled";
};
&expander0 {
rst-usb-low-hub-hog {
gpio-hog;
gpios = <13 0>;
output-low;
line-name = "RST_USB_HUB#";
};
};
&sel_usb_hub_hog {
output-low;
status = "disabled";
};
&gpio2 {
sel-usb-low-hub-hog {
gpio-hog;
gpios = <1 GPIO_ACTIVE_HIGH>;
output-low;
};
};
&usbotg1 {

5
arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl-mba8mx.dts
View File

@@ -64,6 +64,11 @@ expander2: gpio@27 {
};
};
&mipi_dsi {
samsung,burst-clock-frequency = <891000000>;
samsung,esc-clock-frequency = <20000000>;
};
&sai3 {
assigned-clocks = <&clk IMX8MN_CLK_SAI3>;
assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>;

4
arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dts
View File

@@ -17,6 +17,8 @@ / {
compatible = "gw,imx8mn-gw7902", "fsl,imx8mn";
aliases {
rtc0 = &gsc_rtc;
rtc1 = &snvs_rtc;
usb0 = &usbotg1;
};
@@ -562,7 +564,7 @@ eeprom@53 {
pagesize = <16>;
};
rtc@68 {
gsc_rtc: rtc@68 {
compatible = "dallas,ds1672";
reg = <0x68>;
};

255
arch/arm64/boot/dts/freescale/imx8mp-dhcom-drc02.dts Normal file
View File

@@ -0,0 +1,255 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2024 Marek Vasut <marex@denx.de>
*
* DHCOM iMX8MP variant:
* DHCM-iMX8ML8-C160-R204-F1638-SPI16-E2-CAN2-RTC-I-01D2
* DHCOM PCB number: 660-100 or newer
* DRC02 PCB number: 568-100 or newer
*/
/dts-v1/;
#include <dt-bindings/leds/common.h>
#include <dt-bindings/phy/phy-imx8-pcie.h>
#include "imx8mp-dhcom-som.dtsi"
/ {
model = "DH electronics i.MX8M Plus DHCOM on DRC02";
compatible = "dh,imx8mp-dhcom-drc02", "dh,imx8mp-dhcom-som",
"fsl,imx8mp";
chosen {
stdout-path = &uart1;
};
};
&eqos { /* First ethernet */
pinctrl-0 = <&pinctrl_eqos_rmii>;
phy-handle = <&ethphy0f>;
phy-mode = "rmii";
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>,
<&clk IMX8MP_SYS_PLL2_100M>,
<&clk IMX8MP_SYS_PLL2_50M>;
assigned-clock-rates = <0>, <100000000>, <50000000>;
};
&ethphy0g { /* Micrel KSZ9131RNXI */
status = "disabled";
};
&ethphy0f { /* SMSC LAN8740Ai */
status = "okay";
};
&fec { /* Second ethernet */
pinctrl-0 = <&pinctrl_fec_rmii>;
phy-handle = <&ethphy1f>;
phy-mode = "rmii";
status = "okay";
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>,
<&clk IMX8MP_SYS_PLL2_100M>,
<&clk IMX8MP_SYS_PLL2_50M>,
<&clk IMX8MP_SYS_PLL2_50M>;
assigned-clock-rates = <0>, <100000000>, <50000000>, <0>;
};
&ethphy1f { /* SMSC LAN8740Ai */
status = "okay";
};
&flexcan1 {
status = "okay";
};
&flexcan2 {
status = "okay";
};
&gpio1 {
gpio-line-names =
"DRC02-In1", "", "", "", "", "DHCOM-I", "DRC02-HW2", "DRC02-HW0",
"DHCOM-B", "DHCOM-A", "", "DHCOM-H", "", "", "", "",
"", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "";
/*
* NOTE: On DRC02, the RS485_RX_En is controlled by a separate
* GPIO line, however the i.MX8 UART driver assumes RX happens
* during TX anyway and that it only controls drive enable DE
* line. Hence, the RX is always enabled here.
*/
rs485-rx-en-hog {
gpio-hog;
gpios = <13 0>; /* GPIO Q */
line-name = "rs485-rx-en";
output-low;
};
};
&gpio2 {
gpio-line-names =
"", "", "", "", "", "", "", "",
"DHCOM-O", "DHCOM-N", "", "SOM-HW1", "", "", "", "",
"", "", "", "", "DRC02-In2", "", "", "",
"", "", "", "", "", "", "", "";
};
&gpio3 {
gpio-line-names =
"", "", "", "", "", "", "", "",
"", "", "", "", "", "", "SOM-HW0", "",
"", "", "", "", "", "", "SOM-MEM0", "SOM-MEM1",
"SOM-MEM2", "SOM-HW2", "", "", "", "", "", "";
};
&gpio4 {
gpio-line-names =
"", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "",
"", "", "", "SOM-HW1", "", "", "", "",
"", "", "", "DRC02-Out2", "", "", "", "";
};
&gpio5 {
gpio-line-names =
"", "", "DHCOM-C", "", "", "", "", "",
"", "", "", "", "", "", "", "",
"", "", "", "", "", "", "DHCOM-E", "DRC02-Out1",
"", "", "", "", "", "", "", "";
};
/* No HS connector on this SoM variant, so no HDMI, PCIe and only USB HS. */
&hdmi_blk_ctrl {
status = "disabled";
};
&hdmi_pvi {
status = "disabled";
};
&hdmi_tx {
status = "disabled";
};
&hdmi_tx_phy {
status = "disabled";
};
&i2c3 {
/* Resistive touch controller not populated on this one SoM variant. */
touchscreen@49 {
status = "disabled";
};
};
&irqsteer_hdmi {
status = "disabled";
};
&lcdif3 {
status = "disabled";
};
&pcie_phy {
status = "disabled";
};
&pcie {
status = "disabled";
};
/* Console UART */
&pinctrl_uart1 {
fsl,pins = <
/* No pull-ups on DRC02, enable in-SoC pull-ups */
MX8MP_IOMUXC_SAI2_RXC__UART1_DCE_RX 0x149
MX8MP_IOMUXC_SAI2_RXFS__UART1_DCE_TX 0x149
>;
};
&pinctrl_uart3 {
fsl,pins = <
/* No pull-ups on DRC02, enable in-SoC pull-ups */
MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX 0x149
MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX 0x149
>;
};
&uart1 {
/*
* Due to the use of CAN2 the signals for CAN2 Tx and Rx are routed to
* DHCOM UART1 RTS/CTS pins. Therefore this UART have to use DHCOM GPIOs
* for RTS/CTS. So configure DHCOM GPIO I as RTS and GPIO M as CTS.
*/
/delete-property/ uart-has-rtscts;
cts-gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>; /* GPIO M */
pinctrl-0 = <&pinctrl_uart1 &pinctrl_dhcom_i &pinctrl_dhcom_m>;
pinctrl-names = "default";
rts-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; /* GPIO I */
};
&uart3 {
/*
* On DRC02 this UART is used as RS485 interface and RS485_TX_En is
* controlled by DHCOM GPIO P. So remove RTS/CTS pins and the property
* uart-has-rtscts from this UART and add the DHCOM GPIO P pin via
* rts-gpios. The RS485_RX_En is controlled by DHCOM GPIO Q, see gpio1
* node above.
*/
/delete-property/ uart-has-rtscts;
linux,rs485-enabled-at-boot-time;
pinctrl-0 = <&pinctrl_uart3 &pinctrl_dhcom_p &pinctrl_dhcom_q>;
pinctrl-names = "default";
rts-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>; /* GPIO P */
};
/* No WiFi/BT chipset on this SoM variant. */
&uart2 {
bluetooth {
status = "disabled";
};
};
/* USB_OTG port is not routed out on DRC02. */
&usb3_0 {
status = "disabled";
};
&usb_dwc3_0 {
status = "disabled";
};
/* USB_HOST port has USB Hub connected to it, PWR/OC pins are unused */
&usb3_1 {
fsl,disable-port-power-control;
fsl,permanently-attached;
};
&usb_dwc3_1 {
dr_mode = "host";
maximum-speed = "high-speed";
};
/* No WiFi/BT chipset on this SoM variant. */
&usdhc1 {
status = "disabled";
};
&iomuxc {
/*
* GPIO I is connected to UART1_RTS
* GPIO M is connected to UART1_CTS
* GPIO P is connected to RS485_TX_En
* GPIO Q is connected to RS485_RX_En
*/
pinctrl-0 = <&pinctrl_hog_base
&pinctrl_dhcom_a &pinctrl_dhcom_b &pinctrl_dhcom_c
&pinctrl_dhcom_d &pinctrl_dhcom_e &pinctrl_dhcom_f
&pinctrl_dhcom_g &pinctrl_dhcom_h &pinctrl_dhcom_j
&pinctrl_dhcom_k &pinctrl_dhcom_l &pinctrl_dhcom_n
&pinctrl_dhcom_o &pinctrl_dhcom_r &pinctrl_dhcom_s
&pinctrl_dhcom_int>;
};

176
arch/arm64/boot/dts/freescale/imx8mp-dhcom-picoitx.dts Normal file
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (C) 2023-2024 Marek Vasut <marex@denx.de>
*
* DHCOM iMX8MP variant:
* DHCM-iMX8ML8-C160-R204-F1638-SPI16-E-SD-RTC-T-RGB-I-01D2
* DHCOM PCB number: 660-200 or newer
* PicoITX PCB number: 487-600 or newer
*/
/dts-v1/;
#include <dt-bindings/leds/common.h>
#include "imx8mp-dhcom-som.dtsi"
/ {
model = "DH electronics i.MX8M Plus DHCOM PicoITX";
compatible = "dh,imx8mp-dhcom-picoitx", "dh,imx8mp-dhcom-som",
"fsl,imx8mp";
chosen {
stdout-path = &uart1;
};
led {
compatible = "gpio-leds";
led-0 {
color = <LED_COLOR_ID_YELLOW>;
default-state = "off";
function = LED_FUNCTION_INDICATOR;
gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; /* GPIO I */
pinctrl-0 = <&pinctrl_dhcom_i>;
pinctrl-names = "default";
};
};
};
&eqos { /* First ethernet */
pinctrl-0 = <&pinctrl_eqos_rmii>;
phy-handle = <&ethphy0f>;
phy-mode = "rmii";
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>,
<&clk IMX8MP_SYS_PLL2_100M>,
<&clk IMX8MP_SYS_PLL2_50M>;
assigned-clock-rates = <0>, <100000000>, <50000000>;
};
&ethphy0g { /* Micrel KSZ9131RNXI */
status = "disabled";
};
&ethphy0f { /* SMSC LAN8740Ai */
status = "okay";
};
&fec {
status = "disabled";
};
&flexcan1 {
status = "okay";
};
&gpio1 {
gpio-line-names =
"DHCOM-G", "", "", "",
"", "DHCOM-I", "PicoITX-HW0", "PicoITX-HW2",
"DHCOM-B", "DHCOM-A", "", "DHCOM-H", "", "", "", "",
"", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "";
};
&gpio2 {
gpio-line-names =
"", "", "", "", "", "", "", "",
"", "", "", "PicoITX-HW1", "", "", "", "",
"", "", "", "", "DHCOM-INT", "", "", "",
"", "", "", "", "", "", "", "";
};
&gpio4 {
gpio-line-names =
"", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "",
"", "", "", "SOM-HW1", "", "", "", "",
"", "", "", "PicoITX-Out2", "", "", "", "";
};
&gpio5 {
gpio-line-names =
"", "", "PicoITX-In2", "", "", "", "", "",
"", "", "", "", "", "", "", "",
"", "", "", "",
"", "", "PicoITX-In1", "PicoITX-Out1",
"", "", "", "", "", "", "", "";
};
/* No HS connector on this SoM variant, so no HDMI, PCIe and only USB HS. */
&hdmi_blk_ctrl {
status = "disabled";
};
&hdmi_pvi {
status = "disabled";
};
&hdmi_tx {
status = "disabled";
};
&hdmi_tx_phy {
status = "disabled";
};
&irqsteer_hdmi {
status = "disabled";
};
&lcdif3 {
status = "disabled";
};
&pcie_phy {
status = "disabled";
};
&pcie {
status = "disabled";
};
/* No WiFi/BT chipset on this SoM variant. */
&uart2 {
bluetooth {
status = "disabled";
};
};
/* USB_OTG port is not routed out on PicoITX. */
&usb3_0 {
status = "disabled";
};
&usb_dwc3_0 {
status = "disabled";
};
&usb3_1 {
fsl,over-current-active-low;
};
&usb_dwc3_1 {
dr_mode = "host";
maximum-speed = "high-speed";
};
/* No WiFi/BT chipset on this SoM variant. */
&usdhc1 {
status = "disabled";
};
&iomuxc {
/*
* The following DHCOM GPIOs are used on this board.
* Therefore, they have been removed from the list below.
* I: yellow led
*/
pinctrl-0 = <&pinctrl_dhcom_a &pinctrl_dhcom_b &pinctrl_dhcom_c
&pinctrl_dhcom_d &pinctrl_dhcom_e &pinctrl_dhcom_f
&pinctrl_dhcom_g &pinctrl_dhcom_h &pinctrl_dhcom_j
&pinctrl_dhcom_k &pinctrl_dhcom_l &pinctrl_dhcom_m
&pinctrl_dhcom_n &pinctrl_dhcom_o &pinctrl_dhcom_p
&pinctrl_dhcom_q &pinctrl_dhcom_r &pinctrl_dhcom_s
&pinctrl_dhcom_int>;
};

17
arch/arm64/boot/dts/freescale/imx8mp-evk-pcie-ep.dtso Normal file
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2024 NXP
*/
/dts-v1/;
/plugin/;
&pcie {
status = "disabled";
};
&pcie_ep {
pinctrl-0 = <&pinctrl_pcie0>;
pinctrl-names = "default";
status = "okay";
};

423
arch/arm64/boot/dts/freescale/imx8mp-iota2-lumpy.dts Normal file
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2023 Y Soft
*/
/dts-v1/;
#include "imx8mp.dtsi"
/ {
compatible = "ysoft,imx8mp-iota2-lumpy", "fsl,imx8mp";
model = "Y Soft i.MX8MPlus IOTA2 Lumpy board";
beeper {
compatible = "pwm-beeper";
pwms = <&pwm4 0 500000 0>;
};
chosen {
stdout-path = &uart2;
};
gpio_keys: gpio-keys {
compatible = "gpio-keys";
pinctrl-0 = <&pinctrl_gpio_keys>;
pinctrl-names = "default";
button-reset {
gpios = <&gpio1 7 GPIO_ACTIVE_LOW>;
label = "Factory RESET";
linux,code = <BTN_0>;
};
};
reg_usb_host: regulator-usb-host {
compatible = "regulator-fixed";
pinctrl-0 = <&pinctrl_usb_host_vbus>;
pinctrl-names = "default";
regulator-max-microvolt = <5000000>;
regulator-min-microvolt = <5000000>;
regulator-name = "usb-host";
gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
memory@40000000 {
reg = <0x0 0x40000000 0 0x80000000>,
<0x1 0x00000000 0 0x80000000>;
device_type = "memory";
};
};
&A53_0 {
cpu-supply = <&reg_arm>;
};
&A53_1 {
cpu-supply = <&reg_arm>;
};
&A53_2 {
cpu-supply = <&reg_arm>;
};
&A53_3 {
cpu-supply = <&reg_arm>;
};
&eqos {
phy-handle = <&ethphy0>;
phy-mode = "rgmii-id";
pinctrl-0 = <&pinctrl_eqos>;
pinctrl-names = "default";
status = "okay";
mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@0 {
reg = <0>;
interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
interrupt-parent = <&gpio3>;
pinctrl-0 = <&pinctrl_ethphy0>;
pinctrl-names = "default";
reset-assert-us = <1000>;
reset-deassert-us = <1000>;
reset-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>;
micrel,led-mode = <0>;
};
};
};
&fec {
fsl,magic-packet;
phy-handle = <&ethphy1>;
phy-mode = "rgmii-id";
pinctrl-0 = <&pinctrl_fec>;
pinctrl-names = "default";
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy1: ethernet-phy@0 {
reg = <0>;
interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
interrupt-parent = <&gpio3>;
pinctrl-0 = <&pinctrl_ethphy1>;
pinctrl-names = "default";
reset-assert-us = <1000>;
reset-deassert-us = <1000>;
reset-gpios = <&gpio3 20 GPIO_ACTIVE_LOW>;
micrel,led-mode = <0>;
};
};
};
&i2c1 {
clock-frequency = <400000>;
pinctrl-0 = <&pinctrl_i2c1>;
pinctrl-names = "default";
status = "okay";
pmic@25 {
compatible = "nxp,pca9450c";
reg = <0x25>;
interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
interrupt-parent = <&gpio1>;
pinctrl-0 = <&pinctrl_pmic>;
pinctrl-names = "default";
regulators {
BUCK1 {
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <1000000>;
regulator-min-microvolt = <720000>;
regulator-name = "BUCK1";
regulator-ramp-delay = <3125>;
};
reg_arm: BUCK2 {
nxp,dvs-run-voltage = <950000>;
nxp,dvs-standby-voltage = <850000>;
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <1025000>;
regulator-min-microvolt = <720000>;
regulator-name = "BUCK2";
regulator-ramp-delay = <3125>;
};
BUCK4 {
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <3600000>;
regulator-min-microvolt = <3000000>;
regulator-name = "BUCK4";
};
BUCK5 {
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <1950000>;
regulator-min-microvolt = <1650000>;
regulator-name = "BUCK5";
};
BUCK6 {
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <1155000>;
regulator-min-microvolt = <1045000>;
regulator-name = "BUCK6";
};
LDO1 {
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <1950000>;
regulator-min-microvolt = <1650000>;
regulator-name = "LDO1";
};
LDO3 {
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <1890000>;
regulator-min-microvolt = <1710000>;
regulator-name = "LDO3";
};
LDO4 {
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <950000>;
regulator-min-microvolt = <850000>;
regulator-name = "LDO4";
};
LDO5 {
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <1800000>;
regulator-name = "LDO5";
};
};
};
};
&i2c2 {
clock-frequency = <400000>;
pinctrl-0 = <&pinctrl_i2c2>;
pinctrl-names = "default";
status = "okay";
rtc: rtc@68 {
compatible = "dallas,ds1341";
reg = <0x68>;
};
};
&pwm4 {
pinctrl-0 = <&pinctrl_pwm4>;
pinctrl-names = "default";
status = "okay";
};
&uart2 {
pinctrl-0 = <&pinctrl_uart2>;
pinctrl-names = "default";
status = "okay";
};
&usb3_1 {
status = "okay";
};
&usb3_phy1 {
vbus-supply = <&reg_usb_host>;
status = "okay";
};
&usb_dwc3_1 {
dr_mode = "host";
status = "okay";
};
&usdhc3 {
assigned-clocks = <&clk IMX8MP_CLK_USDHC3>;
assigned-clock-rates = <400000000>;
pinctrl-0 = <&pinctrl_usdhc3>;
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
bus-width = <8>;
non-removable;
status = "okay";
};
&wdog1 {
pinctrl-0 = <&pinctrl_wdog>;
pinctrl-names = "default";
fsl,ext-reset-output;
status = "okay";
};
&iomuxc {
pinctrl_eqos: eqosgrp {
fsl,pins = <
MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2
MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2
MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90
MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90
MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90
MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90
MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90
MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90
MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16
MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16
MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16
MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16
MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16
MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16
>;
};
pinctrl_ethphy0: ethphy0grp {
fsl,pins = <
MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x10
MX8MP_IOMUXC_SAI5_RXD1__GPIO3_IO22 0x10
>;
};
pinctrl_ethphy1: ethphy1grp {
fsl,pins = <
MX8MP_IOMUXC_SAI5_RXFS__GPIO3_IO19 0x10
MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20 0x10
>;
};
pinctrl_fec: fecgrp {
fsl,pins = <
MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x2
MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x2
MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x90
MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x90
MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x90
MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x90
MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x90
MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x90
MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x16
MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x16
MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x16
MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x16
MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x16
MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x16
>;
};
pinctrl_gpio_keys: gpiokeysgrp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x80
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2
MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2
MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2
>;
};
pinctrl_pmic: pmicgrp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x1c0
>;
};
pinctrl_pwm4: pwm4grp {
fsl,pins = <
MX8MP_IOMUXC_SAI3_MCLK__PWM4_OUT 0x102
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x0
MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x0
>;
};
pinctrl_usb_host_vbus: usb1grp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR 0x0
>;
};
pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
fsl,pins = <
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194
>;
};
pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
fsl,pins = <
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x166
>;
};
};

305
arch/arm64/boot/dts/freescale/imx8mp-kontron-bl-osm-s.dts Normal file
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// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
* Copyright (C) 2022 Kontron Electronics GmbH
*/
/dts-v1/;
#include "imx8mp-kontron-osm-s.dtsi"
/ {
model = "Kontron BL i.MX8MP OSM-S";
compatible = "kontron,imx8mp-bl-osm-s", "kontron,imx8mp-osm-s", "fsl,imx8mp";
aliases {
ethernet0 = &fec;
ethernet1 = &eqos;
};
extcon_usbc: usbc {
compatible = "linux,extcon-usb-gpio";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb1_id>;
id-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
};
leds {
compatible = "gpio-leds";
led1 {
label = "led1";
gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
};
pwm-beeper {
compatible = "pwm-beeper";
pwms = <&pwm2 0 5000 0>;
};
reg_vcc_panel: regulator-vcc-panel {
compatible = "regulator-fixed";
gpio = <&gpio4 3 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3300000>;
regulator-name = "VCC_PANEL";
};
};
&ecspi2 {
status = "okay";
eeram@0 {
compatible = "microchip,48l640";
reg = <0>;
spi-max-frequency = <20000000>;
};
};
&eqos { /* Second ethernet (OSM-S ETH_B) */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_eqos_rgmii>;
phy-mode = "rgmii-id";
phy-handle = <&ethphy1>;
status = "okay";
mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
ethphy1: ethernet-phy@1 {
compatible = "ethernet-phy-id4f51.e91b";
reg = <1>;
pinctrl-0 = <&pinctrl_ethphy1>;
pinctrl-names = "default";
reset-assert-us = <10000>;
reset-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
};
};
};
&fec { /* First ethernet (OSM-S ETH_A) */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet_rgmii>;
phy-connection-type = "rgmii-id";
phy-handle = <&ethphy0>;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@1 {
compatible = "ethernet-phy-id4f51.e91b";
reg = <1>;
pinctrl-0 = <&pinctrl_ethphy0>;
pinctrl-names = "default";
reset-assert-us = <10000>;
reset-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
};
};
};
&flexcan1 {
status = "okay";
};
/*
* Rename SoM signals according to board usage:
* SDIO_A_PWR_EN -> CAN_ADDR2
* SDIO_A_WP -> CAN_ADDR3
*/
&gpio2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio2>;
gpio-line-names = "", "", "", "", "", "", "", "", "", "", "", "",
"SDIO_A_CD", "SDIO_A_CLK", "SDIO_A_CMD", "SDIO_A_D0",
"SDIO_A_D1", "SDIO_A_D2", "SDIO_A_D3", "CAN_ADDR2",
"CAN_ADDR3";
};
/*
* Rename SoM signals according to board usage:
* SPI_A_WP -> CAN_ADDR0
* SPI_A_HOLD -> CAN_ADDR1
* GPIO_B_0 -> DIO1_OUT
* GPIO_B_1 -> DIO2_OUT
*/
&gpio3 {
gpio-line-names = "PCIE_WAKE", "PCIE_CLKREQ", "PCIE_A_PERST", "SDIO_B_D5",
"SDIO_B_D6", "SDIO_B_D7", "CAN_ADDR0", "CAN_ADDR1",
"UART_B_RTS", "UART_B_CTS", "SDIO_B_D0", "SDIO_B_D1",
"SDIO_B_D2", "SDIO_B_D3", "SDIO_B_WP", "SDIO_B_D4",
"PCIE_SM_ALERT", "SDIO_B_CLK", "SDIO_B_CMD", "DIO1_OUT",
"DIO2_OUT", "", "BOOT_SEL0", "BOOT_SEL1",
"", "", "SDIO_B_CD", "SDIO_B_PWR_EN",
"HDMI_CEC", "HDMI_HPD";
};
/*
* Rename SoM signals according to board usage:
* GPIO_B_5 -> DIO2_IN
* GPIO_B_6 -> DIO3_IN
* GPIO_B_7 -> DIO4_IN
* GPIO_B_3 -> DIO4_OUT
* GPIO_B_4 -> DIO1_IN
* GPIO_B_2 -> DIO3_OUT
*/
&gpio4 {
gpio-line-names = "DIO2_IN", "DIO3_IN", "DIO4_IN", "GPIO_C_0",
"ETH_A_MDC", "ETH_A_MDIO", "ETH_A_RXD0", "ETH_A_RXD1",
"ETH_A_RXD2", "ETH_A_RXD3", "ETH_A_RX_DV", "ETH_A_RX_CLK",
"ETH_A_TXD0", "ETH_A_TXD1", "ETH_A_TXD2", "ETH_A_TXD3",
"ETH_A_TX_EN", "ETH_A_TX_CLK", "DIO4_OUT", "DIO1_IN",
"DIO3_OUT", "GPIO_A_6", "CAN_A_TX", "UART_A_CTS",
"UART_A_RTS", "CAN_A_RX", "CAN_B_TX", "CAN_B_RX",
"GPIO_A_7", "CARRIER_PWR_EN", "I2S_A_DATA_IN", "I2S_LRCLK";
};
&hdmi_pvi {
status = "okay";
};
&hdmi_tx {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hdmi>;
ddc-i2c-bus = <&i2c2>;
status = "okay";
};
&hdmi_tx_phy {
status = "okay";
};
&i2c1 {
status = "okay";
gpio_expander_dio: io-expander@20 {
compatible = "ti,tca6408";
reg = <0x20>;
gpio-controller;
#gpio-cells = <2>;
gpio-line-names = "DIO1_OUT","DIO1_IN", "DIO2_OUT","DIO2_IN",
"DIO3_OUT","DIO3_IN", "DIO4_OUT","DIO4_IN";
interrupt-parent = <&gpio3>;
interrupts = <19 IRQ_TYPE_EDGE_FALLING>;
reset-gpios = <&gpio3 20 GPIO_ACTIVE_LOW>;
};
};
&i2c2 {
status = "okay";
};
&i2c4 {
status = "okay";
};
&lcdif3 {
status = "okay";
};
&pwm2 {
status = "okay";
};
&reg_usdhc2_vcc {
status = "disabled";
};
&snvs_pwrkey {
status = "okay";
};
&uart1 {
uart-has-rtscts;
status = "okay";
};
&uart4 {
linux,rs485-enabled-at-boot-time;
uart-has-rtscts;
status = "okay";
};
&usb_dwc3_0 {
adp-disable;
hnp-disable;
srp-disable;
dr_mode = "otg";
extcon = <&extcon_usbc>;
usb-role-switch;
status = "okay";
};
&usb_dwc3_1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb_hub>;
#address-cells = <1>;
#size-cells = <0>;
dr_mode = "host";
status = "okay";
usb-hub@1 {
compatible = "usb424,2514";
reg = <1>;
reset-gpios = <&gpio3 14 GPIO_ACTIVE_LOW>;
};
};
&usb3_0 {
status = "okay";
};
&usb3_1 {
fsl,disable-port-power-control;
fsl,permanently-attached;
status = "okay";
};
&usb3_phy0 {
vbus-supply = <&reg_usb1_vbus>;
status = "okay";
};
&usb3_phy1 {
status = "okay";
};
&usdhc2 {
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
vmmc-supply = <&reg_vdd_3v3>;
status = "okay";
};
&iomuxc {
pinctrl_ethphy0: ethphy0grp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x46
>;
};
pinctrl_ethphy1: ethphy1grp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x46
>;
};
pinctrl_gpio2: gpio2grp {
fsl,pins = <
MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x46
MX8MP_IOMUXC_SD2_WP__GPIO2_IO20 0x46
>;
};
pinctrl_usb_hub: usbhubgrp {
fsl,pins = <
MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14 0x46
>;
};
};

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arch/arm64/boot/dts/freescale/imx8mp-kontron-dl.dtso Normal file
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// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
* Copyright (C) 2023 Kontron Electronics GmbH
*/
/dts-v1/;
/plugin/;
#include <dt-bindings/gpio/gpio.h>
#include "imx8mp-pinfunc.h"
&{/} {
model = "Kontron DL i.MX8MP OSM-S";
compatible = "kontron,imx8mp-bl-osm-s", "kontron,imx8mp-osm-s", "fsl,imx8mp";
backlight: backlight {
compatible = "pwm-backlight";
pwms = <&pwm1 0 50000 0>;
brightness-levels = <0 100>;
num-interpolated-steps = <100>;
default-brightness-level = <100>;
};
panel {
compatible = "jenson,bl-jt60050-01a", "panel-lvds";
backlight = <&backlight>;
data-mapping = "vesa-24";
enable-gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
power-supply = <&reg_vcc_panel>;
height-mm = <86>;
width-mm = <154>;
panel-timing {
clock-frequency = <50000000>;
hactive = <1024>;
hback-porch = <160>;
hfront-porch = <160>;
hsync-len = <1>;
vactive = <600>;
vback-porch = <23>;
vfront-porch = <12>;
vsync-len = <1>;
};
port {
panel_in_lvds0: endpoint {
remote-endpoint = <&ldb_lvds_ch0>;
};
};
};
};
&gpio4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio4>, <&pinctrl_panel_stby>;
panel-rst-hog {
gpio-hog;
gpios = <21 GPIO_ACTIVE_HIGH>;
output-high;
line-name = "panel-reset";
};
panel-stby-hog {
gpio-hog;
gpios = <28 GPIO_ACTIVE_HIGH>;
output-high;
line-name = "panel-standby";
};
};
&i2c1 {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
touchscreen@5d {
compatible = "goodix,gt928";
reg = <0x5d>;
interrupt-parent = <&gpio1>;
interrupts = <6 8>;
irq-gpios = <&gpio1 6 0>;
AVDD28-supply = <&reg_vcc_panel>;
VDDIO-supply = <&reg_vcc_panel>;
reset-gpios = <&gpio1 7 0>;
};
};
&lcdif2 {
status = "okay";
};
&ldb_lvds_ch0 {
remote-endpoint = <&panel_in_lvds0>;
};
&lvds_bridge {
status = "okay";
};
&pwm1 {
status = "okay";
};
&iomuxc {
pinctrl_panel_stby: panelstbygrp {
fsl,pins = <
MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x19
>;
};
};

908
arch/arm64/boot/dts/freescale/imx8mp-kontron-osm-s.dtsi Normal file
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// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
* Copyright (C) 2022 Kontron Electronics GmbH
*/
#include <dt-bindings/interrupt-controller/irq.h>
#include "imx8mp.dtsi"
/ {
model = "Kontron OSM-S i.MX8MP";
compatible = "kontron,imx8mp-osm-s", "fsl,imx8mp";
aliases {
rtc0 = &rv3028;
rtc1 = &snvs_rtc;
};
memory@40000000 {
device_type = "memory";
/*
* There are multiple SoM flavors with different DDR sizes.
* The smallest is 1GB. For larger sizes the bootloader will
* update the reg property.
*/
reg = <0x0 0x40000000 0 0x80000000>;
};
chosen {
stdout-path = &uart3;
};
reg_usb1_vbus: regulator-usb1-vbus {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_usb1_vbus>;
gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-name = "VBUS_USB_A";
};
reg_usb2_vbus: regulator-usb2-vbus {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_usb2_vbus>;
gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-name = "VBUS_USB_B";
};
reg_usdhc2_vcc: regulator-usdhc2-vcc {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_usdhc2_vcc>;
gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "VCC_SDIO_A";
};
reg_usdhc3_vcc: regulator-usdhc3-vcc {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_usdhc3_vcc>;
gpio = <&gpio3 27 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "VCC_SDIO_B";
};
reg_vdd_carrier: regulator-vdd-carrier {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_vdd_carrier>;
gpio = <&gpio3 16 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-always-on;
regulator-boot-on;
regulator-name = "VDD_CARRIER";
regulator-state-standby {
regulator-on-in-suspend;
};
regulator-state-mem {
regulator-off-in-suspend;
};
regulator-state-disk {
regulator-off-in-suspend;
};
};
};
&A53_0 {
cpu-supply = <&reg_vdd_arm>;
};
&A53_1 {
cpu-supply = <&reg_vdd_arm>;
};
&A53_2 {
cpu-supply = <&reg_vdd_arm>;
};
&A53_3 {
cpu-supply = <&reg_vdd_arm>;
};
&ecspi1 { /* OSM-S SPI_A */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
};
&ecspi2 { /* OSM-S SPI_B */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi2>;
cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
};
&flexcan1 { /* OSM-S CAN_A */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan1>;
};
&flexcan2 { /* OSM-S CAN_B */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan2>;
};
&gpio1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio1>;
gpio-line-names = "GPIO_A_0", "GPIO_A_1", "", "",
"", "GPIO_A_2", "GPIO_A_3", "GPIO_A_4",
"GPIO_A_5", "USB_B_EN", "USB_A_ID", "USB_B_ID",
"USB_A_EN", "USB_A_OC","CAM_MCK", "USB_B_OC",
"ETH_B_MDC", "ETH_B_MDIO", "ETH_B_TXD3", "ETH_B_TXD2",
"ETH_B_TXD1", "ETH_B_TXD0", "ETH_B_TX_EN", "ETH_B_TX_CLK",
"ETH_B_RX_DV", "ETH_B_RX_CLK", "ETH_B_RXD0", "ETH_B_RXD1",
"ETH_B_RXD2", "ETH_B_RXD3";
};
&gpio2 {
gpio-line-names = "", "", "", "", "", "", "", "", "", "", "", "",
"SDIO_A_CD", "SDIO_A_CLK", "SDIO_A_CMD", "SDIO_A_D0",
"SDIO_A_D1", "SDIO_A_D2", "SDIO_A_D3", "SDIO_A_PWR_EN",
"SDIO_A_WP";
};
&gpio3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio3>;
gpio-line-names = "PCIE_WAKE", "PCIE_CLKREQ", "PCIE_A_PERST", "SDIO_B_D5",
"SDIO_B_D6", "SDIO_B_D7", "SPI_A_WP", "SPI_A_HOLD",
"UART_B_RTS", "UART_B_CTS", "SDIO_B_D0", "SDIO_B_D1",
"SDIO_B_D2", "SDIO_B_D3", "SDIO_B_WP", "SDIO_B_D4",
"PCIE_SM_ALERT", "SDIO_B_CLK", "SDIO_B_CMD", "GPIO_B_0",
"GPIO_B_1", "", "BOOT_SEL0", "BOOT_SEL1",
"", "", "SDIO_B_CD", "SDIO_B_PWR_EN",
"HDMI_CEC", "HDMI_HPD";
};
&gpio4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio4>;
gpio-line-names = "GPIO_B_5", "GPIO_B_6", "GPIO_B_7", "GPIO_C_0",
"ETH_A_MDC", "ETH_A_MDIO", "ETH_A_RXD0", "ETH_A_RXD1",
"ETH_A_RXD2", "ETH_A_RXD3", "ETH_A_RX_DV", "ETH_A_RX_CLK",
"ETH_A_TXD0", "ETH_A_TXD1", "ETH_A_TXD2", "ETH_A_TXD3",
"ETH_A_TX_EN", "ETH_A_TX_CLK", "GPIO_B_3", "GPIO_B_4",
"GPIO_B_2", "GPIO_A_6", "CAN_A_TX", "UART_A_CTS",
"UART_A_RTS", "CAN_A_RX", "CAN_B_TX", "CAN_B_RX",
"GPIO_A_7", "CARRIER_PWR_EN", "I2S_A_DATA_IN", "I2S_LRCLK";
};
&gpio5 {
gpio-line-names = "I2S_BITCLK", "I2S_A_DATA_OUT", "I2S_MCLK", "PWM_2",
"PWM_1", "PWM_0", "SPI_A_SCK", "SPI_A_SDO",
"SPI_A_SDI", "SPI_A_CS0", "SPI_B_SCK", "SPI_B_SDO",
"SPI_B_SDI", "SPI_B_CS0", "I2C_A_SCL", "I2C_A_SDA",
"I2C_B_SCL", "I2C_B_SDA", "PCIE_SMCLK", "PCIE_SMDAT",
"I2C_CAM_SCL", "I2C_CAM_SDA", "UART_A_RX", "UART_A_TX",
"UART_C_RX", "UART_C_TX", "UART_CON_RX", "UART_CON_TX",
"UART_B_RX", "UART_B_TX";
};
&i2c1 { /* OSM-S I2C_A */
clock-frequency = <400000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1>;
pinctrl-1 = <&pinctrl_i2c1_gpio>;
scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
};
&i2c2 { /* OSM-S I2C_B */
clock-frequency = <400000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c2>;
pinctrl-1 = <&pinctrl_i2c2_gpio>;
scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
};
&i2c3 { /* OSM-S PCIe SMDAT/SMCLK */
clock-frequency = <400000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c3>;
pinctrl-1 = <&pinctrl_i2c3_gpio>;
scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
};
&i2c4 { /* OSM-S I2C_CAM */
clock-frequency = <400000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c4>;
pinctrl-1 = <&pinctrl_i2c4_gpio>;
scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
};
&i2c5 { /* PMIC, EEPROM, RTC */
clock-frequency = <400000>;
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c5>;
pinctrl-1 = <&pinctrl_i2c5_gpio>;
scl-gpios = <&gpio3 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio3 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay";
pca9450: pmic@25 {
compatible = "nxp,pca9450c";
reg = <0x25>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pmic>;
interrupt-parent = <&gpio1>;
interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
nxp,i2c-lt-enable;
regulators {
reg_vdd_soc: BUCK1 { /* dual phase with BUCK3 */
regulator-name = "+0V8_VDD_SOC (BUCK1)";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <950000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <3125>;
};
reg_vdd_arm: BUCK2 {
regulator-name = "+0V9_VDD_ARM (BUCK2)";
regulator-min-microvolt = <850000>;
regulator-max-microvolt = <950000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <3125>;
nxp,dvs-run-voltage = <950000>;
nxp,dvs-standby-voltage = <850000>;
};
reg_vdd_3v3: BUCK4 {
regulator-name = "+3V3 (BUCK4)";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
reg_vdd_1v8: BUCK5 {
regulator-name = "+1V8 (BUCK5)";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
reg_nvcc_dram: BUCK6 {
regulator-name = "+1V1_NVCC_DRAM (BUCK6)";
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
regulator-boot-on;
regulator-always-on;
};
reg_nvcc_snvs: LDO1 {
regulator-name = "+1V8_NVCC_SNVS (LDO1)";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
reg_vdda: LDO3 {
regulator-name = "+1V8_VDDA (LDO3)";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
reg_nvcc_sd: LDO5 {
regulator-name = "NVCC_SD (LDO5)";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
};
};
};
eeprom@50 {
compatible = "onnn,n24s64b", "atmel,24c64";
reg = <0x50>;
pagesize = <32>;
size = <8192>;
num-addresses = <1>;
};
rv3028: rtc@52 {
compatible = "microcrystal,rv3028";
reg = <0x52>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rtc>;
interrupts-extended = <&gpio3 24 IRQ_TYPE_LEVEL_LOW>;
};
};
&pwm1 { /* OSM-S PWM_0 */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm1>;
};
&pwm2 { /* OSM-S PWM_1 */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm2>;
};
&pwm3 { /* OSM-S PWM_2 */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm3>;
};
&sai3 { /* OSM-S I2S_A */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai3>;
};
&uart1 { /* OSM-S UART_A */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
};
&uart2 { /* OSM-S UART_C */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
};
&uart3 { /* OSM-S UART_CON */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
status = "okay";
};
&uart4 { /* OSM-S UART_B */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart4>;
};
&usb3_0 { /* OSM-S USB_A */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb1_oc>;
fsl,over-current-active-low;
};
&usb3_1 { /* OSM-S USB_B */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb2_oc>;
fsl,over-current-active-low;
};
&usdhc1 { /* eMMC */
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
vmmc-supply = <&reg_vdd_3v3>;
vqmmc-supply = <&reg_vdd_1v8>;
bus-width = <8>;
non-removable;
status = "okay";
};
&usdhc2 { /* OSM-S SDIO_A */
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>, <&pinctrl_usdhc2_wp>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>, <&pinctrl_usdhc2_wp>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>, <&pinctrl_usdhc2_wp>;
vmmc-supply = <&reg_usdhc2_vcc>;
vqmmc-supply = <&reg_nvcc_sd>;
cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
};
&usdhc3 { /* OSM-S SDIO_B */
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_usdhc3_gpio>;
pinctrl-1 = <&pinctrl_usdhc3_100mhz>, <&pinctrl_usdhc3_gpio>;
pinctrl-2 = <&pinctrl_usdhc3_200mhz>, <&pinctrl_usdhc3_gpio>;
vmmc-supply = <&reg_usdhc3_vcc>;
vqmmc-supply = <&reg_nvcc_sd>;
cd-gpios = <&gpio3 26 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio3 14 GPIO_ACTIVE_HIGH>;
};
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
status = "okay";
};
&iomuxc {
pinctrl_csi_mck: csimckgrp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO14__CCM_CLKO1 0x59 /* CAM_MCK */
>;
};
pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO 0x44 /* SPI_A_SDI_(IO0) */
MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI 0x44 /* SPI_A_SDO_(IO1) */
MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK 0x44 /* SPI_A_SCK */
MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 0x40 /* SPI_A_CS0# */
>;
};
pinctrl_ecspi2: ecspi2grp {
fsl,pins = <
MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x44 /* SPI_B_SDI */
MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x44 /* SPI_B_SDO */
MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x44 /* SPI_B_SCK */
MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x40 /* SPI_B_CS0# */
>;
};
pinctrl_enet_rgmii: enetrgmiigrp {
fsl,pins = <
MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3 /* ETH_MDC */
MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3 /* ETH_MDIO */
MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91 /* ETH_A_(S)(R)(G)MII_RXD0 */
MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91 /* ETH_A_(S)(R)(G)MII_RXD1 */
MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91 /* ETH_A_(R)(G)MII_RXD2 */
MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91 /* ETH_A_(R)(G)MII_RXD3 */
MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91 /* ETH_A_(R)(G)MII_RX_CLK */
MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91 /* ETH_A_(R)(G)MII_RX_DV(_ER) */
MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f /* ETH_A_(S)(R)(G)MII_TXD0 */
MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f /* ETH_A_(S)(R)(G)MII_TXD1 */
MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f /* ETH_A_(S)(R)(G)MII_TXD2 */
MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f /* ETH_A_(S)(R)(G)MII_TXD3 */
MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f /* ETH_A_(R)(G)MII_TX_CLK */
MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f /* ETH_A_(R)(G)MII_TX_EN(_ER) */
>;
};
pinctrl_eqos_rgmii: eqosrgmiigrp {
fsl,pins = <
MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3 /* ETH_B_MDC */
MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3 /* ETH_B_MDIO */
MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91 /* ETH_B_(S)(R)(G)MII_RXD0 */
MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91 /* ETH_B_(S)(R)(G)MII_RXD1 */
MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91 /* ETH_B_(R)(G)MII_RXD2 */
MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91 /* ETH_B_(R)(G)MII_RXD3 */
MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91 /* ETH_B_(R)(G)MII_RX_CLK */
MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91 /* ETH_B_(R)(G)MII_RX_DV(_ER) */
MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f /* ETH_B_(S)(R)(G)MII_TXD0 */
MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f /* ETH_B_(S)(R)(G)MII_TXD1 */
MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f /* ETH_B_(S)(R)(G)MII_TXD2 */
MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f /* ETH_B_(S)(R)(G)MII_TXD3 */
MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f /* ETH_B_(R)(G)MII_TX_CLK */
MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f /* ETH_B_(R)(G)MII_TX_EN(_ER) */
>;
};
pinctrl_flexcan1: flexcan1grp {
fsl,pins = <
MX8MP_IOMUXC_SAI2_RXC__CAN1_TX 0x154 /* CAN_A_TX */
MX8MP_IOMUXC_SAI2_TXC__CAN1_RX 0x154 /* CAN_A_RX */
>;
};
pinctrl_flexcan2: flexcan2grp {
fsl,pins = <
MX8MP_IOMUXC_SAI2_TXD0__CAN2_TX 0x154 /* CAN_B_TX */
MX8MP_IOMUXC_SAI2_MCLK__CAN2_RX 0x154 /* CAN_B_RX */
>;
};
pinctrl_gpio1: gpio1grp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x19 /* GPIO_A_0 */
MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x19 /* GPIO_A_1 */
MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05 0x19 /* GPIO_A_2 */
MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x19 /* GPIO_A_3 */
MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x19 /* GPIO_A_4 */
MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08 0x19 /* GPIO_A_5 */
>;
};
pinctrl_gpio3: gpio3grp {
fsl,pins = <
MX8MP_IOMUXC_NAND_CE0_B__GPIO3_IO01 0x19 /* GPIO_A_7 */
MX8MP_IOMUXC_SAI5_RXFS__GPIO3_IO19 0x19 /* GPIO_B_0 */
MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20 0x19 /* GPIO_B_1 */
MX8MP_IOMUXC_SAI5_RXD1__GPIO3_IO22 0x19 /* BOOT_SEL0# */
MX8MP_IOMUXC_SAI5_RXD2__GPIO3_IO23 0x19 /* BOOT_SEL1# */
>;
};
pinctrl_gpio4: gpio4grp {
fsl,pins = <
MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00 0x19 /* GPIO_B_5 */
MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x19 /* GPIO_B_6 */
MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x19 /* GPIO_B_7 */
MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x19 /* GPIO_C_0 */
MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x19 /* GPIO_B_3 */
MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x19 /* GPIO_B_4 */
MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x19 /* GPIO_B_2 */
MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 0x19 /* GPIO_A_6 */
>;
};
pinctrl_hdmi: hdmigrp {
fsl,pins = <
MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x19 /* HDMI_HPD */
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x40000084 /* I2C_A_SCL */
MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x40000084 /* I2C_A_SDA */
>;
};
pinctrl_i2c1_gpio: i2c1gpiogrp {
fsl,pins = <
MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x84 /* I2C_A_SCL */
MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x84 /* I2C_A_SDA */
>;
};
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x40000084 /* I2C_B_SCL */
MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x40000084 /* I2C_B_SDA */
>;
};
pinctrl_i2c2_gpio: i2c2gpiogrp {
fsl,pins = <
MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x84 /* I2C_B_SCL */
MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x84 /* I2C_B_SDA */
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x40000084 /* PCIe_SMCLK */
MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x40000084 /* PCIe_SMDAT */
>;
};
pinctrl_i2c3_gpio: i2c3gpiogrp {
fsl,pins = <
MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x84 /* PCIe_SMCLK */
MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x84 /* PCIe_SMDAT */
>;
};
pinctrl_i2c4: i2c4grp {
fsl,pins = <
MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x40000084 /* I2C_CAM_SCL/CSI_TX_P */
MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x40000084 /* I2C_CAM_SDA/CSI_TX_N */
>;
};
pinctrl_i2c4_gpio: i2c4gpiogrp {
fsl,pins = <
MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20 0x84 /* I2C_CAM_SCL/CSI_TX_P */
MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x84 /* I2C_CAM_SDA/CSI_TX_N */
>;
};
pinctrl_i2c5: i2c5grp {
fsl,pins = <
MX8MP_IOMUXC_SAI5_RXD0__I2C5_SCL 0x40000084
MX8MP_IOMUXC_SAI5_MCLK__I2C5_SDA 0x40000084
>;
};
pinctrl_i2c5_gpio: i2c5gpiogrp {
fsl,pins = <
MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x84
MX8MP_IOMUXC_SAI5_MCLK__GPIO3_IO25 0x84
>;
};
pinctrl_pcie: pciegrp {
fsl,pins = <
MX8MP_IOMUXC_UART4_RXD__PCIE_CLKREQ_B 0x19 /* PCIe_CLKREQ# */
MX8MP_IOMUXC_NAND_CE1_B__GPIO3_IO02 0x19 /* PCIe_A_PERST# */
MX8MP_IOMUXC_NAND_ALE__GPIO3_IO00 0x19 /* PCIe_WAKE# */
MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x19 /* PCIe_SM_ALERT */
>;
};
pinctrl_pmic: pmicgrp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x1c0
>;
};
pinctrl_pwm1: pwm1grp {
fsl,pins = <
MX8MP_IOMUXC_SPDIF_EXT_CLK__PWM1_OUT 0x6 /* PWM_0 */
>;
};
pinctrl_pwm2: pwm2grp {
fsl,pins = <
MX8MP_IOMUXC_SPDIF_RX__PWM2_OUT 0x6 /* PWM_1 */
>;
};
pinctrl_pwm3: pwm3grp {
fsl,pins = <
MX8MP_IOMUXC_SPDIF_TX__PWM3_OUT 0x6 /* PWM_2 */
>;
};
pinctrl_reg_usb1_vbus: regusb1vbusgrp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x19 /* USB_A_EN */
>;
};
pinctrl_reg_usb2_vbus: regusb2vbusgrp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09 0x19 /* USB_B_EN */
>;
};
pinctrl_reg_usdhc2_vcc: regusdhc2vccgrp {
fsl,pins = <
MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x19 /* SDIO_A_PWR_EN */
>;
};
pinctrl_reg_usdhc3_vcc: regusdhc3vccgrp {
fsl,pins = <
MX8MP_IOMUXC_HDMI_DDC_SDA__GPIO3_IO27 0x19 /* SDIO_B_PWR_EN */
>;
};
pinctrl_reg_vdd_carrier: regvddcarriergrp {
fsl,pins = <
MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x19 /* CARRIER_PWR_EN */
>;
};
pinctrl_rtc: rtcgrp {
fsl,pins = <
MX8MP_IOMUXC_SAI5_RXD3__GPIO3_IO24 0x1c0
>;
};
pinctrl_sai3: sai3grp {
fsl,pins = <
MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 0xd6 /* I2S_A_DATA_IN */
MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00 0xd6 /* I2S_A_DATA_OUT */
MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_SAI3_RX_DATA01 0xd6 /* I2S_B_DATA_IN */
MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_DATA01 0xd6 /* I2S_B_DATA_OUT */
MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI3_MCLK 0xd6 /* I2S_MCLK */
MX8MP_IOMUXC_NAND_DATA01__AUDIOMIX_SAI3_TX_SYNC 0xd6 /* I2S_LRCLK */
MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK 0xd6 /* I2S_BITCLK */
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140 /* UART_A_RX */
MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140 /* UART_A_TX */
MX8MP_IOMUXC_SAI2_RXD0__UART1_DCE_RTS 0x140 /* UART_A_CTS */
MX8MP_IOMUXC_SAI2_TXFS__UART1_DCE_CTS 0x140 /* UART_A_RTS */
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140 /* UART_C_RX */
MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140 /* UART_C_TX */
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x140 /* UART_CON_RX */
MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x140 /* UART_CON_TX */
>;
};
pinctrl_uart4: uart4grp {
fsl,pins = <
MX8MP_IOMUXC_NAND_DATA00__UART4_DCE_RX 0x140 /* UART_B_RX */
MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x140 /* UART_B_TX */
MX8MP_IOMUXC_NAND_DATA03__UART4_DCE_RTS 0x140 /* UART_B_CTS */
MX8MP_IOMUXC_NAND_DATA02__UART4_DCE_CTS 0x140 /* UART_B_RTS */
>;
};
pinctrl_usb1_id: usb1idgrp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x1c4 /* USB_A_ID */
>;
};
pinctrl_usb1_oc: usb1ocgrp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC 0x1c0 /* USB_A_OC# */
>;
};
pinctrl_usb2_id: usb2idgrp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO11__USB2_OTG_ID 0x1c4 /* USB_B_ID */
>;
};
pinctrl_usb2_oc: usb2ocgrp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO15__USB2_OTG_OC 0x1c0 /* USB_B_OC# */
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190
MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0
MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0
MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0
MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0
MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0
MX8MP_IOMUXC_SD1_DATA4__USDHC1_DATA4 0x1d0
MX8MP_IOMUXC_SD1_DATA5__USDHC1_DATA5 0x1d0
MX8MP_IOMUXC_SD1_DATA6__USDHC1_DATA6 0x1d0
MX8MP_IOMUXC_SD1_DATA7__USDHC1_DATA7 0x1d0
MX8MP_IOMUXC_SD1_RESET_B__USDHC1_RESET_B 0x141
MX8MP_IOMUXC_SD1_STROBE__USDHC1_STROBE 0x190
>;
};
pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
fsl,pins = <
MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x194
MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d4
MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d4
MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d4
MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d4
MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d4
MX8MP_IOMUXC_SD1_DATA4__USDHC1_DATA4 0x1d4
MX8MP_IOMUXC_SD1_DATA5__USDHC1_DATA5 0x1d4
MX8MP_IOMUXC_SD1_DATA6__USDHC1_DATA6 0x1d4
MX8MP_IOMUXC_SD1_DATA7__USDHC1_DATA7 0x1d4
MX8MP_IOMUXC_SD1_RESET_B__USDHC1_RESET_B 0x141
MX8MP_IOMUXC_SD1_STROBE__USDHC1_STROBE 0x194
>;
};
pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
fsl,pins = <
MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x196
MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d6
MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d6
MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d6
MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d6
MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d6
MX8MP_IOMUXC_SD1_DATA4__USDHC1_DATA4 0x1d6
MX8MP_IOMUXC_SD1_DATA5__USDHC1_DATA5 0x1d6
MX8MP_IOMUXC_SD1_DATA6__USDHC1_DATA6 0x1d6
MX8MP_IOMUXC_SD1_DATA7__USDHC1_DATA7 0x1d6
MX8MP_IOMUXC_SD1_RESET_B__USDHC1_RESET_B 0x141
MX8MP_IOMUXC_SD1_STROBE__USDHC1_STROBE 0x196
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 /* SDIO_A_CLK */
MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 /* SDIO_A_CMD */
MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 /* SDIO_A_D0 */
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 /* SDIO_A_D1 */
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 /* SDIO_A_D2 */
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 /* SDIO_A_D3 */
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x1d0
>;
};
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
fsl,pins = <
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 /* SDIO_A_CLK */
MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 /* SDIO_A_CMD */
MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 /* SDIO_A_D0 */
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 /* SDIO_A_D1 */
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 /* SDIO_A_D2 */
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 /* SDIO_A_D3 */
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x1d0
>;
};
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
fsl,pins = <
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 /* SDIO_A_CLK */
MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 /* SDIO_A_CMD */
MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 /* SDIO_A_D0 */
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 /* SDIO_A_D1 */
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 /* SDIO_A_D2 */
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 /* SDIO_A_D3 */
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x1d0
>;
};
pinctrl_usdhc2_gpio: usdhc2gpiogrp {
fsl,pins = <
MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x19 /* SDIO_A_CD# */
>;
};
pinctrl_usdhc2_wp: usdhc2wpgrp {
fsl,pins = <
MX8MP_IOMUXC_SD2_WP__USDHC2_WP 0x400000d6 /* SDIO_A_WP */
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 /* SDIO_B_CLK */
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 /* SDIO_B_CMD */
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 /* SDIO_B_D0 */
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 /* SDIO_B_D1 */
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 /* SDIO_B_D2 */
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 /* SDIO_B_D3 */
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 /* SDIO_B_D4 */
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 /* SDIO_B_D5 */
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 /* SDIO_B_D6 */
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 /* SDIO_B_D7 */
>;
};
pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
fsl,pins = <
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 /* SDIO_B_CLK */
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 /* SDIO_B_CMD */
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 /* SDIO_B_D0 */
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 /* SDIO_B_D1 */
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 /* SDIO_B_D2 */
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 /* SDIO_B_D3 */
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 /* SDIO_B_D4 */
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 /* SDIO_B_D5 */
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 /* SDIO_B_D6 */
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 /* SDIO_B_D7 */
>;
};
pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
fsl,pins = <
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 /* SDIO_B_CLK */
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 /* SDIO_B_CMD */
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 /* SDIO_B_D0 */
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 /* SDIO_B_D1 */
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 /* SDIO_B_D2 */
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 /* SDIO_B_D3 */
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 /* SDIO_B_D4 */
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 /* SDIO_B_D5 */
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 /* SDIO_B_D6 */
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 /* SDIO_B_D7 */
>;
};
pinctrl_usdhc3_gpio: usdhc3gpiogrp {
fsl,pins = <
MX8MP_IOMUXC_HDMI_DDC_SCL__GPIO3_IO26 0x19 /* SDIO_B_CD# */
MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14 0x19 /* SDIO_B_WP */
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6
>;
};
};

254
arch/arm64/boot/dts/freescale/imx8mp-kontron-smarc-eval-carrier.dts Normal file
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// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
* Copyright (C) 2024 Kontron Electronics GmbH
*/
/dts-v1/;
#include <dt-bindings/phy/phy-imx8-pcie.h>
#include "imx8mp-kontron-smarc.dtsi"
/ {
model = "Kontron SMARC Eval Carrier with i.MX8MP";
compatible = "kontron,imx8mp-smarc-eval-carrier", "kontron,imx8mp-smarc",
"kontron,imx8mp-osm-s", "fsl,imx8mp";
backlight: backlight {
compatible = "pwm-backlight";
pwms = <&pwm1 0 50000 0>;
brightness-levels = <0 100>;
num-interpolated-steps = <100>;
default-brightness-level = <100>;
enable-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>;
};
extcon_usbc: usbc {
compatible = "linux,extcon-usb-gpio";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb1_id>;
id-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
};
sound {
compatible = "simple-audio-card";
simple-audio-card,bitclock-master = <&codec_dai>;
simple-audio-card,format = "i2s";
simple-audio-card,frame-master = <&codec_dai>;
simple-audio-card,mclk-fs = <256>;
simple-audio-card,name = "imx8mp-wm8904";
simple-audio-card,routing =
"Headphone Jack", "HPOUTL",
"Headphone Jack", "HPOUTR",
"IN2L", "Line In Jack",
"IN2R", "Line In Jack",
"Headphone Jack", "MICBIAS",
"IN1L", "Headphone Jack";
simple-audio-card,widgets =
"Microphone", "Headphone Jack",
"Headphone", "Headphone Jack",
"Line", "Line In Jack";
codec_dai: simple-audio-card,codec {
clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1>;
sound-dai = <&wm8904>;
};
simple-audio-card,cpu {
sound-dai = <&sai3>;
};
};
regulator_can0: can0-regulator {
compatible = "regulator-fixed";
regulator-name = "can0_en";
gpio = <&expander_pm_out 6 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
regulator_can1: can1-regulator {
compatible = "regulator-fixed";
regulator-name = "can1_en";
gpio = <&expander_pm_out 7 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
};
&ecspi1 {
status = "okay";
};
&ecspi2 {
status = "okay";
};
&eqos {
status = "okay";
};
&fec {
status = "okay";
};
&flexcan1 {
xceiver-supply = <&regulator_can0>;
status = "okay";
};
&flexcan2 {
xceiver-supply = <&regulator_can1>;
status = "okay";
};
&hdmi_pvi {
status = "okay";
};
&hdmi_tx {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hdmi>;
ddc-i2c-bus = <&i2c3>;
status = "okay";
};
&hdmi_tx_phy {
status = "okay";
};
&i2c1 {
status = "okay";
expander_pm_out: io-expander@22 {
compatible = "nxp,pca9554";
reg = <0x22>;
gpio-controller;
#gpio-cells = <2>;
gpio-line-names = "EN_5V0_S0", "EN_3V3_S0", "EN_1V8_S0",
"EN_1V5_S0", "EN_12V0_PCIE", "EN_3V3_S5",
"CAN0_EN", "CAN1_EN";
};
expander_pm_in: io-expander@24 {
compatible = "nxp,pca9554";
reg = <0x24>;
gpio-controller;
#gpio-cells = <2>;
gpio-line-names = "PG_5V0_3V3_S0", "PG_5V0_3V3_S5", "PG_1V8_S0",
"PG_1V5_S0", "PG_BKLT_5V", "PG_BKLT_12V";
};
};
&i2c2 {
status = "okay";
wm8904: audio-codec@1a {
compatible = "wlf,wm8904";
reg = <0x1a>;
#sound-dai-cells = <0>;
clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1>;
clock-names = "mclk";
AVDD-supply = <&reg_vdd_1v8>;
CPVDD-supply = <&reg_vdd_1v8>;
DBVDD-supply = <&reg_vdd_1v8>;
DCVDD-supply = <&reg_vdd_1v8>;
MICVDD-supply = <&reg_vdd_3v3>;
};
expander_audio: io-expander@20 {
compatible = "nxp,pca9554";
reg = <0x20>;
gpio-controller;
#gpio-cells = <2>;
gpio-line-names = "I2C_SEL_CODEC_LOOPBACK", "FPAH_PRESENCE",
"CODEC_OPTION_SW_I2S_HDA", "LINE_IN_JD",
"LINE_OUT_JD", "HEADPHONES_JD", "MIC_JD";
};
};
&i2c3 {
status = "okay";
};
&i2c4 {
status = "okay";
};
&lcdif3 {
status = "okay";
};
&pcie_phy {
fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>;
fsl,clkreq-unsupported;
clocks = <&hsio_blk_ctrl>;
clock-names = "ref";
status = "okay";
};
&pcie {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie>;
reset-gpio = <&gpio3 2 GPIO_ACTIVE_LOW>;
status = "okay";
};
&pwm1 {
status = "okay";
};
&sai3 {
assigned-clocks = <&clk IMX8MP_CLK_SAI3>;
assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>;
assigned-clock-rates = <24576000>;
fsl,sai-mclk-direction-output;
status = "okay";
};
&uart1 {
uart-has-rtscts;
status = "okay";
};
&uart2 {
status = "okay";
};
&uart4 {
uart-has-rtscts;
status = "okay";
};
&usb_dwc3_0 {
adp-disable;
hnp-disable;
srp-disable;
dr_mode = "otg";
extcon = <&extcon_usbc>;
usb-role-switch;
status = "okay";
};
&usb_dwc3_1 {
status = "okay";
};
&usb3_0 {
status = "okay";
};
&usb3_1 {
status = "okay";
};
&usb3_phy0 {
vbus-supply = <&reg_usb1_vbus>;
status = "okay";
};
&usb3_phy1 {
status = "okay";
};
&usdhc2 {
vmmc-supply = <&reg_vdd_3v3>;
status = "okay";
};

280
arch/arm64/boot/dts/freescale/imx8mp-kontron-smarc.dtsi Normal file
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// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
* Copyright (C) 2024 Kontron Electronics GmbH
*/
#include <dt-bindings/gpio/gpio.h>
#include "imx8mp-kontron-osm-s.dtsi"
/ {
model = "Kontron SMARC i.MX8MP";
compatible = "kontron,imx8mp-smarc", "kontron,imx8mp-osm-s", "fsl,imx8mp";
leds {
compatible = "gpio-leds";
led1 {
label = "led1";
gpios = <&gpio4 3 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
};
};
&ecspi1 {
status = "okay";
tpm@0 {
compatible = "infineon,slb9670", "tcg,tpm_tis-spi";
reg = <0>;
spi-max-frequency = <18500000>;
};
};
&eqos { /* Second ethernet (OSM-S ETH_B) */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_eqos_rgmii>;
phy-mode = "rgmii-id";
phy-handle = <&ethphy1>;
mdio {
compatible = "snps,dwmac-mdio";
#address-cells = <1>;
#size-cells = <0>;
ethphy1: ethernet-phy@1 {
compatible = "ethernet-phy-id4f51.e91b";
reg = <1>;
pinctrl-0 = <&pinctrl_ethphy1>;
pinctrl-names = "default";
reset-assert-us = <10000>;
reset-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
};
};
};
&fec { /* First ethernet (OSM-S ETH_A) */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet_rgmii>;
phy-connection-type = "rgmii-id";
phy-handle = <&ethphy0>;
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@1 {
compatible = "ethernet-phy-id4f51.e91b";
reg = <1>;
pinctrl-0 = <&pinctrl_ethphy0>;
pinctrl-names = "default";
reset-assert-us = <10000>;
reset-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
};
};
};
/*
* Rename SoM signals according to SMARC module usage:
* GPIO_A_2 -> GPIO0
* GPIO_A_3 -> GPIO1
* GPIO_A_4 -> GPIO2
* GPIO_A_5 -> GPIO3
* USB_B_EN -> n.a.
* USB_B_ID -> n.a.
* USB_B_OC -> n.a.
*/
&gpio1 {
gpio-line-names = "GPIO_A_0", "GPIO_A_1", "", "",
"", "GPIO0", "GPIO1", "GPIO2",
"GPIO3", "", "USB_A_ID", "",
"USB_A_EN", "USB_A_OC","CAM_MCK", "",
"ETH_B_MDC", "ETH_B_MDIO", "ETH_B_TXD3", "ETH_B_TXD2",
"ETH_B_TXD1", "ETH_B_TXD0", "ETH_B_TX_EN", "ETH_B_TX_CLK",
"ETH_B_RX_DV", "ETH_B_RX_CLK", "ETH_B_RXD0", "ETH_B_RXD1",
"ETH_B_RXD2", "ETH_B_RXD3";
};
/*
* Rename SoM signals according to SMARC module usage:
* SDIO_A_CD -> SDIO_CD
* SDIO_A_CLK -> SDIO_CK
* SDIO_A_CMD -> SDIO_CMD
* SDIO_A_D0 -> SDIO_D0
* SDIO_A_D1 -> SDIO_D1
* SDIO_A_D2 -> SDIO_D2
* SDIO_A_D3 -> SDIO_D3
* SDIO_A_PWR_EN -> SDIO_PWR_EN
* SDIO_A_WP -> SDIO_WP
*/
&gpio2 {
gpio-line-names = "", "", "", "", "", "", "", "", "", "", "", "",
"SDIO_CD", "SDIO_CK", "SDIO_CMD", "SDIO_D0",
"SDIO_D1", "SDIO_D2", "SDIO_D3", "SDIO_PWR_EN",
"SDIO_WP";
};
/*
* Rename SoM signals according to SMARC module usage:
* PCIE_CLKREQ -> PCIE_A_CKREQ
* PCIE_A_PERST -> PCIE_A_RST
* SDIO_B_D5 -> n.a.
* SDIO_B_D6 -> n.a.
* SDIO_B_D7 -> n.a.
* SPI_A_WP -> n.a.
* SPI_A_HOLD -> n.a.
* UART_B_RTS -> SER2_RTS
* UART_B_CTS -> SER2_CTS
* SDIO_B_D0 -> GPIO8
* SDIO_B_D1 -> GPIO9
* SDIO_B_D2 -> GPIO10
* SDIO_B_D3 -> GPIO11
* SDIO_B_WP -> n.a.
* SDIO_B_D4 -> n.a.
* PCIE_SM_ALERT -> SMB_ALERT
* SDIO_B_CLK -> GPIO6
* SDIO_B_CMD -> GPIO7
* GPIO_B_0 -> LCD0_BKLT_EN
* GPIO_B_1 -> LCD1_BKLT_EN
* BOOT_SEL0 -> BOOT_SEL2
* SDIO_B_CD -> n.a.
* SDIO_B_PWR_EN -> n.a.
* HDMI_CEC -> n.a.
* SDIO_B_PWR_EN -> n.a.
*/
&gpio3 {
pinctrl-0 = <&pinctrl_gpio3>, <&pinctrl_gpio3_smarc>;
gpio-line-names = "PCIE_WAKE", "PCIE_A_CKREQ", "PCIE_A_RST", "",
"", "", "", "",
"SER2_RTS", "SER2_CTS", "GPIO8", "GPIO9",
"GPIO10", "GPIO11", "", "",
"SMB_ALERT", "GPIO6", "GPIO7", "LCD0_BKLT_EN",
"LCD1_BKLT_EN", "", "BOOT_SEL2", "BOOT_SEL1",
"", "", "", "",
"", "HDMI_HPD";
};
/*
* Rename SoM signals according to SMARC module usage:
* GPIO_B_5 -> n.a.
* GPIO_B_6 -> n.a.
* GPIO_B_7 -> n.a.
* GPIO_C_0 -> LED
* GPIO_B_3 -> ETH2_INT
* GPIO_B_4 -> USB_HUB_RST
* GPIO_B_2 -> ETH1_INT
* GPIO_A_6 -> GPIO4
* CAN_A_TX -> CAN0_TX
* UART_A_CTS -> SER0_CTS
* UART_A_RTS -> SER0_RTS
* CAN_A_RX -> CAN0_RX
* CAN_B_TX -> CAN1_TX
* CAN_B_RX -> CAN1_RX
* GPIO_A_7 -> TEST
* I2S_A_DATA_IN -> I2S0_SDIN
* I2S_LRCLK -> I2S0_LRCK
*/
&gpio4 {
gpio-line-names = "", "", "", "LED",
"ETH_A_MDC", "ETH_A_MDIO", "ETH_A_RXD0", "ETH_A_RXD1",
"ETH_A_RXD2", "ETH_A_RXD3", "ETH_A_RX_DV", "ETH_A_RX_CLK",
"ETH_A_TXD0", "ETH_A_TXD1", "ETH_A_TXD2", "ETH_A_TXD3",
"ETH_A_TX_EN", "ETH_A_TX_CLK", "ETH2_INT", "USB_HUB_RST",
"ETH1_INT", "GPIO4", "CAN0_TX", "SER0_CTS",
"SER0_RTS", "CAN0_RX", "CAN1_TX", "CAN1_RX",
"TEST", "CARRIER_PWR_EN", "I2S0_SDIN", "I2S0_LRCK";
};
/*
* Rename SoM signals according to SMARC module usage:
* I2S_BITCLK -> I2S0_CK
* I2S_A_DATA_OUT -> I2S0_SDOUT
* I2S_MCLK -> AUDIO_MCK
* PWM_2 -> GPIO5
* PWM_1 -> LCD1_BKLT_PWM
* PWM_0 -> LCD0_BKLT_PWM
* SPI_A_SCK -> SPI0_CK
* SPI_A_SDO -> SPI0_DO
* SPI_A_SDI -> SPI0_DIN
* SPI_A_CS0 -> SPI0_CS0
* SPI_B_SCK -> ESPI_CK
* SPI_B_SDO -> ESPI_IO_0
* SPI_B_SDI -> ESPI_IO_1
* SPI_B_CS0 -> ESPI_CS0
* I2C_A_SCL -> I2C_PM_CK
* I2C_A_SDA -> I2C_PM_DAT
* I2C_B_SCL -> I2C_GP_CK
* I2C_B_SDA -> I2C_GP_DAT
* PCIE_SMCLK -> HDMI_CTRL_CK
* PCIE_SMDAT -> HDMI_CTRL_DAT
* I2C_CAM_SCL -> I2C_CAM1_CK
* I2C_CAM_SDA -> I2C_CAM1_DAT
* UART_A_RX -> SER0_RX
* UART_A_TX -> SER0_TX
* UART_C_RX -> SER3_RX
* UART_C_TX -> SER3_TX
* UART_CON_RX -> SER1_RX
* UART_CON_TX -> SER1_TX
* UART_B_RX -> SER2_RX
* UART_B_TX -> SER2_TX
*/
&gpio5 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio5_smarc>;
gpio-line-names = "I2S0_CK", "I2S0_SDOUT", "AUDIO_MCK", "GPIO5",
"LCD1_BKLT_PWM", "LCD0_BKLT_PWM", "SPI0_CK", "SPI0_DO",
"SPI0_DIN", "SPI0_CS0", "ESPI_CK", "ESPI_IO_0",
"ESPI_IO_1", "ESPI_CS0", "I2C_PM_CK", "I2C_PM_DAT",
"I2C_GP_CK", "I2C_GP_DAT", "HDMI_CTRL_CK", "HDMI_CTRL_DAT",
"I2C_CAM1_CK", "I2C_CAM1_DAT", "SER0_RX", "SER0_TX",
"SER3_RX", "SER3_TX", "SER1_RX", "SER1_TX",
"SER2_RX", "SER2_TX";
};
&usb_dwc3_1 {
dr_mode = "host";
#address-cells = <1>;
#size-cells = <0>;
usb-hub@1 {
compatible = "usb424,2514";
reg = <1>;
reset-gpios = <&gpio4 19 GPIO_ACTIVE_LOW>;
};
};
&usb3_1 {
fsl,disable-port-power-control;
fsl,permanently-attached;
};
&iomuxc {
pinctrl_ethphy0: ethphy0grp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x46
>;
};
pinctrl_ethphy1: ethphy1grp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x46
>;
};
pinctrl_gpio3_smarc: gpio3smarcgrp {
fsl,pins = <
MX8MP_IOMUXC_NAND_DATA04__GPIO3_IO10 0x1d0 /* SMARC GPIO8 */
MX8MP_IOMUXC_NAND_DATA05__GPIO3_IO11 0x1d0 /* SMARC GPIO9 */
MX8MP_IOMUXC_NAND_DATA06__GPIO3_IO12 0x1d0 /* SMARC GPIO10 */
MX8MP_IOMUXC_NAND_DATA07__GPIO3_IO13 0x1d0 /* SMARC GPIO11 */
MX8MP_IOMUXC_NAND_WE_B__GPIO3_IO17 0x190 /* SMARC GPIO6 */
MX8MP_IOMUXC_NAND_WP_B__GPIO3_IO18 0x1d0 /* SMARC GPIO7 */
>;
};
pinctrl_gpio5_smarc: gpio5smarcgrp {
fsl,pins = <
MX8MP_IOMUXC_SPDIF_RX__GPIO5_IO04 0x1d0 /* SMARC GPIO5 */
>;
};
};

47
arch/arm64/boot/dts/freescale/imx8mp-navqp.dts
View File

@@ -18,6 +18,18 @@ chosen {
stdout-path = &uart2;
};
hdmi-connector {
compatible = "hdmi-connector";
label = "J15";
type = "d";
port {
hdmi_connector_in: endpoint {
remote-endpoint = <&hdmi_tx_out>;
};
};
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
@@ -85,6 +97,28 @@ ethphy0: ethernet-phy@0 {
};
};
&hdmi_pvi {
status = "okay";
};
&hdmi_tx {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hdmi>;
status = "okay";
ports {
port@1 {
hdmi_tx_out: endpoint {
remote-endpoint = <&hdmi_connector_in>;
};
};
};
};
&hdmi_tx_phy {
status = "okay";
};
&i2c1 {
clock-frequency = <400000>;
pinctrl-names = "default";
@@ -213,6 +247,10 @@ rtc@53 {
};
};
&lcdif3 {
status = "okay";
};
&uart2 {
/* console */
pinctrl-names = "default";
@@ -279,6 +317,15 @@ MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x19
>;
};
pinctrl_hdmi: hdmigrp {
fsl,pins = <
MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x1c2
MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA 0x1c2
MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x10
MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x10
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3

348
arch/arm64/boot/dts/freescale/imx8mp-nitrogen-smarc-som.dtsi Normal file
View File

@@ -0,0 +1,348 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2023 Boundary Devices
* Copyright 2024 Silicon Signals Pvt. Ltd.
*
* Author : Bhavin Sharma <bhavin.sharma@siliconsignals.io>
*/
/dts-v1/;
#include <dt-bindings/leds/common.h>
#include "imx8mp.dtsi"
/ {
model = "Boundary Device Nitrogen8MP SMARC SoM";
compatible = "boundary,imx8mp-nitrogen-smarc-som", "fsl,imx8mp";
chosen {
stdout-path = &uart2;
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_led>;
led-0 {
function = LED_FUNCTION_POWER;
gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
};
reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
compatible = "regulator-fixed";
regulator-name = "VSD_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
};
&A53_0 {
cpu-supply = <&buck2>;
};
&A53_1 {
cpu-supply = <&buck2>;
};
&A53_2 {
cpu-supply = <&buck2>;
};
&A53_3 {
cpu-supply = <&buck2>;
};
&i2c1 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
pmic@25 {
compatible = "nxp,pca9450c";
reg = <0x25>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pmic>;
interrupt-parent = <&gpio1>;
interrupts = <14 IRQ_TYPE_LEVEL_LOW>;
regulators {
buck1: BUCK1 {
regulator-name = "BUCK1";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <2187500>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <3125>;
};
buck2: BUCK2 {
regulator-name = "BUCK2";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <2187500>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <3125>;
nxp,dvs-run-voltage = <950000>;
nxp,dvs-standby-voltage = <850000>;
};
buck4: BUCK4 {
regulator-name = "BUCK4";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <3400000>;
regulator-boot-on;
regulator-always-on;
};
buck5: BUCK5 {
regulator-name = "BUCK5";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <3400000>;
regulator-boot-on;
regulator-always-on;
};
buck6: BUCK6 {
regulator-name = "BUCK6";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <3400000>;
regulator-boot-on;
regulator-always-on;
};
ldo1: LDO1 {
regulator-name = "LDO1";
regulator-min-microvolt = <1600000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
ldo2: LDO2 {
regulator-name = "LDO2";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1150000>;
regulator-boot-on;
regulator-always-on;
};
ldo3: LDO3 {
regulator-name = "LDO3";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
ldo4: LDO4 {
regulator-name = "LDO4";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
ldo5: LDO5 {
regulator-name = "LDO5";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
};
};
};
&i2c6 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c6>;
status = "okay";
mcp23018: gpio@20 {
compatible = "microchip,mcp23018";
gpio-controller;
#gpio-cells = <0x2>;
reg = <0x20>;
interrupts-extended = <&gpio4 22 IRQ_TYPE_LEVEL_LOW>;
interrupt-controller;
#interrupt-cells = <0x2>;
microchip,irq-mirror;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mcp23018>;
reset-gpios = <&gpio4 27 GPIO_ACTIVE_LOW>;
};
};
/* Console */
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
status = "okay";
};
/* SD-card */
&usdhc2 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
vmmc-supply = <&reg_usdhc2_vmmc>;
bus-width = <4>;
status = "okay";
};
/* eMMC */
&usdhc1 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
bus-width = <8>;
non-removable;
status = "okay";
};
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
fsl,ext-reset-output;
status = "okay";
};
&iomuxc {
pinctrl_gpio_led: gpioledgrp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x19
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3
MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3
>;
};
pinctrl_i2c6: i2c6grp {
fsl,pins = <
MX8MP_IOMUXC_SAI5_RXFS__I2C6_SCL 0x400001c3
MX8MP_IOMUXC_SAI5_RXC__I2C6_SDA 0x400001c3
>;
};
pinctrl_mcp23018: mcp23018grp {
fsl,pins = <
MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x1c0
MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x100
>;
};
pinctrl_pmic: pmicgrp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x1c0
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x40
MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x40
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x10
MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x150
MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x150
MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x150
MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x150
MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x150
MX8MP_IOMUXC_SD1_DATA4__USDHC1_DATA4 0x150
MX8MP_IOMUXC_SD1_DATA5__USDHC1_DATA5 0x150
MX8MP_IOMUXC_SD1_DATA6__USDHC1_DATA6 0x150
MX8MP_IOMUXC_SD1_DATA7__USDHC1_DATA7 0x150
MX8MP_IOMUXC_SD1_STROBE__USDHC1_STROBE 0x10
MX8MP_IOMUXC_SD1_RESET_B__USDHC1_RESET_B 0x140
>;
};
pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
fsl,pins = <
MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x14
MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x154
MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x154
MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x154
MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x154
MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x154
MX8MP_IOMUXC_SD1_DATA4__USDHC1_DATA4 0x154
MX8MP_IOMUXC_SD1_DATA5__USDHC1_DATA5 0x154
MX8MP_IOMUXC_SD1_DATA6__USDHC1_DATA6 0x154
MX8MP_IOMUXC_SD1_DATA7__USDHC1_DATA7 0x154
MX8MP_IOMUXC_SD1_STROBE__USDHC1_STROBE 0x14
>;
};
pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
fsl,pins = <
MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x12
MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x152
MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x152
MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x152
MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x152
MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x152
MX8MP_IOMUXC_SD1_DATA4__USDHC1_DATA4 0x152
MX8MP_IOMUXC_SD1_DATA5__USDHC1_DATA5 0x152
MX8MP_IOMUXC_SD1_DATA6__USDHC1_DATA6 0x152
MX8MP_IOMUXC_SD1_DATA7__USDHC1_DATA7 0x152
MX8MP_IOMUXC_SD1_STROBE__USDHC1_STROBE 0x12
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190
MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0
MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0
>;
};
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
fsl,pins = <
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194
MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4
MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4
>;
};
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
fsl,pins = <
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196
MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6
MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x140
>;
};
};

17
arch/arm64/boot/dts/freescale/imx8mp-nitrogen-smarc-universal-board.dts Normal file
View File

@@ -0,0 +1,17 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2023 Boundary Devices
* Copyright 2024 Silicon Signals Pvt. Ltd.
*
* Author : Bhavin Sharma <bhavin.sharma@siliconsignals.io>
*/
/dts-v1/;
#include "imx8mp-nitrogen-smarc-som.dtsi"
/ {
model = "Boundary Device Nitrogen8MP Universal SMARC Carrier Board";
compatible = "boundary,imx8mp-nitrogen-smarc-universal-board",
"boundary,imx8mp-nitrogen-smarc-som", "fsl,imx8mp";
};

50
arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts
View File

@@ -9,6 +9,7 @@
#include <dt-bindings/phy/phy-imx8-pcie.h>
#include <dt-bindings/leds/leds-pca9532.h>
#include <dt-bindings/pwm/pwm.h>
#include <dt-bindings/thermal/thermal.h>
#include "imx8mp-phycore-som.dtsi"
/ {
@@ -32,6 +33,16 @@ backlight_lvds: backlight {
pwms = <&pwm3 0 50000 0>;
};
fan0: fan {
compatible = "gpio-fan";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fan>;
gpio-fan,speed-map = <0 0
13000 1>;
gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>;
#cooling-cells = <2>;
};
panel1_lvds: panel-lvds {
compatible = "edt,etml1010g3dra";
backlight = <&backlight_lvds>;
@@ -111,6 +122,25 @@ reg_vcc_3v3_sw: regulator-vcc-3v3-sw {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
thermal-zones {
soc-thermal {
trips {
active1: trip2 {
temperature = <60000>;
hysteresis = <2000>;
type = "active";
};
};
cooling-maps {
map1 {
trip = <&active1>;
cooling-device = <&fan0 1 THERMAL_NO_LIMIT>;
};
};
};
};
};
/* TPM */
@@ -322,15 +352,16 @@ &usdhc2 {
&gpio1 {
gpio-line-names = "", "", "X_PMIC_WDOG_B", "",
"PMIC_SD_VSEL", "", "", "", "", "",
"", "", "USB1_OTG_PWR", "", "", "X_nETHPHY_INT";
"PMIC_SD_VSEL", "", "", "", "PCIe_nPERST", "LVDS1REG_EN",
"PCIe_nWAKE", "PCIe_nCLKREQ", "USB1_OTG_PWR", "",
"PCIe_nW_DISABLE";
};
&gpio2 {
gpio-line-names = "", "", "", "",
"", "", "", "", "", "",
"", "", "X_SD2_CD_B", "", "", "",
"", "", "", "SD2_RESET_B";
"", "", "", "SD2_RESET_B", "LVDS1_BL_EN";
};
&gpio3 {
@@ -344,7 +375,12 @@ &gpio4 {
gpio-line-names = "", "", "", "",
"", "", "", "", "", "",
"", "", "", "", "", "",
"", "", "X_PMIC_IRQ_B", "", "nENET0_INT_PWDN";
"", "", "X_PMIC_IRQ_B", "nRTC_INT", "nENET0_INT_PWDN";
};
&gpio5 {
gpio-line-names = "", "", "", "",
"", "", "", "", "", "X_ECSPI1_SSO";
};
&iomuxc {
@@ -377,6 +413,12 @@ MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x10
>;
};
pinctrl_fan: fan0grp {
fsl,pins = <
MX8MP_IOMUXC_SPDIF_RX__GPIO5_IO04 0x16
>;
};
pinctrl_flexcan1: flexcan1grp {
fsl,pins = <
MX8MP_IOMUXC_SAI5_RXD2__CAN1_RX 0x154

4
arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi
View File

@@ -209,9 +209,7 @@ &wdog1 {
};
&gpio1 {
gpio-line-names = "", "", "X_PMIC_WDOG_B", "",
"", "", "", "", "", "",
"", "", "", "", "", "X_nETHPHY_INT";
gpio-line-names = "", "", "X_PMIC_WDOG_B";
};
&gpio4 {

4
arch/arm64/boot/dts/freescale/imx8mp-venice-gw702x.dtsi
View File

@@ -11,6 +11,8 @@
/ {
aliases {
ethernet0 = &eqos;
rtc0 = &gsc_rtc;
rtc1 = &snvs_rtc;
};
memory@40000000 {
@@ -280,7 +282,7 @@ eeprom@53 {
pagesize = <16>;
};
rtc@68 {
gsc_rtc: rtc@68 {
compatible = "dallas,ds1672";
reg = <0x68>;
};

7
arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts
View File

@@ -25,6 +25,8 @@ aliases {
ethernet4 = &lan3;
ethernet5 = &lan4;
ethernet6 = &lan5;
rtc0 = &gsc_rtc;
rtc1 = &snvs_rtc;
};
chosen {
@@ -299,7 +301,7 @@ &gpio2 {
&gpio3 {
gpio-line-names =
"", "", "", "", "", "", "m2_rst", "",
"", "", "", "", "", "", "", "",
"", "", "", "", "", "", "m2_gpio10", "",
"", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "";
};
@@ -481,7 +483,7 @@ eeprom@53 {
pagesize = <16>;
};
rtc@68 {
gsc_rtc: rtc@68 {
compatible = "dallas,ds1672";
reg = <0x68>;
};
@@ -816,6 +818,7 @@ MX8MP_IOMUXC_SD2_CLK__GPIO2_IO13 0x40000150 /* PCIE1_WDIS# */
MX8MP_IOMUXC_SD2_CMD__GPIO2_IO14 0x40000150 /* PCIE3_WDIS# */
MX8MP_IOMUXC_SD2_DATA3__GPIO2_IO18 0x40000150 /* PCIE2_WDIS# */
MX8MP_IOMUXC_NAND_DATA00__GPIO3_IO06 0x40000040 /* M2SKT_RST# */
MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14 0x40000040 /* M2SKT_GPIO10 */
MX8MP_IOMUXC_SAI3_TXD__GPIO5_IO01 0x40000104 /* UART_TERM */
MX8MP_IOMUXC_SAI3_TXFS__GPIO4_IO31 0x40000104 /* UART_RS485 */
MX8MP_IOMUXC_SAI3_TXC__GPIO5_IO00 0x40000104 /* UART_HALF */

16
arch/arm64/boot/dts/freescale/imx8mp-venice-gw75xx.dtsi
View File

@@ -104,6 +104,16 @@ &i2c2 {
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
accelerometer@19 {
compatible = "st,lis2de12";
reg = <0x19>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_accel>;
interrupt-parent = <&gpio5>;
interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
st,drdy-int-pin = <1>;
};
eeprom@52 {
compatible = "atmel,24c32";
reg = <0x52>;
@@ -204,6 +214,12 @@ MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x40000106 /* PCI_WDIS# */
>;
};
pinctrl_accel: accelgrp {
fsl,pins = <
MX8MP_IOMUXC_ECSPI1_MISO__GPIO5_IO08 0x159
>;
};
pinctrl_gpio_leds: gpioledgrp {
fsl,pins = <
MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x6 /* LEDG */

19
arch/arm64/boot/dts/freescale/imx8mp-venice-gw82xx-2x.dts Normal file
View File

@@ -0,0 +1,19 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2024 Gateworks Corporation
*/
/dts-v1/;
#include "imx8mp.dtsi"
#include "imx8mp-venice-gw702x.dtsi"
#include "imx8mp-venice-gw82xx.dtsi"
/ {
model = "Gateworks Venice GW82xx-2x i.MX8MP Development Kit";
compatible = "gateworks,imx8mp-gw82xx-2x", "fsl,imx8mp";
chosen {
stdout-path = &uart2;
};
};

533
arch/arm64/boot/dts/freescale/imx8mp-venice-gw82xx.dtsi Normal file
View File

@@ -0,0 +1,533 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2024 Gateworks Corporation
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/phy/phy-imx8-pcie.h>
/ {
aliases {
ethernet1 = &eth1;
fsa1 = &fsa0;
fsa2 = &fsa1;
};
led-controller {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_leds>;
led-0 {
function = LED_FUNCTION_STATUS;
color = <LED_COLOR_ID_GREEN>;
gpios = <&gpio4 1 GPIO_ACTIVE_HIGH>;
default-state = "on";
linux,default-trigger = "heartbeat";
};
led-1 {
function = LED_FUNCTION_STATUS;
color = <LED_COLOR_ID_RED>;
gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>;
default-state = "off";
};
};
pcie0_refclk: clock-pcie0 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <100000000>;
};
pps {
compatible = "pps-gpio";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pps>;
gpios = <&gpio4 3 GPIO_ACTIVE_HIGH>;
};
reg_usb2_vbus: regulator-usb2 {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_usb2_en>;
regulator-name = "usb2_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio4 12 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2_vmmc>;
regulator-name = "VDD_3V3_SD";
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3300000>;
gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
enable-active-high;
off-on-delay-us = <12000>;
startup-delay-us = <100>;
};
};
&ecspi2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi2>;
cs-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>, /* CS0 onboard TPM */
<&gpio5 13 GPIO_ACTIVE_LOW>, /* CS1 off-board J32 SPI */
<&gpio1 12 GPIO_ACTIVE_LOW>, /* CS3 off-board J52 FSA1 */
<&gpio4 26 GPIO_ACTIVE_LOW>; /* CS2 off-board J51 FSA2 */
status = "okay";
tpm@0 {
compatible = "atmel,attpm20p", "tcg,tpm_tis-spi";
reg = <0x0>;
spi-max-frequency = <10000000>;
};
};
&flexcan1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_can1>;
status = "okay";
};
&flexcan2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_can2>;
status = "okay";
};
&gpio1 {
gpio-line-names =
"", "", "", "",
"", "", "", "",
"", "", "", "",
"", "fsa2_gpio1", "", "",
"", "", "", "",
"", "", "", "",
"", "", "", "",
"", "", "", "";
};
&gpio4 {
gpio-line-names =
"", "", "", "",
"", "", "", "",
"dio1", "fsa1_gpio2", "", "dio0",
"", "", "", "",
"", "", "", "",
"", "", "rs485_en", "rs485_term",
"fsa2_gpio2", "fsa1_gpio1", "", "rs485_half",
"", "", "", "";
};
&i2c2 {
accelerometer@19 {
compatible = "st,lis2de12";
reg = <0x19>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_accel>;
interrupt-parent = <&gpio4>;
interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
st,drdy-int-pin = <1>;
};
magnetometer@1e {
compatible = "st,lis2mdl";
reg = <0x1e>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mag>;
interrupt-parent = <&gpio4>;
interrupts = <28 IRQ_TYPE_LEVEL_LOW>;
};
};
&i2c3 {
i2c-mux@70 {
compatible = "nxp,pca9548";
reg = <0x70>;
#address-cells = <1>;
#size-cells = <0>;
/* J30 */
fsa1: i2c@0 {
reg = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fsa2i2c>;
#address-cells = <1>;
#size-cells = <0>;
gpio@20 {
compatible = "nxp,pca9555";
reg = <0x20>;
interrupt-parent = <&gpio4>;
interrupts = <4 IRQ_TYPE_EDGE_FALLING>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-controller;
#gpio-cells = <2>;
};
eeprom@54 {
compatible = "atmel,24c02";
reg = <0x54>;
pagesize = <16>;
};
eeprom@55 {
compatible = "atmel,24c02";
reg = <0x55>;
pagesize = <16>;
};
};
/* J29 */
fsa0: i2c@1 {
reg = <1>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fsa1i2c>;
#address-cells = <1>;
#size-cells = <0>;
gpio@20 {
compatible = "nxp,pca9555";
reg = <0x20>;
interrupt-parent = <&gpio4>;
interrupts = <14 IRQ_TYPE_EDGE_FALLING>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-controller;
#gpio-cells = <2>;
};
eeprom@54 {
compatible = "atmel,24c02";
reg = <0x54>;
pagesize = <16>;
};
eeprom@55 {
compatible = "atmel,24c02";
reg = <0x55>;
pagesize = <16>;
};
};
/* J33 */
i2c@2 {
reg = <2>;
#address-cells = <1>;
#size-cells = <0>;
};
};
};
&pcie_phy {
clocks = <&pcie0_refclk>;
clock-names = "ref";
fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
fsl,clkreq-unsupported;
status = "okay";
};
&pcie {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie0>;
reset-gpio = <&gpio4 29 GPIO_ACTIVE_LOW>;
status = "okay";
pcie@0,0 {
reg = <0x0000 0 0 0 0>;
device_type = "pci";
#address-cells = <3>;
#size-cells = <2>;
ranges;
pcie@0,0 {
reg = <0x0000 0 0 0 0>;
device_type = "pci";
#address-cells = <3>;
#size-cells = <2>;
ranges;
pcie@7,0 {
reg = <0x3800 0 0 0 0>;
device_type = "pci";
#address-cells = <3>;
#size-cells = <2>;
ranges;
eth1: ethernet@0,0 {
reg = <0x0000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
local-mac-address = [00 00 00 00 00 00];
};
};
};
};
};
/* GPS */
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
/* RS232 */
&uart4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart4>;
status = "okay";
};
/* USB1 - FSA1 */
&usb3_0 {
fsl,permanently-attached;
fsl,disable-port-power-control;
status = "okay";
};
&usb3_phy0 {
status = "okay";
};
&usb_dwc3_0 {
dr_mode = "host";
status = "okay";
};
/* USB2 - USB3.0 Hub */
&usb3_1 {
fsl,permanently-attached;
fsl,disable-port-power-control;
status = "okay";
};
&usb3_phy1 {
vbus-supply = <&reg_usb2_vbus>;
status = "okay";
};
&usb_dwc3_1 {
dr_mode = "host";
status = "okay";
};
/* SDIO 1.8V */
&usdhc1 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
bus-width = <4>;
non-removable;
status = "okay";
};
/* microSD */
&usdhc2 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
cd-gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>; /* CD is active high */
bus-width = <4>;
vmmc-supply = <&reg_usdhc2_vmmc>;
status = "okay";
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
pinctrl_hog: hoggrp {
fsl,pins = <
MX8MP_IOMUXC_SAI1_RXD6__GPIO4_IO08 0x40000146 /* DIO1 */
MX8MP_IOMUXC_SAI1_TXC__GPIO4_IO11 0x40000146 /* DIO0 */
MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x40000106 /* RS485_HALF */
MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x40000106 /* RS485_EN */
MX8MP_IOMUXC_SAI2_RXD0__GPIO4_IO23 0x40000106 /* RS485_TERM */
>;
};
pinctrl_accel: accelgrp {
fsl,pins = <
MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 0x150 /* IRQ# */
>;
};
pinctrl_can1: can1grp {
fsl,pins = <
MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x154
MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154
>;
};
pinctrl_can2: can2grp {
fsl,pins = <
MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x154
MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x154
>;
};
pinctrl_gpio_leds: gpioledgrp {
fsl,pins = <
MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x6 /* LEDG */
MX8MP_IOMUXC_SAI1_RXD3__GPIO4_IO05 0x6 /* LEDR */
>;
};
pinctrl_fsa1i2c: fsa1i2cgrp {
fsl,pins = <
MX8MP_IOMUXC_SAI1_TXD2__GPIO4_IO14 0x1d0 /* FSA1_ALERT# */
MX8MP_IOMUXC_SAI2_TXC__GPIO4_IO25 0x400001d0 /* FSA1_GPIO1 */
MX8MP_IOMUXC_SAI1_RXD7__GPIO4_IO09 0x400001d0 /* FSA1_GPIO2 */
>;
};
pinctrl_fsa2i2c: fsa2i2cgrp {
fsl,pins = <
MX8MP_IOMUXC_SAI1_RXD2__GPIO4_IO04 0x1d0 /* FSA2_ALERT# */
MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x400001d0 /* FSA2_GPIO1 */
MX8MP_IOMUXC_SAI2_TXFS__GPIO4_IO24 0x400001d0 /* FSA2_GPIO2 */
>;
};
pinctrl_mag: maggrp {
fsl,pins = <
MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x140 /* IRQ# */
>;
};
pinctrl_pcie0: pcie0grp {
fsl,pins = <
MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x106 /* PERST# */
>;
};
pinctrl_pps: ppsgrp {
fsl,pins = <
MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x146
>;
};
pinctrl_reg_usb2_en: regusb2grp {
fsl,pins = <
MX8MP_IOMUXC_SAI1_TXD0__GPIO4_IO12 0x146 /* USBHUB_RST# */
>;
};
pinctrl_spi2: spi2grp {
fsl,pins = <
MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0xd0
MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0xd0
MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0xd0
MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x140 /* J32_CS */
MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x140 /* TPM_CS */
MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x140 /* FSA1_CS */
MX8MP_IOMUXC_SAI2_TXD0__GPIO4_IO26 0x140 /* FSA2_CS */
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140
MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140
>;
};
pinctrl_uart4: uart4grp {
fsl,pins = <
MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x140
MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x140
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190
MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0
MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0
MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0
MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0
MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0
>;
};
pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
fsl,pins = <
MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x194
MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d4
MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d4
MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d4
MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d4
MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d4
>;
};
pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
fsl,pins = <
MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x196
MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d6
MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d6
MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d6
MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d6
MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d6
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190
MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0
MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
>;
};
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
fsl,pins = <
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194
MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4
MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
>;
};
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
fsl,pins = <
MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196
MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6
MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
>;
};
pinctrl_usdhc2_vmmc: usdhc2-vmmc-grp {
fsl,pins = <
MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x1d0
>;
};
pinctrl_usdhc2_gpio: usdhc2gpiogrp {
fsl,pins = <
MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4
>;
};
};

512
arch/arm64/boot/dts/freescale/imx8mp-verdin-ivy.dtsi Normal file
View File

@@ -0,0 +1,512 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright 2024 Toradex
*
* Common dtsi for Verdin IMX8MP SoM on Ivy carrier board
*
* https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx-8m-plus
* https://www.toradex.com/products/carrier-board/ivy-carrier-board
*/
#include <dt-bindings/mux/mux.h>
#include <dt-bindings/leds/common.h>
#include <dt-bindings/net/ti-dp83867.h>
/ {
/* AIN1 Voltage w/o AIN1_MODE gpio control */
ain1_voltage_unmanaged: voltage-divider-ain1 {
compatible = "voltage-divider";
#io-channel-cells = <1>;
io-channels = <&ivy_adc1 0>;
full-ohms = <19>;
output-ohms = <1>;
};
/* AIN1 Current w/o AIN1_MODE gpio control */
ain1_current_unmanaged: current-sense-shunt-ain1 {
compatible = "current-sense-shunt";
#io-channel-cells = <0>;
io-channels = <&ivy_adc1 1>;
shunt-resistor-micro-ohms = <100000000>;
};
/* AIN1_MODE - SODIMM 216 */
ain1_mode_mux_ctrl: mux-controller-0 {
compatible = "gpio-mux";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio5>;
#mux-control-cells = <0>;
mux-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
};
ain1-voltage {
compatible = "io-channel-mux";
channels = "ain1_voltage", "";
io-channels = <&ain1_voltage_unmanaged 0>;
io-channel-names = "parent";
mux-controls = <&ain1_mode_mux_ctrl>;
settle-time-us = <1000>;
};
ain1-current {
compatible = "io-channel-mux";
channels = "", "ain1_current";
io-channels = <&ain1_current_unmanaged>;
io-channel-names = "parent";
mux-controls = <&ain1_mode_mux_ctrl>;
settle-time-us = <1000>;
};
/* AIN2 Voltage w/o AIN2_MODE gpio control */
ain2_voltage_unmanaged: voltage-divider-ain2 {
compatible = "voltage-divider";
#io-channel-cells = <1>;
io-channels = <&ivy_adc2 0>;
full-ohms = <19>;
output-ohms = <1>;
};
/* AIN2 Current w/o AIN2_MODE gpio control */
ain2_current_unmanaged: current-sense-shunt-ain2 {
compatible = "current-sense-shunt";
#io-channel-cells = <0>;
io-channels = <&ivy_adc2 1>;
shunt-resistor-micro-ohms = <100000000>;
};
/* AIN2_MODE - SODIMM 218 */
ain2_mode_mux_ctrl: mux-controller-1 {
compatible = "gpio-mux";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio6>;
#mux-control-cells = <0>;
mux-gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
};
ain2-voltage {
compatible = "io-channel-mux";
channels = "ain2_voltage", "";
io-channels = <&ain2_voltage_unmanaged 0>;
io-channel-names = "parent";
mux-controls = <&ain2_mode_mux_ctrl>;
settle-time-us = <1000>;
};
ain2-current {
compatible = "io-channel-mux";
channels = "", "ain2_current";
io-channels = <&ain2_current_unmanaged>;
io-channel-names = "parent";
mux-controls = <&ain2_mode_mux_ctrl>;
settle-time-us = <1000>;
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ivy_leds>;
/* D7 Blue - SODIMM 30 - LEDs.GPIO1 */
led-0 {
color = <LED_COLOR_ID_BLUE>;
default-state = "off";
function = LED_FUNCTION_STATUS;
function-enumerator = <1>;
gpios = <&gpio3 25 GPIO_ACTIVE_HIGH>;
};
/* D7 Green - SODIMM 32 - LEDs.GPIO2 */
led-1 {
color = <LED_COLOR_ID_GREEN>;
default-state = "off";
function = LED_FUNCTION_STATUS;
function-enumerator = <1>;
gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>;
};
/* D7 Red - SODIMM 34 - LEDs.GPIO3 */
led-2 {
color = <LED_COLOR_ID_RED>;
default-state = "off";
function = LED_FUNCTION_STATUS;
function-enumerator = <1>;
gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>;
};
/* D8 Blue - SODIMM 36 - LEDs.GPIO4 */
led-3 {
color = <LED_COLOR_ID_BLUE>;
default-state = "off";
function = LED_FUNCTION_STATUS;
function-enumerator = <2>;
gpios = <&gpio4 2 GPIO_ACTIVE_HIGH>;
};
/* D8 Green - SODIMM 54 - LEDs.GPIO5 */
led-4 {
color = <LED_COLOR_ID_GREEN>;
default-state = "off";
function = LED_FUNCTION_STATUS;
function-enumerator = <2>;
gpios = <&gpio3 1 GPIO_ACTIVE_HIGH>;
};
/* D8 Red - SODIMM 44 - LEDs.GPIO6 */
led-5 {
color = <LED_COLOR_ID_RED>;
default-state = "off";
function = LED_FUNCTION_STATUS;
function-enumerator = <2>;
gpios = <&gpio4 31 GPIO_ACTIVE_HIGH>;
};
/* D9 Blue - SODIMM 46 - LEDs.GPIO7 */
led-6 {
color = <LED_COLOR_ID_BLUE>;
default-state = "off";
function = LED_FUNCTION_STATUS;
function-enumerator = <3>;
gpios = <&gpio5 01 GPIO_ACTIVE_HIGH>;
};
/* D9 Red - SODIMM 48 - LEDs.GPIO8 */
led-7 {
color = <LED_COLOR_ID_RED>;
default-state = "off";
function = LED_FUNCTION_STATUS;
function-enumerator = <3>;
gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>;
};
};
reg_3v2_ain1: regulator-3v2-ain1 {
compatible = "regulator-fixed";
regulator-max-microvolt = <3200000>;
regulator-min-microvolt = <3200000>;
regulator-name = "+3V2_AIN1";
};
reg_3v2_ain2: regulator-3v2-ain2 {
compatible = "regulator-fixed";
regulator-max-microvolt = <3200000>;
regulator-min-microvolt = <3200000>;
regulator-name = "+3V2_AIN2";
};
/* Ivy Power Supply Input Voltage */
ivy-input-voltage {
compatible = "voltage-divider";
/* Verdin ADC_1 */
io-channels = <&verdin_som_adc 7>;
full-ohms = <204700>; /* 200k + 4.7k */
output-ohms = <4700>;
};
ivy-5v-voltage {
compatible = "voltage-divider";
/* Verdin ADC_2 */
io-channels = <&verdin_som_adc 6>;
full-ohms = <39000>; /* 27k + 12k */
output-ohms = <12000>;
};
ivy-3v3-voltage {
compatible = "voltage-divider";
/* Verdin ADC_3 */
io-channels = <&verdin_som_adc 5>;
full-ohms = <54000>; /* 27k + 27k */
output-ohms = <27000>;
};
ivy-1v8-voltage {
compatible = "voltage-divider";
/* Verdin ADC_4 */
io-channels = <&verdin_som_adc 4>;
full-ohms = <39000>; /* 12k + 27k */
output-ohms = <27000>;
};
};
/* Verdin SPI_1 */
&ecspi1 {
pinctrl-0 = <&pinctrl_ecspi1>,
<&pinctrl_gpio1>,
<&pinctrl_gpio4>;
cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>,
<&gpio1 0 GPIO_ACTIVE_LOW>,
<&gpio1 6 GPIO_ACTIVE_LOW>;
status = "okay";
tpm@1 {
compatible = "infineon,slb9670", "tcg,tpm_tis-spi";
reg = <1>;
spi-max-frequency = <18500000>;
};
fram@2 {
compatible = "fujitsu,mb85rs256", "atmel,at25";
reg = <2>;
address-width = <16>;
size = <32768>;
spi-max-frequency = <33000000>;
pagesize = <1>;
};
};
/* EEPROM on Ivy */
&eeprom_carrier_board {
status = "okay";
};
/* Verdin ETH_1 */
&eqos {
status = "okay";
};
/* Verdin ETH_2 */
&fec {
phy-handle = <&ethphy2>;
phy-mode = "rgmii-id";
status = "okay";
};
&verdin_eth2_mdio {
ethphy2: ethernet-phy@2 {
reg = <2>;
interrupt-parent = <&gpio4>;
interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
};
};
/* Verdin CAN_1 */
&flexcan1 {
status = "okay";
};
/* Verdin CAN_2 */
&flexcan2 {
status = "okay";
};
&gpio1 {
gpio-line-names =
"", /* 0 */
"GPIO2", /* Verdin GPIO_2 - SODIMM 208 */
"",
"",
"",
"GPIO3", /* Verdin GPIO_3 - SODIMM 210 */
"",
"",
"",
"",
"",
"", /* 10 */
"",
"",
"",
"",
"",
"",
"",
"",
"",
"", /* 20 */
"",
"",
"",
"",
"",
"",
"",
"",
"";
};
&gpio3 {
gpio-line-names =
"", /* 0 */
"",
"",
"",
"",
"",
"DIG_1", /* SODIMM 56 */
"DIG_2", /* SODIMM 58 */
"REL1", /* SODIMM 60 */
"REL2", /* SODIMM 62 */
"", /* 10 */
"",
"",
"",
"REL4", /* SODIMM 66 */
"",
"REL3", /* SODIMM 64 */
"",
"",
"",
"", /* 20 */
"",
"",
"",
"",
"",
"",
"",
"",
"";
};
/* Temperature sensor on Ivy */
&hwmon_temp {
compatible = "ti,tmp1075";
status = "okay";
};
/* Verdin I2C_4 CSI */
&i2c3 {
status = "okay";
ivy_adc1: adc@40 {
compatible = "ti,ads1119";
reg = <0x40>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio7>;
interrupt-parent = <&gpio4>;
interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
avdd-supply = <&reg_3v2_ain1>;
dvdd-supply = <&reg_3v2_ain1>;
vref-supply = <&reg_3v2_ain1>;
#address-cells = <1>;
#io-channel-cells = <1>;
#size-cells = <0>;
/* AIN1 0-33V Voltage Input */
channel@0 {
reg = <0>;
diff-channels = <0 1>;
};
/* AIN1 0-20mA Current Input */
channel@1 {
reg = <1>;
diff-channels = <2 3>;
};
};
ivy_adc2: adc@41 {
compatible = "ti,ads1119";
reg = <0x41>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio8>;
interrupt-parent = <&gpio4>;
interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
avdd-supply = <&reg_3v2_ain2>;
dvdd-supply = <&reg_3v2_ain2>;
vref-supply = <&reg_3v2_ain2>;
#address-cells = <1>;
#io-channel-cells = <1>;
#size-cells = <0>;
/* AIN2 0-33V Voltage Input */
channel@0 {
reg = <0>;
diff-channels = <0 1>;
};
/* AIN2 0-20mA Current Input */
channel@1 {
reg = <1>;
diff-channels = <2 3>;
};
};
};
/* Verdin I2C_1 */
&i2c4 {
status = "okay";
};
/* Verdin PCIE_1 */
&pcie {
status = "okay";
};
&pcie_phy {
status = "okay";
};
/* Verdin UART_1 */
&uart1 {
status = "okay";
};
/* Verdin UART_2 */
&uart2 {
linux,rs485-enabled-at-boot-time;
rs485-rx-during-tx;
status = "okay";
};
/* Verdin UART_3 */
&uart3 {
status = "okay";
};
/* Verdin USB_1 */
&usb3_0 {
status = "okay";
};
&usb3_phy0 {
status = "okay";
};
/* Verdin USB_2 */
&usb3_1 {
status = "okay";
};
&usb3_phy1 {
status = "okay";
};
/* Verdin SD_1 */
&usdhc2 {
status = "okay";
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio2>, <&pinctrl_gpio3>,
<&pinctrl_ivy_dig_inputs>, <&pinctrl_ivy_relays>;
pinctrl_ivy_dig_inputs: ivydiginputsgrp {
fsl,pins =
<MX8MP_IOMUXC_NAND_DATA00__GPIO3_IO06 0x96>, /* SODIMM 56 */
<MX8MP_IOMUXC_NAND_DATA01__GPIO3_IO07 0x96>; /* SODIMM 58 */
};
pinctrl_ivy_leds: ivyledsgrp {
fsl,pins =
<MX8MP_IOMUXC_SAI5_MCLK__GPIO3_IO25 0x16>, /* SODIMM 30 */
<MX8MP_IOMUXC_SAI5_RXD1__GPIO3_IO22 0x16>, /* SODIMM 32 */
<MX8MP_IOMUXC_SAI5_RXFS__GPIO3_IO19 0x16>, /* SODIMM 34 */
<MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x16>, /* SODIMM 36 */
<MX8MP_IOMUXC_SAI3_TXFS__GPIO4_IO31 0x16>, /* SODIMM 44 */
<MX8MP_IOMUXC_SAI3_TXD__GPIO5_IO01 0x16>, /* SODIMM 46 */
<MX8MP_IOMUXC_SAI3_RXD__GPIO4_IO30 0x16>, /* SODIMM 48 */
<MX8MP_IOMUXC_NAND_CE0_B__GPIO3_IO01 0x16>; /* SODIMM 54 */
};
pinctrl_ivy_relays: ivyrelaysgrp {
fsl,pins =
<MX8MP_IOMUXC_NAND_DATA02__GPIO3_IO08 0x16>, /* SODIMM 60 */
<MX8MP_IOMUXC_NAND_DATA03__GPIO3_IO09 0x16>, /* SODIMM 62 */
<MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x16>, /* SODIMM 64 */
<MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14 0x16>; /* SODIMM 66 */
};
};

18
arch/arm64/boot/dts/freescale/imx8mp-verdin-nonwifi-ivy.dts Normal file
View File

@@ -0,0 +1,18 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright 2024 Toradex
*/
/dts-v1/;
#include "imx8mp-verdin.dtsi"
#include "imx8mp-verdin-nonwifi.dtsi"
#include "imx8mp-verdin-ivy.dtsi"
/ {
model = "Toradex Verdin iMX8M Plus on Ivy";
compatible = "toradex,verdin-imx8mp-nonwifi-ivy",
"toradex,verdin-imx8mp-nonwifi",
"toradex,verdin-imx8mp",
"fsl,imx8mp";
};

18
arch/arm64/boot/dts/freescale/imx8mp-verdin-wifi-ivy.dts Normal file
View File

@@ -0,0 +1,18 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright 2024 Toradex
*/
/dts-v1/;
#include "imx8mp-verdin.dtsi"
#include "imx8mp-verdin-wifi.dtsi"
#include "imx8mp-verdin-ivy.dtsi"
/ {
model = "Toradex Verdin iMX8M Plus WB on Ivy";
compatible = "toradex,verdin-imx8mp-wifi-ivy",
"toradex,verdin-imx8mp-wifi",
"toradex,verdin-imx8mp",
"fsl,imx8mp";
};

12
arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi
View File

@@ -175,7 +175,7 @@ reg_usdhc2_vmmc: regulator-usdhc2 {
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3300000>;
regulator-name = "+V3.3_SD";
startup-delay-us = <2000>;
startup-delay-us = <20000>;
};
reserved-memory {
@@ -320,7 +320,7 @@ &fec {
pinctrl-0 = <&pinctrl_fec>;
pinctrl-1 = <&pinctrl_fec_sleep>;
mdio {
verdin_eth2_mdio: mdio {
#address-cells = <1>;
#size-cells = <0>;
@@ -478,6 +478,7 @@ &i2c1 {
pinctrl-1 = <&pinctrl_i2c1_gpio>;
scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
single-master;
status = "okay";
pca9450: pmic@25 {
@@ -591,11 +592,12 @@ hwmon_temp_module: sensor@48 {
vs-supply = <&reg_vdd_1v8>;
};
adc@49 {
verdin_som_adc: adc@49 {
compatible = "ti,ads1015";
reg = <0x49>;
#address-cells = <1>;
#size-cells = <0>;
#io-channel-cells = <1>;
/* Verdin I2C_1 (ADC_4 - ADC_3) */
channel@0 {
@@ -669,6 +671,7 @@ &i2c2 {
pinctrl-1 = <&pinctrl_i2c2_gpio>;
scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
single-master;
atmel_mxt_ts_mezzanine: touch-mezzanine@4a {
compatible = "atmel,maxtouch";
@@ -690,6 +693,7 @@ &i2c3 {
pinctrl-1 = <&pinctrl_i2c3_gpio>;
scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
single-master;
};
/* Verdin I2C_1 */
@@ -700,6 +704,7 @@ &i2c4 {
pinctrl-1 = <&pinctrl_i2c4_gpio>;
scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
single-master;
gpio_expander_21: gpio-expander@21 {
compatible = "nxp,pcal6416";
@@ -788,6 +793,7 @@ &i2c5 {
pinctrl-1 = <&pinctrl_i2c5_gpio>;
scl-gpios = <&gpio3 26 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio3 27 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
single-master;
};
/* Verdin PCIE_1 */

25
arch/arm64/boot/dts/freescale/imx8mp.dtsi
View File

@@ -47,6 +47,20 @@ cpus {
#address-cells = <1>;
#size-cells = <0>;
idle-states {
entry-method = "psci";
cpu_pd_wait: cpu-pd-wait {
compatible = "arm,idle-state";
arm,psci-suspend-param = <0x0010033>;
local-timer-stop;
entry-latency-us = <1000>;
exit-latency-us = <700>;
min-residency-us = <2700>;
wakeup-latency-us = <1500>;
};
};
A53_0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53";
@@ -65,6 +79,7 @@ A53_0: cpu@0 {
nvmem-cell-names = "speed_grade";
operating-points-v2 = <&a53_opp_table>;
#cooling-cells = <2>;
cpu-idle-states = <&cpu_pd_wait>;
};
A53_1: cpu@1 {
@@ -83,6 +98,7 @@ A53_1: cpu@1 {
next-level-cache = <&A53_L2>;
operating-points-v2 = <&a53_opp_table>;
#cooling-cells = <2>;
cpu-idle-states = <&cpu_pd_wait>;
};
A53_2: cpu@2 {
@@ -101,6 +117,7 @@ A53_2: cpu@2 {
next-level-cache = <&A53_L2>;
operating-points-v2 = <&a53_opp_table>;
#cooling-cells = <2>;
cpu-idle-states = <&cpu_pd_wait>;
};
A53_3: cpu@3 {
@@ -119,6 +136,7 @@ A53_3: cpu@3 {
next-level-cache = <&A53_L2>;
operating-points-v2 = <&a53_opp_table>;
#cooling-cells = <2>;
cpu-idle-states = <&cpu_pd_wait>;
};
A53_L2: l2-cache0 {
@@ -2176,8 +2194,11 @@ pcie: pcie@33800000 {
pcie_ep: pcie-ep@33800000 {
compatible = "fsl,imx8mp-pcie-ep";
reg = <0x33800000 0x000400000>, <0x18000000 0x08000000>;
reg-names = "dbi", "addr_space";
reg = <0x33800000 0x100000>,
<0x18000000 0x8000000>,
<0x33900000 0x100000>,
<0x33b00000 0x100000>;
reg-names = "dbi", "addr_space", "dbi2", "atu";
clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
<&clk IMX8MP_CLK_HSIO_AXI>,
<&clk IMX8MP_CLK_PCIE_ROOT>;

8
arch/arm64/boot/dts/freescale/imx8mq.dtsi
View File

@@ -1819,9 +1819,11 @@ pcie1: pcie@33c00000 {
pcie1_ep: pcie-ep@33c00000 {
compatible = "fsl,imx8mq-pcie-ep";
reg = <0x33c00000 0x000400000>,
<0x20000000 0x08000000>;
reg-names = "dbi", "addr_space";
reg = <0x33c00000 0x100000>,
<0x20000000 0x8000000>,
<0x33d00000 0x100000>,
<0x33f00000 0x100000>;
reg-names = "dbi", "addr_space", "dbi2", "atu";
num-lanes = <1>;
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "dma";

89
arch/arm64/boot/dts/freescale/imx8qm-mek.dts
View File

@@ -92,6 +92,27 @@ vdevbuffer: memory@90400000 {
reg = <0 0x90400000 0 0x100000>;
no-map;
};
dsp_reserved: memory@92400000 {
reg = <0 0x92400000 0 0x1000000>;
no-map;
};
dsp_vdev0vring0: memory@942f0000 {
reg = <0 0x942f0000 0 0x8000>;
no-map;
};
dsp_vdev0vring1: memory@942f8000 {
reg = <0 0x942f8000 0 0x8000>;
no-map;
};
dsp_vdev0buffer: memory@94300000 {
compatible = "shared-dma-pool";
reg = <0 0x94300000 0 0x100000>;
no-map;
};
};
lvds_backlight0: backlight-lvds0 {
@@ -181,6 +202,17 @@ reg_can2_stby: regulator-can2-stby {
vin-supply = <&reg_can2_en>;
};
reg_pciea: regulator-pcie {
compatible = "regulator-fixed";
pinctrl-0 = <&pinctrl_pciea_reg>;
pinctrl-names = "default";
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3300000>;
regulator-name = "mpcie_3v3";
gpio = <&lsio_gpio1 13 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_vref_1v8: regulator-adc-vref {
compatible = "regulator-fixed";
regulator-name = "vref_1v8";
@@ -296,6 +328,12 @@ &cm41_intmux {
status = "okay";
};
&hsio_phy {
fsl,hsio-cfg = "pciea-pcieb-sata";
fsl,refclk-pad-mode = "input";
status = "okay";
};
&i2c0 {
#address-cells = <1>;
#size-cells = <0>;
@@ -541,6 +579,25 @@ &fec2 {
status = "okay";
};
&pciea {
phys = <&hsio_phy 0 PHY_TYPE_PCIE 0>;
phy-names = "pcie-phy";
pinctrl-0 = <&pinctrl_pciea>;
pinctrl-names = "default";
reset-gpio = <&lsio_gpio4 29 GPIO_ACTIVE_LOW>;
vpcie-supply = <&reg_pciea>;
status = "okay";
};
&pcieb {
phys = <&hsio_phy 1 PHY_TYPE_PCIE 1>;
phy-names = "pcie-phy";
pinctrl-0 = <&pinctrl_pcieb>;
pinctrl-names = "default";
reset-gpio = <&lsio_gpio5 0 GPIO_ACTIVE_LOW>;
status = "disabled";
};
&qm_pwm_lvds0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm_lvds0>;
@@ -640,6 +697,16 @@ &sai7 {
status = "okay";
};
&sata {
status = "okay";
};
&vpu_dsp {
memory-region = <&dsp_vdev0buffer>, <&dsp_vdev0vring0>,
<&dsp_vdev0vring1>, <&dsp_reserved>;
status = "okay";
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
@@ -829,6 +896,28 @@ IMX8QM_LVDS1_I2C1_SDA_LVDS1_I2C1_SDA 0xc600004c
>;
};
pinctrl_pciea: pcieagrp {
fsl,pins = <
IMX8QM_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO28 0x04000021
IMX8QM_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO29 0x06000021
IMX8QM_SCU_GPIO0_07_SCU_DSC_RTC_CLOCK_OUTPUT_32K 0x20
>;
};
pinctrl_pciea_reg: pcieareggrp {
fsl,pins = <
IMX8QM_LVDS1_I2C0_SDA_LSIO_GPIO1_IO13 0x06000021
>;
};
pinctrl_pcieb: pciebgrp {
fsl,pins = <
IMX8QM_PCIE_CTRL1_CLKREQ_B_HSIO_PCIE1_CLKREQ_B 0x06000021
IMX8QM_PCIE_CTRL1_WAKE_B_LSIO_GPIO4_IO31 0x04000021
IMX8QM_PCIE_CTRL1_PERST_B_LSIO_GPIO5_IO00 0x06000021
>;
};
pinctrl_pwm_lvds0: pwmlvds0grp {
fsl,pins = <
IMX8QM_LVDS0_GPIO00_LVDS0_PWM0_OUT 0x00000020

4
arch/arm64/boot/dts/freescale/imx8qm-ss-audio.dtsi
View File

@@ -304,7 +304,7 @@ &dsp_ram_lpcg {
};
/* edma2 called in imx8qm RM with the same address in edma0 of imx8qxp */
&edma0{
&edma0 {
reg = <0x591f0000 0x150000>;
dma-channels = <20>;
dma-channel-mask = <0>;
@@ -351,7 +351,7 @@ &edma0{
};
/* edma3 called in imx8qm RM with the same address in edma1 of imx8qxp */
&edma1{
&edma1 {
reg = <0x599f0000 0xc0000>;
dma-channels = <11>;
dma-channel-mask = <0xc0>;

4
arch/arm64/boot/dts/freescale/imx8qm-ss-conn.dtsi
View File

@@ -4,6 +4,10 @@
* Dong Aisheng <aisheng.dong@nxp.com>
*/
&usbphy1 {
compatible = "fsl,imx8qm-usbphy", "fsl,imx7ulp-usbphy";
};
&fec1 {
compatible = "fsl,imx8qm-fec", "fsl,imx6sx-fec";
iommus = <&smmu 0x12 0x7f80>;

3
arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi
View File

@@ -4,6 +4,9 @@
* Dong Aisheng <aisheng.dong@nxp.com>
*/
/delete-node/ &adma_pwm;
/delete-node/ &adma_pwm_lpcg;
&dma_subsys {
uart4_lpcg: clock-controller@5a4a0000 {
compatible = "fsl,imx8qxp-lpcg";

209
arch/arm64/boot/dts/freescale/imx8qm-ss-hsio.dtsi Normal file
View File

@@ -0,0 +1,209 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2024 NXP
* Richard Zhu <hongxing.zhu@nxp.com>
*/
&hsio_subsys {
compatible = "simple-bus";
ranges = <0x5f000000 0x0 0x5f000000 0x01000000>,
<0x40000000 0x0 0x60000000 0x10000000>,
<0x80000000 0x0 0x70000000 0x10000000>;
#address-cells = <1>;
#size-cells = <1>;
pciea: pcie@5f000000 {
compatible = "fsl,imx8q-pcie";
reg = <0x5f000000 0x10000>,
<0x4ff00000 0x80000>;
reg-names = "dbi", "config";
ranges = <0x81000000 0 0x00000000 0x4ff80000 0 0x00010000>,
<0x82000000 0 0x40000000 0x40000000 0 0x0ff00000>;
#interrupt-cells = <1>;
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi";
#address-cells = <3>;
#size-cells = <2>;
clocks = <&pciea_lpcg IMX_LPCG_CLK_6>,
<&pciea_lpcg IMX_LPCG_CLK_4>,
<&pciea_lpcg IMX_LPCG_CLK_5>;
clock-names = "dbi", "mstr", "slv";
bus-range = <0x00 0xff>;
device_type = "pci";
interrupt-map = <0 0 0 1 &gic 0 73 4>,
<0 0 0 2 &gic 0 74 4>,
<0 0 0 3 &gic 0 75 4>,
<0 0 0 4 &gic 0 76 4>;
interrupt-map-mask = <0 0 0 0x7>;
num-lanes = <1>;
num-viewport = <4>;
power-domains = <&pd IMX_SC_R_PCIE_A>;
fsl,max-link-speed = <3>;
status = "disabled";
};
pcieb: pcie@5f010000 {
compatible = "fsl,imx8q-pcie";
reg = <0x5f010000 0x10000>,
<0x8ff00000 0x80000>;
reg-names = "dbi", "config";
ranges = <0x81000000 0 0x00000000 0x8ff80000 0 0x00010000>,
<0x82000000 0 0x80000000 0x80000000 0 0x0ff00000>;
#interrupt-cells = <1>;
interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi";
#address-cells = <3>;
#size-cells = <2>;
clocks = <&pcieb_lpcg IMX_LPCG_CLK_6>,
<&pcieb_lpcg IMX_LPCG_CLK_4>,
<&pcieb_lpcg IMX_LPCG_CLK_5>;
clock-names = "dbi", "mstr", "slv";
bus-range = <0x00 0xff>;
device_type = "pci";
interrupt-map = <0 0 0 1 &gic 0 105 4>,
<0 0 0 2 &gic 0 106 4>,
<0 0 0 3 &gic 0 107 4>,
<0 0 0 4 &gic 0 108 4>;
interrupt-map-mask = <0 0 0 0x7>;
num-lanes = <1>;
num-viewport = <4>;
power-domains = <&pd IMX_SC_R_PCIE_B>;
fsl,max-link-speed = <3>;
status = "disabled";
};
sata: sata@5f020000 {
compatible = "fsl,imx8qm-ahci";
reg = <0x5f020000 0x10000>;
interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&sata_lpcg IMX_LPCG_CLK_4>,
<&sata_crr4_lpcg IMX_LPCG_CLK_4>;
clock-names = "sata", "sata_ref";
phy-names = "sata-phy", "cali-phy0", "cali-phy1";
power-domains = <&pd IMX_SC_R_SATA_0>;
/*
* Since "REXT" pin is only present for first lane PHY
* and its calibration result will be stored, and shared
* by the PHY used by SATA.
*
* Add the calibration PHYs for SATA here, although only
* the third lane PHY is used by SATA.
*/
phys = <&hsio_phy 2 PHY_TYPE_SATA 0>,
<&hsio_phy 0 PHY_TYPE_PCIE 0>,
<&hsio_phy 1 PHY_TYPE_PCIE 1>;
status = "disabled";
};
pciea_lpcg: clock-controller@5f050000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x5f050000 0x10000>;
clocks = <&hsio_axi_clk>, <&hsio_axi_clk>, <&hsio_axi_clk>;
#clock-cells = <1>;
clock-indices = <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>, <IMX_LPCG_CLK_6>;
clock-output-names = "hsio_pciea_mstr_axi_clk",
"hsio_pciea_slv_axi_clk",
"hsio_pciea_dbi_axi_clk";
power-domains = <&pd IMX_SC_R_PCIE_A>;
};
sata_lpcg: clock-controller@5f070000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x5f070000 0x10000>;
clocks = <&hsio_axi_clk>;
#clock-cells = <1>;
clock-indices = <IMX_LPCG_CLK_4>;
clock-output-names = "hsio_sata_clk";
power-domains = <&pd IMX_SC_R_SATA_0>;
};
phyx2_lpcg: clock-controller@5f080000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x5f080000 0x10000>;
clocks = <&hsio_refa_clk>, <&hsio_per_clk>,
<&hsio_refa_clk>, <&hsio_per_clk>;
#clock-cells = <1>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
<IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>;
clock-output-names = "hsio_phyx2_pclk_0",
"hsio_phyx2_pclk_1",
"hsio_phyx2_apbclk_0",
"hsio_phyx2_apbclk_1";
power-domains = <&pd IMX_SC_R_SERDES_0>;
};
phyx1_lpcg: clock-controller@5f090000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x5f090000 0x10000>;
clocks = <&hsio_refa_clk>, <&hsio_per_clk>,
<&hsio_per_clk>, <&hsio_per_clk>;
#clock-cells = <1>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
<IMX_LPCG_CLK_2>, <IMX_LPCG_CLK_4>;
clock-output-names = "hsio_phyx1_pclk",
"hsio_phyx1_epcs_tx_clk",
"hsio_phyx1_epcs_rx_clk",
"hsio_phyx1_apb_clk";
power-domains = <&pd IMX_SC_R_SERDES_1>;
};
phyx2_crr0_lpcg: clock-controller@5f0a0000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x5f0a0000 0x10000>;
clocks = <&hsio_per_clk>;
#clock-cells = <1>;
clock-indices = <IMX_LPCG_CLK_4>;
clock-output-names = "hsio_phyx2_per_clk";
power-domains = <&pd IMX_SC_R_SERDES_0>;
};
pciea_crr2_lpcg: clock-controller@5f0c0000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x5f0c0000 0x10000>;
clocks = <&hsio_per_clk>;
#clock-cells = <1>;
clock-indices = <IMX_LPCG_CLK_4>;
clock-output-names = "hsio_pciea_per_clk";
power-domains = <&pd IMX_SC_R_PCIE_A>;
};
sata_crr4_lpcg: clock-controller@5f0e0000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x5f0e0000 0x10000>;
clocks = <&hsio_per_clk>;
#clock-cells = <1>;
clock-indices = <IMX_LPCG_CLK_4>;
clock-output-names = "hsio_sata_per_clk";
power-domains = <&pd IMX_SC_R_SATA_0>;
};
hsio_phy: phy@5f180000 {
compatible = "fsl,imx8qm-hsio";
reg = <0x5f180000 0x30000>,
<0x5f110000 0x20000>,
<0x5f130000 0x30000>,
<0x5f160000 0x10000>;
reg-names = "reg", "phy", "ctrl", "misc";
clocks = <&phyx2_lpcg IMX_LPCG_CLK_0>,
<&phyx2_lpcg IMX_LPCG_CLK_1>,
<&phyx2_lpcg IMX_LPCG_CLK_4>,
<&phyx2_lpcg IMX_LPCG_CLK_5>,
<&phyx1_lpcg IMX_LPCG_CLK_0>,
<&phyx1_lpcg IMX_LPCG_CLK_1>,
<&phyx1_lpcg IMX_LPCG_CLK_2>,
<&phyx1_lpcg IMX_LPCG_CLK_4>,
<&phyx2_crr0_lpcg IMX_LPCG_CLK_4>,
<&phyx1_crr1_lpcg IMX_LPCG_CLK_4>,
<&pciea_crr2_lpcg IMX_LPCG_CLK_4>,
<&pcieb_crr3_lpcg IMX_LPCG_CLK_4>,
<&sata_crr4_lpcg IMX_LPCG_CLK_4>,
<&misc_crr5_lpcg IMX_LPCG_CLK_4>;
clock-names = "pclk0", "pclk1", "apb_pclk0", "apb_pclk1",
"pclk2", "epcs_tx", "epcs_rx", "apb_pclk2",
"phy0_crr", "phy1_crr", "ctl0_crr",
"ctl1_crr", "ctl2_crr", "misc_crr";
#phy-cells = <3>;
power-domains = <&pd IMX_SC_R_SERDES_0>, <&pd IMX_SC_R_SERDES_1>;
status = "disabled";
};
};

34
arch/arm64/boot/dts/freescale/imx8qm.dtsi
View File

@@ -24,6 +24,10 @@ aliases {
serial1 = &lpuart1;
serial2 = &lpuart2;
serial3 = &lpuart3;
spi0 = &lpspi0;
spi1 = &lpspi1;
spi2 = &lpspi2;
spi3 = &lpspi3;
vpu-core0 = &vpu_core0;
vpu-core1 = &vpu_core1;
vpu-core2 = &vpu_core2;
@@ -581,6 +585,32 @@ mipi_pll_div2_clk: clock-controller-mipi-div2-pll {
clock-output-names = "mipi_pll_div2_clk";
};
vpu_subsys_dsp: bus@55000000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x55000000 0x0 0x55000000 0x1000000>;
vpu_dsp: dsp@556e8000 {
compatible = "fsl,imx8qm-hifi4";
reg = <0x556e8000 0x88000>;
clocks = <&clk_dummy>,
<&clk_dummy>,
<&clk_dummy>;
clock-names = "ipg", "ocram", "core";
power-domains = <&pd IMX_SC_R_MU_13B>,
<&pd IMX_SC_R_DSP>,
<&pd IMX_SC_R_DSP_RAM>,
<&pd IMX_SC_R_MU_2A>;
mboxes = <&lsio_mu13 0 0>,
<&lsio_mu13 1 0>,
<&lsio_mu13 3 0>;
mbox-names = "tx", "rx", "rxdb";
firmware-name = "imx/dsp/hifi4.bin";
status = "disabled";
};
};
/* sorted in register address */
#include "imx8-ss-cm41.dtsi"
#include "imx8-ss-audio.dtsi"
@@ -594,6 +624,7 @@ mipi_pll_div2_clk: clock-controller-mipi-div2-pll {
#include "imx8-ss-dma.dtsi"
#include "imx8-ss-conn.dtsi"
#include "imx8-ss-lsio.dtsi"
#include "imx8-ss-hsio.dtsi"
};
#include "imx8qm-ss-img.dtsi"
@@ -603,3 +634,6 @@ mipi_pll_div2_clk: clock-controller-mipi-div2-pll {
#include "imx8qm-ss-audio.dtsi"
#include "imx8qm-ss-lvds.dtsi"
#include "imx8qm-ss-mipi.dtsi"
#include "imx8qm-ss-hsio.dtsi"
/delete-node/ &dsp;

298
arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
View File

@@ -12,15 +12,52 @@ / {
model = "Freescale i.MX8QXP MEK";
compatible = "fsl,imx8qxp-mek", "fsl,imx8qxp";
bt_sco_codec: audio-codec-bt {
compatible = "linux,bt-sco";
#sound-dai-cells = <1>;
};
chosen {
stdout-path = &lpuart0;
};
imx8x_cm4: imx8x-cm4 {
compatible = "fsl,imx8qxp-cm4";
mbox-names = "tx", "rx", "rxdb";
mboxes = <&lsio_mu5 0 1
&lsio_mu5 1 1
&lsio_mu5 3 1>;
memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>,
<&vdev1vring0>, <&vdev1vring1>, <&rsc_table>;
power-domains = <&pd IMX_SC_R_M4_0_PID0>,
<&pd IMX_SC_R_M4_0_MU_1A>;
fsl,entry-address = <0x34fe0000>;
fsl,resource-id = <IMX_SC_R_M4_0_PID0>;
};
memory@80000000 {
device_type = "memory";
reg = <0x00000000 0x80000000 0 0x40000000>;
};
reserved-memory {
dsp_vdev0vring0: memory@942f0000 {
reg = <0 0x942f0000 0 0x8000>;
no-map;
};
dsp_vdev0vring1: memory@942f8000 {
reg = <0 0x942f8000 0 0x8000>;
no-map;
};
dsp_vdev0buffer: memory@94300000 {
compatible = "shared-dma-pool";
reg = <0 0x94300000 0 0x100000>;
no-map;
};
};
reg_usdhc2_vmmc: usdhc2-vmmc {
compatible = "regulator-fixed";
regulator-name = "SD1_SPWR";
@@ -45,6 +82,132 @@ usb3_data_ss: endpoint {
};
};
reg_pcieb: regulator-pcie {
compatible = "regulator-fixed";
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3300000>;
regulator-name = "mpcie_3v3";
gpio = <&pca9557_a 2 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_audio: regulator-audio {
compatible = "regulator-fixed";
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3300000>;
regulator-name = "cs42888_supply";
};
reg_can_en: regulator-can-en {
compatible = "regulator-fixed";
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3300000>;
regulator-name = "can-en";
gpio = <&pca6416 3 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_can_stby: regulator-can-stby {
compatible = "regulator-fixed";
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <3300000>;
regulator-name = "can-stby";
gpio = <&pca6416 5 GPIO_ACTIVE_HIGH>;
enable-active-high;
vin-supply = <&reg_can_en>;
};
reg_usb_otg1_vbus: regulator-usbotg1-vbus {
compatible = "regulator-fixed";
regulator-max-microvolt = <5000000>;
regulator-min-microvolt = <5000000>;
regulator-name = "usb_otg1_vbus";
gpio = <&pca9557_b 2 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
vdev0vring0: memory@90000000 {
reg = <0 0x90000000 0 0x8000>;
no-map;
};
vdev0vring1: memory@90008000 {
reg = <0 0x90008000 0 0x8000>;
no-map;
};
vdev1vring0: memory@90010000 {
reg = <0 0x90010000 0 0x8000>;
no-map;
};
vdev1vring1: memory@90018000 {
reg = <0 0x90018000 0 0x8000>;
no-map;
};
rsc_table: memory@900ff000 {
reg = <0 0x900ff000 0 0x1000>;
no-map;
};
vdevbuffer: memory@90400000 {
compatible = "shared-dma-pool";
reg = <0 0x90400000 0 0x100000>;
no-map;
};
gpu_reserved: memory@880000000 {
no-map;
reg = <0x8 0x80000000 0 0x10000000>;
};
};
sound-bt-sco {
compatible = "simple-audio-card";
simple-audio-card,bitclock-inversion;
simple-audio-card,bitclock-master = <&btcpu>;
simple-audio-card,format = "dsp_a";
simple-audio-card,frame-master = <&btcpu>;
simple-audio-card,name = "bt-sco-audio";
simple-audio-card,codec {
sound-dai = <&bt_sco_codec 1>;
};
btcpu: simple-audio-card,cpu {
dai-tdm-slot-num = <2>;
dai-tdm-slot-width = <16>;
sound-dai = <&sai0>;
};
};
sound-cs42888 {
compatible = "fsl,imx-audio-cs42888";
audio-asrc = <&asrc0>;
audio-codec = <&cs42888>;
audio-cpu = <&esai0>;
audio-routing =
"Line Out Jack", "AOUT1L",
"Line Out Jack", "AOUT1R",
"Line Out Jack", "AOUT2L",
"Line Out Jack", "AOUT2R",
"Line Out Jack", "AOUT3L",
"Line Out Jack", "AOUT3R",
"Line Out Jack", "AOUT4L",
"Line Out Jack", "AOUT4R",
"AIN1L", "Line In Jack",
"AIN1R", "Line In Jack",
"AIN2L", "Line In Jack",
"AIN2R", "Line In Jack";
model = "imx-cs42888";
};
sound-wm8960 {
compatible = "fsl,imx-audio-wm8960";
model = "wm8960-audio";
@@ -62,8 +225,18 @@ sound-wm8960 {
};
};
&amix {
status = "okay";
};
&asrc0 {
fsl,asrc-rate = <48000>;
status = "okay";
};
&dsp {
memory-region = <&dsp_reserved>;
memory-region = <&dsp_vdev0buffer>, <&dsp_vdev0vring0>,
<&dsp_vdev0vring1>, <&dsp_reserved>;
status = "okay";
};
@@ -71,6 +244,19 @@ &dsp_reserved {
status = "okay";
};
&esai0 {
assigned-clocks = <&acm IMX_ADMA_ACM_ESAI0_MCLK_SEL>,
<&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>,
<&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>,
<&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>,
<&esai0_lpcg IMX_LPCG_CLK_0>;
assigned-clock-parents = <&aud_pll_div0_lpcg IMX_LPCG_CLK_0>;
assigned-clock-rates = <0>, <786432000>, <49152000>, <12288000>, <49152000>;
pinctrl-0 = <&pinctrl_esai0>;
pinctrl-names = "default";
status = "okay";
};
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec1>;
@@ -240,12 +426,57 @@ pca6416: gpio@20 {
gpio-controller;
#gpio-cells = <2>;
};
cs42888: audio-codec@48 {
compatible = "cirrus,cs42888";
reg = <0x48>;
clocks = <&mclkout0_lpcg IMX_LPCG_CLK_0>;
clock-names = "mclk";
assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>,
<&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>,
<&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>,
<&mclkout0_lpcg IMX_LPCG_CLK_0>;
assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>;
reset-gpios = <&pca9557_b 1 GPIO_ACTIVE_LOW>;
VA-supply = <&reg_audio>;
VD-supply = <&reg_audio>;
VLC-supply = <&reg_audio>;
VLS-supply = <&reg_audio>;
};
};
&cm40_intmux {
status = "okay";
};
&hsio_phy {
fsl,hsio-cfg = "pciea-x2-pcieb";
fsl,refclk-pad-mode = "input";
status = "okay";
};
&flexcan1 {
pinctrl-0 = <&pinctrl_flexcan1>;
pinctrl-names = "default";
xceiver-supply = <&reg_can_stby>;
status = "okay";
};
&flexcan2 {
pinctrl-0 = <&pinctrl_flexcan2>;
pinctrl-names = "default";
xceiver-supply = <&reg_can_stby>;
status = "okay";
};
&jpegdec {
status = "okay";
};
&jpegenc {
status = "okay";
};
&lpuart0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpuart0>;
@@ -264,6 +495,10 @@ &lpuart3 {
status = "okay";
};
&lsio_mu5 {
status = "okay";
};
&mu_m0 {
status = "okay";
};
@@ -272,6 +507,16 @@ &mu1_m0 {
status = "okay";
};
&pcieb {
phys = <&hsio_phy 0 PHY_TYPE_PCIE 0>;
phy-names = "pcie-phy";
pinctrl-0 = <&pinctrl_pcieb>;
pinctrl-names = "default";
reset-gpios = <&lsio_gpio4 0 GPIO_ACTIVE_LOW>;
vpcie-supply = <&reg_pcieb>;
status = "okay";
};
&scu_key {
status = "okay";
};
@@ -384,6 +629,20 @@ &usb3_phy {
status = "okay";
};
&usbphy1 {
status = "okay";
};
&usbotg1 {
adp-disable;
hnp-disable;
srp-disable;
disable-over-current;
power-active-high;
vbus-supply = <&reg_usb_otg1_vbus>;
status = "okay";
};
&usbotg3 {
status = "okay";
};
@@ -434,6 +693,21 @@ IMX8QXP_ADC_IN0_LSIO_GPIO1_IO10 0xc600004c
>;
};
pinctrl_esai0: esai0grp {
fsl,pins = <
IMX8QXP_ESAI0_FSR_ADMA_ESAI0_FSR 0xc6000040
IMX8QXP_ESAI0_FST_ADMA_ESAI0_FST 0xc6000040
IMX8QXP_ESAI0_SCKR_ADMA_ESAI0_SCKR 0xc6000040
IMX8QXP_ESAI0_SCKT_ADMA_ESAI0_SCKT 0xc6000040
IMX8QXP_ESAI0_TX0_ADMA_ESAI0_TX0 0xc6000040
IMX8QXP_ESAI0_TX1_ADMA_ESAI0_TX1 0xc6000040
IMX8QXP_ESAI0_TX2_RX3_ADMA_ESAI0_TX2_RX3 0xc6000040
IMX8QXP_ESAI0_TX3_RX2_ADMA_ESAI0_TX3_RX2 0xc6000040
IMX8QXP_ESAI0_TX4_RX1_ADMA_ESAI0_TX4_RX1 0xc6000040
IMX8QXP_ESAI0_TX5_RX0_ADMA_ESAI0_TX5_RX0 0xc6000040
>;
};
pinctrl_fec1: fec1grp {
fsl,pins = <
IMX8QXP_ENET0_MDC_CONN_ENET0_MDC 0x06000020
@@ -453,6 +727,20 @@ IMX8QXP_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000020
>;
};
pinctrl_flexcan1: flexcan0grp {
fsl,pins = <
IMX8QXP_FLEXCAN0_TX_ADMA_FLEXCAN0_TX 0x21
IMX8QXP_FLEXCAN0_RX_ADMA_FLEXCAN0_RX 0x21
>;
};
pinctrl_flexcan2: flexcan1grp {
fsl,pins = <
IMX8QXP_FLEXCAN1_TX_ADMA_FLEXCAN1_TX 0x21
IMX8QXP_FLEXCAN1_RX_ADMA_FLEXCAN1_RX 0x21
>;
};
pinctrl_ioexp_rst: ioexprstgrp {
fsl,pins = <
IMX8QXP_SPI2_SDO_LSIO_GPIO1_IO01 0x06000021
@@ -493,6 +781,14 @@ IMX8QXP_FLEXCAN2_RX_ADMA_UART3_RX 0x06000020
>;
};
pinctrl_pcieb: pcieagrp {
fsl,pins = <
IMX8QXP_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00 0x06000021
IMX8QXP_PCIE_CTRL0_CLKREQ_B_HSIO_PCIE0_CLKREQ_B 0x06000021
IMX8QXP_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02 0x04000021
>;
};
pinctrl_typec: typecgrp {
fsl,pins = <
IMX8QXP_SPI2_SCK_LSIO_GPIO1_IO03 0x06000021

4
arch/arm64/boot/dts/freescale/imx8qxp-ss-conn.dtsi
View File

@@ -4,6 +4,10 @@
* Dong Aisheng <aisheng.dong@nxp.com>
*/
&usbphy1 {
compatible = "fsl,imx8qxp-usbphy", "fsl,imx7ulp-usbphy";
};
&usdhc1 {
compatible = "fsl,imx8qxp-usdhc", "fsl,imx7d-usdhc";
};

41
arch/arm64/boot/dts/freescale/imx8qxp-ss-hsio.dtsi Normal file
View File

@@ -0,0 +1,41 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2024 NXP
* Richard Zhu <hongxing.zhu@nxp.com>
*/
&hsio_subsys {
phyx1_lpcg: clock-controller@5f090000 {
compatible = "fsl,imx8qxp-lpcg";
reg = <0x5f090000 0x10000>;
clocks = <&hsio_refb_clk>, <&hsio_per_clk>,
<&hsio_per_clk>, <&hsio_per_clk>;
#clock-cells = <1>;
clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
<IMX_LPCG_CLK_2>, <IMX_LPCG_CLK_4>;
clock-output-names = "hsio_phyx1_pclk",
"hsio_phyx1_epcs_tx_clk",
"hsio_phyx1_epcs_rx_clk",
"hsio_phyx1_apb_clk";
power-domains = <&pd IMX_SC_R_SERDES_1>;
};
hsio_phy: phy@5f1a0000 {
compatible = "fsl,imx8qxp-hsio";
reg = <0x5f1a0000 0x10000>,
<0x5f120000 0x10000>,
<0x5f140000 0x10000>,
<0x5f160000 0x10000>;
reg-names = "reg", "phy", "ctrl", "misc";
clocks = <&phyx1_lpcg IMX_LPCG_CLK_0>,
<&phyx1_lpcg IMX_LPCG_CLK_1>,
<&phyx1_crr1_lpcg IMX_LPCG_CLK_4>,
<&pcieb_crr3_lpcg IMX_LPCG_CLK_4>,
<&misc_crr5_lpcg IMX_LPCG_CLK_4>;
clock-names = "pclk0", "apb_pclk0", "phy0_crr", "ctl0_crr",
"misc_crr";
#phy-cells = <3>;
power-domains = <&pd IMX_SC_R_SERDES_1>;
status = "disabled";
};
};

6
arch/arm64/boot/dts/freescale/imx8qxp.dtsi
View File

@@ -46,6 +46,10 @@ aliases {
serial1 = &lpuart1;
serial2 = &lpuart2;
serial3 = &lpuart3;
spi0 = &lpspi0;
spi1 = &lpspi1;
spi2 = &lpspi2;
spi3 = &lpspi3;
vpu-core0 = &vpu_core0;
vpu-core1 = &vpu_core1;
};
@@ -323,6 +327,7 @@ map0 {
#include "imx8-ss-conn.dtsi"
#include "imx8-ss-ddr.dtsi"
#include "imx8-ss-lsio.dtsi"
#include "imx8-ss-hsio.dtsi"
};
#include "imx8qxp-ss-img.dtsi"
@@ -330,3 +335,4 @@ map0 {
#include "imx8qxp-ss-adma.dtsi"
#include "imx8qxp-ss-conn.dtsi"
#include "imx8qxp-ss-lsio.dtsi"
#include "imx8qxp-ss-hsio.dtsi"

70
arch/arm64/boot/dts/freescale/imx8ulp-evk.dts
View File

@@ -11,6 +11,11 @@ / {
model = "NXP i.MX8ULP EVK";
compatible = "fsl,imx8ulp-evk", "fsl,imx8ulp";
bt_sco_codec: bt-sco-codec {
#sound-dai-cells = <1>;
compatible = "linux,bt-sco";
};
chosen {
stdout-path = &lpuart5;
};
@@ -83,6 +88,37 @@ clock_ext_ts: clock-ext-ts {
clock-output-names = "ext_ts_clk";
#clock-cells = <0>;
};
sound-bt-sco {
compatible = "simple-audio-card";
simple-audio-card,name = "bt-sco-audio";
simple-audio-card,format = "dsp_a";
simple-audio-card,bitclock-inversion;
simple-audio-card,frame-master = <&btcpu>;
simple-audio-card,bitclock-master = <&btcpu>;
btcpu: simple-audio-card,cpu {
sound-dai = <&sai5>;
dai-tdm-slot-num = <2>;
dai-tdm-slot-width = <16>;
};
simple-audio-card,codec {
sound-dai = <&bt_sco_codec 1>;
};
};
sound-spdif {
compatible = "fsl,imx-audio-spdif";
model = "imx-spdif";
audio-cpu = <&spdif>;
audio-codec = <&spdif_out>;
};
spdif_out: spdif-out {
compatible = "linux,spdif-dit";
#sound-dai-cells = <0>;
};
};
&cm33 {
@@ -153,6 +189,25 @@ ptn5150_2: typec@3d {
};
};
&sai5 {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&pinctrl_sai5>;
pinctrl-1 = <&pinctrl_sai5>;
assigned-clocks = <&cgc1 IMX8ULP_CLK_SAI5_SEL>;
assigned-clock-parents = <&cgc1 IMX8ULP_CLK_SPLL3_PFD1_DIV1>;
fsl,dataline = <1 0x08 0x01>;
status = "okay";
};
&spdif {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&pinctrl_spdif>;
pinctrl-1 = <&pinctrl_spdif>;
assigned-clocks = <&cgc2 IMX8ULP_CLK_SPDIF_SEL>;
assigned-clock-parents = <&cgc1 IMX8ULP_CLK_SPLL3_PFD1_DIV1>;
status = "okay";
};
&usbotg1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb1>;
@@ -282,6 +337,21 @@ MX8ULP_PAD_PTE13__LPI2C7_SDA 0x20
>;
};
pinctrl_sai5: sai5grp {
fsl,pins = <
MX8ULP_PAD_PTF26__I2S5_TX_BCLK 0x43
MX8ULP_PAD_PTF27__I2S5_TX_FS 0x43
MX8ULP_PAD_PTF28__I2S5_TXD0 0x43
MX8ULP_PAD_PTF24__I2S5_RXD3 0x43
>;
};
pinctrl_spdif: spdifgrp {
fsl,pins = <
MX8ULP_PAD_PTF25__SPDIF_OUT1 0x43
>;
};
pinctrl_typec1: typec1grp {
fsl,pins = <
MX8ULP_PAD_PTF3__PTF3 0x3

214
arch/arm64/boot/dts/freescale/imx8ulp.dtsi
View File

@@ -28,6 +28,8 @@ aliases {
serial1 = &lpuart5;
serial2 = &lpuart6;
serial3 = &lpuart7;
spi0 = &lpspi4;
spi1 = &lpspi5;
};
cpus {
@@ -212,6 +214,70 @@ per_bridge3: bus@29000000 {
#size-cells = <1>;
ranges;
edma1: dma-controller@29010000 {
compatible = "fsl,imx8ulp-edma";
reg = <0x29010000 0x210000>;
#dma-cells = <3>;
dma-channels = <32>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&pcc3 IMX8ULP_CLK_DMA1_MP>,
<&pcc3 IMX8ULP_CLK_DMA1_CH0>, <&pcc3 IMX8ULP_CLK_DMA1_CH1>,
<&pcc3 IMX8ULP_CLK_DMA1_CH2>, <&pcc3 IMX8ULP_CLK_DMA1_CH3>,
<&pcc3 IMX8ULP_CLK_DMA1_CH4>, <&pcc3 IMX8ULP_CLK_DMA1_CH5>,
<&pcc3 IMX8ULP_CLK_DMA1_CH6>, <&pcc3 IMX8ULP_CLK_DMA1_CH7>,
<&pcc3 IMX8ULP_CLK_DMA1_CH8>, <&pcc3 IMX8ULP_CLK_DMA1_CH9>,
<&pcc3 IMX8ULP_CLK_DMA1_CH10>, <&pcc3 IMX8ULP_CLK_DMA1_CH11>,
<&pcc3 IMX8ULP_CLK_DMA1_CH12>, <&pcc3 IMX8ULP_CLK_DMA1_CH13>,
<&pcc3 IMX8ULP_CLK_DMA1_CH14>, <&pcc3 IMX8ULP_CLK_DMA1_CH15>,
<&pcc3 IMX8ULP_CLK_DMA1_CH16>, <&pcc3 IMX8ULP_CLK_DMA1_CH17>,
<&pcc3 IMX8ULP_CLK_DMA1_CH18>, <&pcc3 IMX8ULP_CLK_DMA1_CH19>,
<&pcc3 IMX8ULP_CLK_DMA1_CH20>, <&pcc3 IMX8ULP_CLK_DMA1_CH21>,
<&pcc3 IMX8ULP_CLK_DMA1_CH22>, <&pcc3 IMX8ULP_CLK_DMA1_CH23>,
<&pcc3 IMX8ULP_CLK_DMA1_CH24>, <&pcc3 IMX8ULP_CLK_DMA1_CH25>,
<&pcc3 IMX8ULP_CLK_DMA1_CH26>, <&pcc3 IMX8ULP_CLK_DMA1_CH27>,
<&pcc3 IMX8ULP_CLK_DMA1_CH28>, <&pcc3 IMX8ULP_CLK_DMA1_CH29>,
<&pcc3 IMX8ULP_CLK_DMA1_CH30>, <&pcc3 IMX8ULP_CLK_DMA1_CH31>;
clock-names = "dma", "ch00","ch01", "ch02", "ch03",
"ch04", "ch05", "ch06", "ch07",
"ch08", "ch09", "ch10", "ch11",
"ch12", "ch13", "ch14", "ch15",
"ch16", "ch17", "ch18", "ch19",
"ch20", "ch21", "ch22", "ch23",
"ch24", "ch25", "ch26", "ch27",
"ch28", "ch29", "ch30", "ch31";
};
mu: mailbox@29220000 {
compatible = "fsl,imx8ulp-mu";
reg = <0x29220000 0x10000>;
@@ -442,6 +508,36 @@ lpuart7: serial@29870000 {
status = "disabled";
};
sai4: sai@29880000 {
compatible = "fsl,imx8ulp-sai";
reg = <0x29880000 0x10000>;
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&pcc4 IMX8ULP_CLK_SAI4>, <&cgc1 IMX8ULP_CLK_DUMMY>,
<&cgc1 IMX8ULP_CLK_SAI4_SEL>, <&cgc1 IMX8ULP_CLK_DUMMY>,
<&cgc1 IMX8ULP_CLK_DUMMY>;
clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
dmas = <&edma1 67 0 1>, <&edma1 68 0 0>;
dma-names = "rx", "tx";
#sound-dai-cells = <0>;
fsl,dataline = <0 0x03 0x03>;
status = "disabled";
};
sai5: sai@29890000 {
compatible = "fsl,imx8ulp-sai";
reg = <0x29890000 0x10000>;
interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&pcc4 IMX8ULP_CLK_SAI5>, <&cgc1 IMX8ULP_CLK_DUMMY>,
<&cgc1 IMX8ULP_CLK_SAI5_SEL>, <&cgc1 IMX8ULP_CLK_DUMMY>,
<&cgc1 IMX8ULP_CLK_DUMMY>;
clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
dmas = <&edma1 69 0 1>, <&edma1 70 0 0>;
dma-names = "rx", "tx";
#sound-dai-cells = <0>;
fsl,dataline = <0 0x0f 0x0f>;
status = "disabled";
};
iomuxc1: pinctrl@298c0000 {
compatible = "fsl,imx8ulp-iomuxc1";
reg = <0x298c0000 0x10000>;
@@ -614,6 +710,70 @@ per_bridge5: bus@2d800000 {
#size-cells = <1>;
ranges;
edma2: dma-controller@2d800000 {
compatible = "fsl,imx8ulp-edma";
reg = <0x2d800000 0x210000>;
#dma-cells = <3>;
dma-channels = <32>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&pcc5 IMX8ULP_CLK_DMA2_MP>,
<&pcc5 IMX8ULP_CLK_DMA2_CH0>, <&pcc5 IMX8ULP_CLK_DMA2_CH1>,
<&pcc5 IMX8ULP_CLK_DMA2_CH2>, <&pcc5 IMX8ULP_CLK_DMA2_CH3>,
<&pcc5 IMX8ULP_CLK_DMA2_CH4>, <&pcc5 IMX8ULP_CLK_DMA2_CH5>,
<&pcc5 IMX8ULP_CLK_DMA2_CH6>, <&pcc5 IMX8ULP_CLK_DMA2_CH7>,
<&pcc5 IMX8ULP_CLK_DMA2_CH8>, <&pcc5 IMX8ULP_CLK_DMA2_CH9>,
<&pcc5 IMX8ULP_CLK_DMA2_CH10>, <&pcc5 IMX8ULP_CLK_DMA2_CH11>,
<&pcc5 IMX8ULP_CLK_DMA2_CH12>, <&pcc5 IMX8ULP_CLK_DMA2_CH13>,
<&pcc5 IMX8ULP_CLK_DMA2_CH14>, <&pcc5 IMX8ULP_CLK_DMA2_CH15>,
<&pcc5 IMX8ULP_CLK_DMA2_CH16>, <&pcc5 IMX8ULP_CLK_DMA2_CH17>,
<&pcc5 IMX8ULP_CLK_DMA2_CH18>, <&pcc5 IMX8ULP_CLK_DMA2_CH19>,
<&pcc5 IMX8ULP_CLK_DMA2_CH20>, <&pcc5 IMX8ULP_CLK_DMA2_CH21>,
<&pcc5 IMX8ULP_CLK_DMA2_CH22>, <&pcc5 IMX8ULP_CLK_DMA2_CH23>,
<&pcc5 IMX8ULP_CLK_DMA2_CH24>, <&pcc5 IMX8ULP_CLK_DMA2_CH25>,
<&pcc5 IMX8ULP_CLK_DMA2_CH26>, <&pcc5 IMX8ULP_CLK_DMA2_CH27>,
<&pcc5 IMX8ULP_CLK_DMA2_CH28>, <&pcc5 IMX8ULP_CLK_DMA2_CH29>,
<&pcc5 IMX8ULP_CLK_DMA2_CH30>, <&pcc5 IMX8ULP_CLK_DMA2_CH31>;
clock-names = "dma", "ch00","ch01", "ch02", "ch03",
"ch04", "ch05", "ch06", "ch07",
"ch08", "ch09", "ch10", "ch11",
"ch12", "ch13", "ch14", "ch15",
"ch16", "ch17", "ch18", "ch19",
"ch20", "ch21", "ch22", "ch23",
"ch24", "ch25", "ch26", "ch27",
"ch28", "ch29", "ch30", "ch31";
};
cgc2: clock-controller@2da60000 {
compatible = "fsl,imx8ulp-cgc2";
reg = <0x2da60000 0x10000>;
@@ -626,6 +786,60 @@ pcc5: clock-controller@2da70000 {
#clock-cells = <1>;
#reset-cells = <1>;
};
sai6: sai@2da90000 {
compatible = "fsl,imx8ulp-sai";
reg = <0x2da90000 0x10000>;
interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&pcc5 IMX8ULP_CLK_SAI6>, <&cgc1 IMX8ULP_CLK_DUMMY>,
<&cgc2 IMX8ULP_CLK_SAI6_SEL>, <&cgc1 IMX8ULP_CLK_DUMMY>,
<&cgc1 IMX8ULP_CLK_DUMMY>;
clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
dmas = <&edma2 71 0 1>, <&edma2 72 0 0>;
dma-names = "rx", "tx";
#sound-dai-cells = <0>;
fsl,dataline = <0 0x0f 0x0f>;
status = "disabled";
};
sai7: sai@2daa0000 {
compatible = "fsl,imx8ulp-sai";
reg = <0x2daa0000 0x10000>;
interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&pcc5 IMX8ULP_CLK_SAI7>, <&cgc1 IMX8ULP_CLK_DUMMY>,
<&cgc2 IMX8ULP_CLK_SAI7_SEL>, <&cgc1 IMX8ULP_CLK_DUMMY>,
<&cgc1 IMX8ULP_CLK_DUMMY>;
clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
dmas = <&edma2 73 0 1>, <&edma2 74 0 0>;
dma-names = "rx", "tx";
#sound-dai-cells = <0>;
fsl,dataline = <0 0x0f 0x0f>;
status = "disabled";
};
spdif: spdif@2dab0000 {
compatible = "fsl,imx8ulp-spdif";
reg = <0x2dab0000 0x10000>;
interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&pcc5 IMX8ULP_CLK_SPDIF>, /* core */
<&sosc>, /* 0, extal */
<&cgc2 IMX8ULP_CLK_SPDIF_SEL>, /* 1, tx */
<&cgc1 IMX8ULP_CLK_DUMMY>, /* 2, tx1 */
<&cgc1 IMX8ULP_CLK_DUMMY>, /* 3, tx2 */
<&cgc1 IMX8ULP_CLK_DUMMY>, /* 4, tx3 */
<&pcc5 IMX8ULP_CLK_SPDIF>, /* 5, sys */
<&cgc1 IMX8ULP_CLK_DUMMY>, /* 6, tx4 */
<&cgc1 IMX8ULP_CLK_DUMMY>, /* 7, tx5 */
<&cgc1 IMX8ULP_CLK_DUMMY>; /* spba */
clock-names = "core", "rxtx0",
"rxtx1", "rxtx2",
"rxtx3", "rxtx4",
"rxtx5", "rxtx6",
"rxtx7", "spba";
dmas = <&edma2 75 0 5>, <&edma2 76 0 4>;
dma-names = "rx", "tx";
status = "disabled";
};
};
gpiod: gpio@2e200000 {

4
arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi
View File

@@ -166,7 +166,7 @@ sgtl5000_a: audio-codec@a {
};
/* Touch controller */
touchscreen@2c {
ad7879_ts: touchscreen@2c {
compatible = "adi,ad7879-1";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ad7879_int>;
@@ -698,7 +698,7 @@ pinctrl_hog2: hog2grp {
/*
* This pin is used in the SCFW as a UART. Using it from
* Linux would require rewritting the SCFW board file.
* Linux would require rewriting the SCFW board file.
*/
pinctrl_hog_scfw: hogscfwgrp {
fsl,pins = <IMX8QXP_SCU_GPIO0_00_LSIO_GPIO2_IO03 0x20>; /* SODIMM 144 */

115
arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts
View File

@@ -78,6 +78,23 @@ reg_vref_1v8: regulator-adc-vref {
regulator-max-microvolt = <1800000>;
};
reg_audio_pwr: regulator-audio-pwr {
compatible = "regulator-fixed";
regulator-name = "audio-pwr";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&adp5585 1 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_can2_standby: regulator-can2-standby {
compatible = "regulator-fixed";
regulator-name = "can2-stby";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&adp5585 6 GPIO_ACTIVE_LOW>;
};
reg_usdhc2_vmmc: regulator-usdhc2 {
compatible = "regulator-fixed";
pinctrl-names = "default";
@@ -139,6 +156,22 @@ cpu {
};
};
sound-wm8962 {
compatible = "fsl,imx-audio-wm8962";
model = "wm8962-audio";
audio-cpu = <&sai3>;
audio-codec = <&wm8962>;
hp-det-gpio = <&pcal6524 4 GPIO_ACTIVE_HIGH>;
audio-routing =
"Headphone Jack", "HPOUTL",
"Headphone Jack", "HPOUTR",
"Ext Spk", "SPKOUTL",
"Ext Spk", "SPKOUTR",
"AMIC", "MICBIAS",
"IN3R", "AMIC",
"IN1R", "AMIC";
};
sound-xcvr {
compatible = "fsl,imx-audio-card";
model = "imx-audio-xcvr";
@@ -216,12 +249,41 @@ ethphy2: ethernet-phy@2 {
};
};
&flexcan2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan2>;
xceiver-supply = <&reg_can2_standby>;
status = "okay";
};
&lpi2c1 {
clock-frequency = <400000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpi2c1>;
status = "okay";
wm8962: codec@1a {
compatible = "wlf,wm8962";
reg = <0x1a>;
clocks = <&clk IMX93_CLK_SAI3_GATE>;
DCVDD-supply = <&reg_audio_pwr>;
DBVDD-supply = <&reg_audio_pwr>;
AVDD-supply = <&reg_audio_pwr>;
CPVDD-supply = <&reg_audio_pwr>;
MICVDD-supply = <&reg_audio_pwr>;
PLLVDD-supply = <&reg_audio_pwr>;
SPKVDD1-supply = <&reg_audio_pwr>;
SPKVDD2-supply = <&reg_audio_pwr>;
gpio-cfg = <
0x0000 /* 0:Default */
0x0000 /* 1:Default */
0x0000 /* 2:FN_DMICCLK */
0x0000 /* 3:Default */
0x0000 /* 4:FN_DMICCDAT */
0x0000 /* 5:Default */
>;
};
inertial-meter@6a {
compatible = "st,lsm6dso";
reg = <0x6a>;
@@ -230,9 +292,8 @@ inertial-meter@6a {
&lpi2c2 {
clock-frequency = <400000>;
pinctrl-names = "default", "sleep";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpi2c2>;
pinctrl-1 = <&pinctrl_lpi2c2>;
status = "okay";
pcal6524: gpio@22 {
@@ -273,7 +334,7 @@ buck2: BUCK2 {
regulator-ramp-delay = <3125>;
};
buck4: BUCK4{
buck4: BUCK4 {
regulator-name = "BUCK4";
regulator-min-microvolt = <1620000>;
regulator-max-microvolt = <3400000>;
@@ -281,7 +342,7 @@ buck4: BUCK4{
regulator-always-on;
};
buck5: BUCK5{
buck5: BUCK5 {
regulator-name = "BUCK5";
regulator-min-microvolt = <1620000>;
regulator-max-microvolt = <3400000>;
@@ -340,6 +401,14 @@ &lpi2c3 {
pinctrl-0 = <&pinctrl_lpi2c3>;
status = "okay";
adp5585_isp: io-expander@34 {
compatible = "adi,adp5585-01", "adi,adp5585";
reg = <0x34>;
gpio-controller;
#gpio-cells = <2>;
#pwm-cells = <3>;
};
ptn5110: tcpc@50 {
compatible = "nxp,ptn5110", "tcpci";
reg = <0x50>;
@@ -455,6 +524,17 @@ &sai1 {
status = "okay";
};
&sai3 {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&pinctrl_sai3>;
pinctrl-1 = <&pinctrl_sai3_sleep>;
assigned-clocks = <&clk IMX93_CLK_SAI3>;
assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>;
assigned-clock-rates = <12288000>;
fsl,sai-mclk-direction-output;
status = "okay";
};
&usbotg1 {
dr_mode = "otg";
hnp-disable;
@@ -614,6 +694,13 @@ MX93_PAD_ENET2_TX_CTL__GPIO4_IO20 0x51e
>;
};
pinctrl_flexcan2: flexcan2grp {
fsl,pins = <
MX93_PAD_GPIO_IO25__CAN2_TX 0x139e
MX93_PAD_GPIO_IO27__CAN2_RX 0x139e
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX93_PAD_UART1_RXD__LPUART1_RX 0x31e
@@ -748,6 +835,26 @@ MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x31e
>;
};
pinctrl_sai3: sai3grp {
fsl,pins = <
MX93_PAD_GPIO_IO26__SAI3_TX_SYNC 0x31e
MX93_PAD_GPIO_IO16__SAI3_TX_BCLK 0x31e
MX93_PAD_GPIO_IO17__SAI3_MCLK 0x31e
MX93_PAD_GPIO_IO19__SAI3_TX_DATA00 0x31e
MX93_PAD_GPIO_IO20__SAI3_RX_DATA00 0x31e
>;
};
pinctrl_sai3_sleep: sai3sleepgrp {
fsl,pins = <
MX93_PAD_GPIO_IO26__GPIO2_IO26 0x51e
MX93_PAD_GPIO_IO16__GPIO2_IO16 0x51e
MX93_PAD_GPIO_IO17__GPIO2_IO17 0x51e
MX93_PAD_GPIO_IO19__GPIO2_IO19 0x51e
MX93_PAD_GPIO_IO20__GPIO2_IO20 0x51e
>;
};
pinctrl_spdif: spdifgrp {
fsl,pins = <
MX93_PAD_GPIO_IO22__SPDIF_IN 0x31e

72
arch/arm64/boot/dts/freescale/imx93-9x9-qsb-i3c.dtso Normal file
View File

@@ -0,0 +1,72 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright 2024 NXP
*/
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/i3c/i3c.h>
#include <dt-bindings/usb/pd.h>
#include "imx93-pinfunc.h"
/dts-v1/;
/plugin/;
&lpi2c1 {
status = "disabled";
};
&i3c1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i3c1>;
#address-cells = <3>;
#size-cells = <0>;
i2c-scl-hz = <400000>;
status = "okay";
tcpc@50 {
compatible = "nxp,ptn5110", "tcpci";
reg = <0x50 0x00 (I2C_FM | I2C_NO_FILTER_LOW_FREQUENCY)>;
interrupt-parent = <&gpio3>;
interrupts = <26 IRQ_TYPE_LEVEL_LOW>;
connector {
compatible = "usb-c-connector";
label = "USB-C";
power-role = "dual";
data-role = "dual";
try-power-role = "sink";
source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
PDO_VAR(5000, 20000, 3000)>;
op-sink-microwatt = <15000000>;
self-powered;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
typec1_dr_sw: endpoint {
remote-endpoint = <&usb1_drd_sw>;
};
};
};
};
};
};
&usb1_drd_sw {
remote-endpoint = <&typec1_dr_sw>;
};
&iomuxc {
pinctrl_i3c1: i3c1grp {
fsl,pins = <
MX93_PAD_I2C1_SCL__I3C1_SCL 0x40000186
MX93_PAD_I2C1_SDA__I3C1_SDA 0x40000186
>;
};
};

158
arch/arm64/boot/dts/freescale/imx93-9x9-qsb.dts
View File

@@ -12,6 +12,11 @@ / {
model = "NXP i.MX93 9x9 Quick Start Board";
compatible = "fsl,imx93-9x9-qsb", "fsl,imx93";
bt_sco_codec: bt-sco-codec {
#sound-dai-cells = <1>;
compatible = "linux,bt-sco";
};
chosen {
stdout-path = &lpuart1;
};
@@ -68,6 +73,15 @@ reg_vref_1v8: regulator-adc-vref {
regulator-max-microvolt = <1800000>;
};
reg_audio_pwr: regulator-audio-pwr {
compatible = "regulator-fixed";
regulator-name = "audio-pwr";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&pcal6524 16 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_rpi_3v3: regulator-rpi {
compatible = "regulator-fixed";
regulator-name = "VDD_RPI_3V3";
@@ -88,6 +102,55 @@ reg_usdhc2_vmmc: regulator-usdhc2 {
enable-active-high;
off-on-delay-us = <12000>;
};
sound-bt-sco {
compatible = "simple-audio-card";
simple-audio-card,name = "bt-sco-audio";
simple-audio-card,format = "dsp_a";
simple-audio-card,bitclock-inversion;
simple-audio-card,frame-master = <&btcpu>;
simple-audio-card,bitclock-master = <&btcpu>;
btcpu: simple-audio-card,cpu {
sound-dai = <&sai1>;
dai-tdm-slot-num = <2>;
dai-tdm-slot-width = <16>;
};
simple-audio-card,codec {
sound-dai = <&bt_sco_codec 1>;
};
};
sound-micfil {
compatible = "fsl,imx-audio-card";
model = "micfil-audio";
pri-dai-link {
link-name = "micfil hifi";
format = "i2s";
cpu {
sound-dai = <&micfil>;
};
};
};
sound-wm8962 {
compatible = "fsl,imx-audio-wm8962";
model = "wm8962-audio";
audio-cpu = <&sai3>;
audio-codec = <&wm8962>;
hp-det-gpio = <&pcal6524 4 GPIO_ACTIVE_HIGH>;
audio-routing =
"Headphone Jack", "HPOUTL",
"Headphone Jack", "HPOUTR",
"Ext Spk", "SPKOUTL",
"Ext Spk", "SPKOUTR",
"AMIC", "MICBIAS",
"IN3R", "AMIC",
"IN1R", "AMIC";
};
};
&adc1 {
@@ -136,6 +199,28 @@ &lpi2c1 {
pinctrl-0 = <&pinctrl_lpi2c1>;
status = "okay";
wm8962: audio-codec@1a {
compatible = "wlf,wm8962";
reg = <0x1a>;
clocks = <&clk IMX93_CLK_SAI3_GATE>;
DCVDD-supply = <&reg_audio_pwr>;
DBVDD-supply = <&reg_audio_pwr>;
AVDD-supply = <&reg_audio_pwr>;
CPVDD-supply = <&reg_audio_pwr>;
MICVDD-supply = <&reg_audio_pwr>;
PLLVDD-supply = <&reg_audio_pwr>;
SPKVDD1-supply = <&reg_audio_pwr>;
SPKVDD2-supply = <&reg_audio_pwr>;
gpio-cfg = <
0x0000 /* 0:Default */
0x0000 /* 1:Default */
0x0000 /* 2:FN_DMICCLK */
0x0000 /* 3:Default */
0x0000 /* 4:FN_DMICCDAT */
0x0000 /* 5:Default */
>;
};
ptn5110: tcpc@50 {
compatible = "nxp,ptn5110", "tcpci";
reg = <0x50>;
@@ -194,6 +279,18 @@ pcal6524: gpio@22 {
interrupts = <26 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcal6524>;
exp-sel-hog {
gpio-hog;
gpios = <22 GPIO_ACTIVE_HIGH>;
output-low;
};
mic-can-sel-hog {
gpio-hog;
gpios = <17 GPIO_ACTIVE_HIGH>;
output-low;
};
};
pmic@25 {
@@ -221,7 +318,7 @@ buck2: BUCK2 {
regulator-ramp-delay = <3125>;
};
buck4: BUCK4{
buck4: BUCK4 {
regulator-name = "BUCK4";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <3400000>;
@@ -229,7 +326,7 @@ buck4: BUCK4{
regulator-always-on;
};
buck5: BUCK5{
buck5: BUCK5 {
regulator-name = "BUCK5";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <3400000>;
@@ -278,6 +375,15 @@ &lpuart1 { /* console */
status = "okay";
};
&micfil {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pdm>;
assigned-clocks = <&clk IMX93_CLK_PDM>;
assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>;
assigned-clock-rates = <49152000>;
status = "okay";
};
&mu1 {
status = "okay";
};
@@ -286,6 +392,27 @@ &mu2 {
status = "okay";
};
&sai1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai1>;
assigned-clocks = <&clk IMX93_CLK_SAI1>;
assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>;
assigned-clock-rates = <12288000>;
fsl,sai-mclk-direction-output;
status = "okay";
};
&sai3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai3>;
assigned-clocks = <&clk IMX93_CLK_SAI3>;
assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>;
assigned-clock-rates = <12288000>;
fsl,sai-mclk-direction-output;
fsl,sai-synchronous-rx;
status = "okay";
};
&usbotg1 {
dr_mode = "otg";
hnp-disable;
@@ -370,6 +497,14 @@ MX93_PAD_CCM_CLKO1__GPIO3_IO26 0x31e
>;
};
pinctrl_pdm: pdmgrp {
fsl,pins = <
MX93_PAD_PDM_CLK__PDM_CLK 0x31e
MX93_PAD_PDM_BIT_STREAM0__PDM_BIT_STREAM00 0x31e
MX93_PAD_PDM_BIT_STREAM1__PDM_BIT_STREAM01 0x31e
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX93_PAD_UART1_RXD__LPUART1_RX 0x31e
@@ -443,6 +578,25 @@ MX93_PAD_SD2_RESET_B__GPIO3_IO07 0x31e
>;
};
pinctrl_sai1: sai1grp {
fsl,pins = <
MX93_PAD_SAI1_TXC__SAI1_TX_BCLK 0x31e
MX93_PAD_SAI1_TXFS__SAI1_TX_SYNC 0x31e
MX93_PAD_SAI1_TXD0__SAI1_TX_DATA00 0x31e
MX93_PAD_SAI1_RXD0__SAI1_RX_DATA00 0x31e
>;
};
pinctrl_sai3: sai3grp {
fsl,pins = <
MX93_PAD_GPIO_IO12__SAI3_RX_SYNC 0x31e
MX93_PAD_GPIO_IO18__SAI3_RX_BCLK 0x31e
MX93_PAD_GPIO_IO17__SAI3_MCLK 0x31e
MX93_PAD_GPIO_IO19__SAI3_TX_DATA00 0x31e
MX93_PAD_GPIO_IO20__SAI3_RX_DATA00 0x31e
>;
};
pinctrl_usdhc2_gpio: usdhc2gpiogrp {
fsl,pins = <
MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e

8
arch/arm64/boot/dts/freescale/imx93.dtsi
View File

@@ -42,6 +42,14 @@ aliases {
serial5 = &lpuart6;
serial6 = &lpuart7;
serial7 = &lpuart8;
spi0 = &lpspi1;
spi1 = &lpspi2;
spi2 = &lpspi3;
spi3 = &lpspi4;
spi4 = &lpspi5;
spi5 = &lpspi6;
spi6 = &lpspi7;
spi7 = &lpspi8;
};
cpus {

86
arch/arm64/boot/dts/freescale/imx95-19x19-evk.dts
View File

@@ -8,11 +8,33 @@
#include <dt-bindings/pwm/pwm.h>
#include "imx95.dtsi"
#define FALLING_EDGE 1
#define RISING_EDGE 2
#define BRD_SM_CTRL_SD3_WAKE 0x8000 /* PCAL6408A-0 */
#define BRD_SM_CTRL_PCIE1_WAKE 0x8001 /* PCAL6408A-4 */
#define BRD_SM_CTRL_BT_WAKE 0x8002 /* PCAL6408A-5 */
#define BRD_SM_CTRL_PCIE2_WAKE 0x8003 /* PCAL6408A-6 */
#define BRD_SM_CTRL_BUTTON 0x8004 /* PCAL6408A-7 */
/ {
model = "NXP i.MX95 19X19 board";
compatible = "fsl,imx95-19x19-evk", "fsl,imx95";
aliases {
gpio0 = &gpio1;
gpio1 = &gpio2;
gpio2 = &gpio3;
gpio3 = &gpio4;
gpio4 = &gpio5;
i2c0 = &lpi2c1;
i2c1 = &lpi2c2;
i2c2 = &lpi2c3;
i2c3 = &lpi2c4;
i2c4 = &lpi2c5;
i2c5 = &lpi2c6;
i2c6 = &lpi2c7;
i2c7 = &lpi2c8;
mmc0 = &usdhc1;
mmc1 = &usdhc2;
serial0 = &lpuart1;
@@ -232,6 +254,42 @@ i2c4_gpio_expander_21: gpio@21 {
};
};
&lpi2c5 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpi2c5>;
status = "okay";
i2c5_pcal6408: gpio@21 {
compatible = "nxp,pcal6408";
reg = <0x21>;
gpio-controller;
#gpio-cells = <2>;
vcc-supply = <&reg_3p3v>;
};
};
&lpi2c6 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpi2c6>;
status = "okay";
i2c6_pcal6416: gpio@21 {
compatible = "nxp,pcal6416";
reg = <0x21>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&gpio4>;
interrupts = <28 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcal6416>;
vcc-supply = <&reg_3p3v>;
};
};
&lpi2c7 {
clock-frequency = <1000000>;
pinctrl-names = "default";
@@ -357,6 +415,14 @@ &usdhc2 {
status = "okay";
};
&scmi_misc {
nxp,ctrl-ids = <BRD_SM_CTRL_SD3_WAKE FALLING_EDGE
BRD_SM_CTRL_PCIE1_WAKE FALLING_EDGE
BRD_SM_CTRL_BT_WAKE FALLING_EDGE
BRD_SM_CTRL_PCIE2_WAKE FALLING_EDGE
BRD_SM_CTRL_BUTTON FALLING_EDGE>;
};
&wdog3 {
fsl,ext-reset-output;
status = "okay";
@@ -410,6 +476,20 @@ IMX95_PAD_GPIO_IO31__LPI2C4_SCL 0x40000b9e
>;
};
pinctrl_lpi2c5: lpi2c5grp {
fsl,pins = <
IMX95_PAD_GPIO_IO22__LPI2C5_SDA 0x40000b9e
IMX95_PAD_GPIO_IO23__LPI2C5_SCL 0x40000b9e
>;
};
pinctrl_lpi2c6: lpi2c6grp {
fsl,pins = <
IMX95_PAD_GPIO_IO02__LPI2C6_SDA 0x40000b9e
IMX95_PAD_GPIO_IO03__LPI2C6_SCL 0x40000b9e
>;
};
pinctrl_lpi2c7: lpi2c7grp {
fsl,pins = <
IMX95_PAD_GPIO_IO08__LPI2C7_SDA 0x40000b9e
@@ -429,6 +509,12 @@ IMX95_PAD_GPIO_IO35__HSIOMIX_TOP_PCIE2_CLKREQ_B 0x4000031e
>;
};
pinctrl_pcal6416: pcal6416grp {
fsl,pins = <
IMX95_PAD_CCM_CLKO3__GPIO4_IO_BIT28 0x31e
>;
};
pinctrl_pdm: pdmgrp {
fsl,pins = <
IMX95_PAD_PDM_CLK__AONMIX_TOP_PDM_CLK 0x31e

68
arch/arm64/boot/dts/freescale/imx95.dtsi
View File

@@ -22,12 +22,27 @@ cpus {
#address-cells = <1>;
#size-cells = <0>;
idle-states {
entry-method = "psci";
cpu_pd_wait: cpu-pd-wait {
compatible = "arm,idle-state";
arm,psci-suspend-param = <0x0010033>;
local-timer-stop;
entry-latency-us = <10000>;
exit-latency-us = <7000>;
min-residency-us = <27000>;
wakeup-latency-us = <15000>;
};
};
A55_0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a55";
reg = <0x0>;
enable-method = "psci";
#cooling-cells = <2>;
cpu-idle-states = <&cpu_pd_wait>;
power-domains = <&scmi_perf IMX95_PERF_A55>;
power-domain-names = "perf";
i-cache-size = <32768>;
@@ -45,6 +60,7 @@ A55_1: cpu@100 {
reg = <0x100>;
enable-method = "psci";
#cooling-cells = <2>;
cpu-idle-states = <&cpu_pd_wait>;
power-domains = <&scmi_perf IMX95_PERF_A55>;
power-domain-names = "perf";
i-cache-size = <32768>;
@@ -62,6 +78,7 @@ A55_2: cpu@200 {
reg = <0x200>;
enable-method = "psci";
#cooling-cells = <2>;
cpu-idle-states = <&cpu_pd_wait>;
power-domains = <&scmi_perf IMX95_PERF_A55>;
power-domain-names = "perf";
i-cache-size = <32768>;
@@ -79,6 +96,7 @@ A55_3: cpu@300 {
reg = <0x300>;
enable-method = "psci";
#cooling-cells = <2>;
cpu-idle-states = <&cpu_pd_wait>;
power-domains = <&scmi_perf IMX95_PERF_A55>;
power-domain-names = "perf";
i-cache-size = <32768>;
@@ -98,6 +116,7 @@ A55_4: cpu@400 {
power-domain-names = "perf";
enable-method = "psci";
#cooling-cells = <2>;
cpu-idle-states = <&cpu_pd_wait>;
i-cache-size = <32768>;
i-cache-line-size = <64>;
i-cache-sets = <128>;
@@ -115,6 +134,7 @@ A55_5: cpu@500 {
power-domain-names = "perf";
enable-method = "psci";
#cooling-cells = <2>;
cpu-idle-states = <&cpu_pd_wait>;
i-cache-size = <32768>;
i-cache-line-size = <64>;
i-cache-sets = <128>;
@@ -293,12 +313,17 @@ scmi {
shmem = <&scmi_buf0>, <&scmi_buf1>;
#address-cells = <1>;
#size-cells = <0>;
arm,max-rx-timeout-ms = <5000>;
scmi_devpd: protocol@11 {
reg = <0x11>;
#power-domain-cells = <1>;
};
scmi_sys_power: protocol@12 {
reg = <0x12>;
};
scmi_perf: protocol@13 {
reg = <0x13>;
#power-domain-cells = <1>;
@@ -318,6 +343,13 @@ scmi_iomuxc: protocol@19 {
reg = <0x19>;
};
scmi_bbm: protocol@81 {
reg = <0x81>;
};
scmi_misc: protocol@84 {
reg = <0x84>;
};
};
};
@@ -334,13 +366,13 @@ a55-thermal {
trips {
cpu_alert0: trip0 {
temperature = <85000>;
temperature = <105000>;
hysteresis = <2000>;
type = "passive";
};
cpu_crit0: trip1 {
temperature = <95000>;
temperature = <125000>;
hysteresis = <2000>;
type = "critical";
};
@@ -359,6 +391,38 @@ map0 {
};
};
};
ana-thermal {
polling-delay-passive = <250>;
polling-delay = <2000>;
thermal-sensors = <&scmi_sensor 0>;
trips {
ana_alert: trip0 {
temperature = <105000>;
hysteresis = <2000>;
type = "passive";
};
ana_crit0: trip1 {
temperature = <125000>;
hysteresis = <2000>;
type = "critical";
};
};
cooling-maps {
map0 {
trip = <&ana_alert>;
cooling-device =
<&A55_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&A55_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&A55_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&A55_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&A55_4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&A55_5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
};
psci {

6
arch/arm64/boot/dts/freescale/mba8mx.dtsi
View File

@@ -100,7 +100,6 @@ panel: panel-lvds {
port {
panel_in_lvds: endpoint {
data-lanes = <1 2 3 4>;
remote-endpoint = <&lvds_bridge_out>;
};
};
@@ -318,11 +317,6 @@ lvds_bridge_out: endpoint {
};
};
&mipi_dsi {
samsung,burst-clock-frequency = <891000000>;
samsung,esc-clock-frequency = <20000000>;
};
&mipi_dsi_out {
data-lanes = <1 2 3 4>;
remote-endpoint = <&lvds_bridge_in>;

153
arch/arm64/boot/dts/freescale/s32g2.dtsi
View File

@@ -162,6 +162,159 @@ jtag-grp4 {
slew-rate = <166>;
};
};
pinctrl_usdhc0: usdhc0grp-pins {
usdhc0-grp0 {
pinmux = <0x2e1>,
<0x381>;
output-enable;
bias-pull-down;
slew-rate = <150>;
};
usdhc0-grp1 {
pinmux = <0x2f1>,
<0x301>,
<0x311>,
<0x321>,
<0x331>,
<0x341>,
<0x351>,
<0x361>,
<0x371>;
output-enable;
input-enable;
bias-pull-up;
slew-rate = <150>;
};
usdhc0-grp2 {
pinmux = <0x391>;
output-enable;
slew-rate = <150>;
};
usdhc0-grp3 {
pinmux = <0x3a0>;
input-enable;
slew-rate = <150>;
};
usdhc0-grp4 {
pinmux = <0x2032>,
<0x2042>,
<0x2052>,
<0x2062>,
<0x2072>,
<0x2082>,
<0x2092>,
<0x20a2>,
<0x20b2>,
<0x20c2>;
};
};
pinctrl_usdhc0_100mhz: usdhc0-100mhzgrp-pins {
usdhc0-100mhz-grp0 {
pinmux = <0x2e1>,
<0x381>;
output-enable;
bias-pull-down;
slew-rate = <150>;
};
usdhc0-100mhz-grp1 {
pinmux = <0x2f1>,
<0x301>,
<0x311>,
<0x321>,
<0x331>,
<0x341>,
<0x351>,
<0x361>,
<0x371>;
output-enable;
input-enable;
bias-pull-up;
slew-rate = <150>;
};
usdhc0-100mhz-grp2 {
pinmux = <0x391>;
output-enable;
slew-rate = <150>;
};
usdhc0-100mhz-grp3 {
pinmux = <0x3a0>;
input-enable;
slew-rate = <150>;
};
usdhc0-100mhz-grp4 {
pinmux = <0x2032>,
<0x2042>,
<0x2052>,
<0x2062>,
<0x2072>,
<0x2082>,
<0x2092>,
<0x20a2>,
<0x20b2>,
<0x20c2>;
};
};
pinctrl_usdhc0_200mhz: usdhc0-200mhzgrp-pins {
usdhc0-200mhz-grp0 {
pinmux = <0x2e1>,
<0x381>;
output-enable;
bias-pull-down;
slew-rate = <208>;
};
usdhc0-200mhz-grp1 {
pinmux = <0x2f1>,
<0x301>,
<0x311>,
<0x321>,
<0x331>,
<0x341>,
<0x351>,
<0x361>,
<0x371>;
output-enable;
input-enable;
bias-pull-up;
slew-rate = <208>;
};
usdhc0-200mhz-grp2 {
pinmux = <0x391>;
output-enable;
slew-rate = <208>;
};
usdhc0-200mhz-grp3 {
pinmux = <0x3a0>;
input-enable;
slew-rate = <208>;
};
usdhc0-200mhz-grp4 {
pinmux = <0x2032>,
<0x2042>,
<0x2052>,
<0x2062>,
<0x2072>,
<0x2082>,
<0x2092>,
<0x20a2>,
<0x20b2>,
<0x20c2>;
};
};
};
uart0: serial@401c8000 {

5
arch/arm64/boot/dts/freescale/s32g274a-evb.dts
View File

@@ -34,6 +34,11 @@ &uart0 {
};
&usdhc0 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc0>;
pinctrl-1 = <&pinctrl_usdhc0_100mhz>;
pinctrl-2 = <&pinctrl_usdhc0_200mhz>;
disable-wp;
no-1-8-v;
status = "okay";
};

13
arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts
View File

@@ -40,6 +40,19 @@ &uart1 {
};
&usdhc0 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc0>;
pinctrl-1 = <&pinctrl_usdhc0_100mhz>;
pinctrl-2 = <&pinctrl_usdhc0_200mhz>;
disable-wp;
/* Remove no-1-8-v to enable higher speed modes for SD card.
* However, this is not enough to enable HS400 or HS200 modes for eMMC.
* In this case, the position of the resistor R797 must be changed
* from A to B before removing the property.
* If the property is removed without changing the resistor position,
* HS*00 may be enabled, but the interface might be unstable because of
* the wrong VCCQ voltage applied to the eMMC.
*/
no-1-8-v;
status = "okay";
};

153
arch/arm64/boot/dts/freescale/s32g3.dtsi
View File

@@ -219,6 +219,159 @@ jtag-grp4 {
slew-rate = <166>;
};
};
pinctrl_usdhc0: usdhc0grp-pins {
usdhc0-grp0 {
pinmux = <0x2e1>,
<0x381>;
output-enable;
bias-pull-down;
slew-rate = <150>;
};
usdhc0-grp1 {
pinmux = <0x2f1>,
<0x301>,
<0x311>,
<0x321>,
<0x331>,
<0x341>,
<0x351>,
<0x361>,
<0x371>;
output-enable;
input-enable;
bias-pull-up;
slew-rate = <150>;
};
usdhc0-grp2 {
pinmux = <0x391>;
output-enable;
slew-rate = <150>;
};
usdhc0-grp3 {
pinmux = <0x3a0>;
input-enable;
slew-rate = <150>;
};
usdhc0-grp4 {
pinmux = <0x2032>,
<0x2042>,
<0x2052>,
<0x2062>,
<0x2072>,
<0x2082>,
<0x2092>,
<0x20a2>,
<0x20b2>,
<0x20c2>;
};
};
pinctrl_usdhc0_100mhz: usdhc0-100mhzgrp-pins {
usdhc0-100mhz-grp0 {
pinmux = <0x2e1>,
<0x381>;
output-enable;
bias-pull-down;
slew-rate = <150>;
};
usdhc0-100mhz-grp1 {
pinmux = <0x2f1>,
<0x301>,
<0x311>,
<0x321>,
<0x331>,
<0x341>,
<0x351>,
<0x361>,
<0x371>;
output-enable;
input-enable;
bias-pull-up;
slew-rate = <150>;
};
usdhc0-100mhz-grp2 {
pinmux = <0x391>;
output-enable;
slew-rate = <150>;
};
usdhc0-100mhz-grp3 {
pinmux = <0x3a0>;
input-enable;
slew-rate = <150>;
};
usdhc0-100mhz-grp4 {
pinmux = <0x2032>,
<0x2042>,
<0x2052>,
<0x2062>,
<0x2072>,
<0x2082>,
<0x2092>,
<0x20a2>,
<0x20b2>,
<0x20c2>;
};
};
pinctrl_usdhc0_200mhz: usdhc0-200mhzgrp-pins {
usdhc0-200mhz-grp0 {
pinmux = <0x2e1>,
<0x381>;
output-enable;
bias-pull-down;
slew-rate = <208>;
};
usdhc0-200mhz-grp1 {
pinmux = <0x2f1>,
<0x301>,
<0x311>,
<0x321>,
<0x331>,
<0x341>,
<0x351>,
<0x361>,
<0x371>;
output-enable;
input-enable;
bias-pull-up;
slew-rate = <208>;
};
usdhc0-200mhz-grp2 {
pinmux = <0x391>;
output-enable;
slew-rate = <208>;
};
usdhc0-200mhz-grp3 {
pinmux = <0x3a0>;
input-enable;
slew-rate = <208>;
};
usdhc0-200mhz-grp4 {
pinmux = <0x2032>,
<0x2042>,
<0x2052>,
<0x2062>,
<0x2072>,
<0x2082>,
<0x2092>,
<0x20a2>,
<0x20b2>,
<0x20c2>;
};
};
};
uart0: serial@401c8000 {

4
arch/arm64/boot/dts/freescale/s32g399a-rdb3.dts
View File

@@ -40,6 +40,10 @@ &uart1 {
};
&usdhc0 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc0>;
pinctrl-1 = <&pinctrl_usdhc0_100mhz>;
pinctrl-2 = <&pinctrl_usdhc0_200mhz>;
bus-width = <8>;
disable-wp;
status = "okay";