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arm64: dts: qcom: sm8650: add cpu interconnect nodes

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Add the interconnect entry for each cpu, with 3 different paths:
- CPU to Last Level Cache Controller (LLCC)
- Last Level Cache Controller (LLCC) to DDR
- L3 Cache from CPU to DDR interface

Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20250211-topic-sm8650-ddr-bw-scaling-v2-2-a0c950540e68@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Neil Armstrong
2025-02-11 13:56:38 +01:00
committed by Bjorn Andersson
parent 62a770da53
commit c9658c3963
1 changed files with 57 additions and 0 deletions
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57
arch/arm64/boot/dts/qcom/sm8650.dtsi
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@@ -15,6 +15,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interconnect/qcom,icc.h>
#include <dt-bindings/interconnect/qcom,sm8650-rpmh.h>
#include <dt-bindings/interconnect/qcom,osm-l3.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/mailbox/qcom-ipcc.h>
#include <dt-bindings/phy/phy-qcom-qmp.h>
@@ -85,6 +86,13 @@ cpu0: cpu@0 {
qcom,freq-domain = <&cpufreq_hw 0>;
interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
&gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>,
<&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
<&epss_l3 MASTER_EPSS_L3_APPS
&epss_l3 SLAVE_EPSS_L3_SHARED>;
#cooling-cells = <2>;
l2_0: l2-cache {
@@ -118,6 +126,13 @@ cpu1: cpu@100 {
qcom,freq-domain = <&cpufreq_hw 0>;
interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
&gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>,
<&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
<&epss_l3 MASTER_EPSS_L3_APPS
&epss_l3 SLAVE_EPSS_L3_SHARED>;
#cooling-cells = <2>;
};
@@ -138,6 +153,13 @@ cpu2: cpu@200 {
qcom,freq-domain = <&cpufreq_hw 3>;
interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
&gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>,
<&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
<&epss_l3 MASTER_EPSS_L3_APPS
&epss_l3 SLAVE_EPSS_L3_SHARED>;
#cooling-cells = <2>;
l2_200: l2-cache {
@@ -165,6 +187,13 @@ cpu3: cpu@300 {
qcom,freq-domain = <&cpufreq_hw 3>;
interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
&gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>,
<&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
<&epss_l3 MASTER_EPSS_L3_APPS
&epss_l3 SLAVE_EPSS_L3_SHARED>;
#cooling-cells = <2>;
};
@@ -185,6 +214,13 @@ cpu4: cpu@400 {
qcom,freq-domain = <&cpufreq_hw 3>;
interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
&gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>,
<&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
<&epss_l3 MASTER_EPSS_L3_APPS
&epss_l3 SLAVE_EPSS_L3_SHARED>;
#cooling-cells = <2>;
l2_400: l2-cache {
@@ -212,6 +248,13 @@ cpu5: cpu@500 {
qcom,freq-domain = <&cpufreq_hw 1>;
interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
&gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>,
<&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
<&epss_l3 MASTER_EPSS_L3_APPS
&epss_l3 SLAVE_EPSS_L3_SHARED>;
#cooling-cells = <2>;
l2_500: l2-cache {
@@ -239,6 +282,13 @@ cpu6: cpu@600 {
qcom,freq-domain = <&cpufreq_hw 1>;
interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
&gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>,
<&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
<&epss_l3 MASTER_EPSS_L3_APPS
&epss_l3 SLAVE_EPSS_L3_SHARED>;
#cooling-cells = <2>;
l2_600: l2-cache {
@@ -266,6 +316,13 @@ cpu7: cpu@700 {
qcom,freq-domain = <&cpufreq_hw 2>;
interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
&gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>,
<&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
<&epss_l3 MASTER_EPSS_L3_APPS
&epss_l3 SLAVE_EPSS_L3_SHARED>;
#cooling-cells = <2>;
l2_700: l2-cache {