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arm64: dts: qcom: sm8650: add OSM L3 node
Add the OSC L3 Cache controller node. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250211-topic-sm8650-ddr-bw-scaling-v2-1-a0c950540e68@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Bjorn Andersson
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97e05bb225
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@@ -5506,6 +5506,16 @@ rpmhpd_opp_turbo_l1: opp-416 {
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};
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};
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epss_l3: interconnect@17d90000 {
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compatible = "qcom,sm8650-epss-l3", "qcom,epss-l3";
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reg = <0 0x17d90000 0 0x1000>;
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clocks = <&bi_tcxo_div2>, <&gcc GCC_GPLL0>;
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clock-names = "xo", "alternate";
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#interconnect-cells = <1>;
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};
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cpufreq_hw: cpufreq@17d91000 {
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compatible = "qcom,sm8650-cpufreq-epss", "qcom,cpufreq-epss";
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reg = <0 0x17d91000 0 0x1000>,
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