mirrors/linux
1
0
Fork 0
mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git synced 2026-05-07 08:03:00 -04:00
Code Issues Packages Projects Releases Wiki Activity

Merge tag 'v5.17-next-dts64' of git://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux into arm/dt

Browse Source 
mt8192
- add clocks to the devices
- add watchdog node
- add power domain controller node

mt8183:
- add pmic (mt6358) key board node
- add JPEG enconder node

mt7986:
- update memory node
- add clock controller for mt7986a version

* tag 'v5.17-next-dts64' of git://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux:
  arm64: dts: mediatek: update mt7986b memory node
  arm64: dts: mediatek: update mt7986a memory node
  arm64: dts: mediatek: add clock support for mt7986a
  arm64: dts: mediatek: Add mt8192 power domains controller
  arm64: dts: mt6358: add mt6358-keys node
  arm64: dts: mt8183: add jpeg enc node for mt8183
  arm64: dts: mt8192: Add watchdog node
  arm64: dts: mediatek: Correct system timer clock of MT8192
  arm64: dts: mediatek: Correct I2C clock of MT8192
  arm64: dts: mediatek: Correct Nor Flash clock of MT8192
  arm64: dts: mediatek: Correct SPI clock of MT8192
  arm64: dts: mediatek: Correct uart clock of MT8192

Link: https://lore.kernel.org/r/c2064dcc-acdc-c86b-5ef7-cb8e7ae3122f@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
2022-03-01 15:08:16 +01:00
parent 29cefaaf2b 809967d76e
commit c723b6b7b7
6 changed files with 350 additions and 47 deletions
Download Patch File Download Diff File Expand all files Collapse all files

12
arch/arm64/boot/dts/mediatek/mt6358.dtsi
View File

@@ -2,6 +2,7 @@
/*
* Copyright (c) 2020 MediaTek Inc.
*/
#include <dt-bindings/input/input.h>
&pwrap {
pmic: mt6358 {
@@ -357,5 +358,16 @@ mt6358_vsim2_reg: ldo_vsim2 {
mt6358rtc: mt6358rtc {
compatible = "mediatek,mt6358-rtc";
};
mt6358keys: mt6358keys {
compatible = "mediatek,mt6358-keys";
power {
linux,keycodes = <KEY_POWER>;
wakeup-source;
};
home {
linux,keycodes = <KEY_HOME>;
};
};
};
};

3
arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts
View File

@@ -19,7 +19,8 @@ chosen {
stdout-path = "serial0:115200n8";
};
memory {
memory@40000000 {
device_type = "memory";
reg = <0 0x40000000 0 0x40000000>;
};
};

68
arch/arm64/boot/dts/mediatek/mt7986a.dtsi
View File

@@ -6,16 +6,18 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/mt7986-clk.h>
/ {
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
system_clk: dummy40m {
clk40m: oscillator@0 {
compatible = "fixed-clock";
clock-frequency = <40000000>;
#clock-cells = <0>;
clock-output-names = "clkxtal";
};
cpus {
@@ -98,6 +100,18 @@ gic: interrupt-controller@c000000 {
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
};
infracfg: infracfg@10001000 {
compatible = "mediatek,mt7986-infracfg", "syscon";
reg = <0 0x10001000 0 0x1000>;
#clock-cells = <1>;
};
topckgen: topckgen@1001b000 {
compatible = "mediatek,mt7986-topckgen", "syscon";
reg = <0 0x1001B000 0 0x1000>;
#clock-cells = <1>;
};
watchdog: watchdog@1001c000 {
compatible = "mediatek,mt7986-wdt",
"mediatek,mt6589-wdt";
@@ -107,6 +121,12 @@ watchdog: watchdog@1001c000 {
status = "disabled";
};
apmixedsys: apmixedsys@1001e000 {
compatible = "mediatek,mt7986-apmixedsys";
reg = <0 0x1001E000 0 0x1000>;
#clock-cells = <1>;
};
pio: pinctrl@1001f000 {
compatible = "mediatek,mt7986a-pinctrl";
reg = <0 0x1001f000 0 0x1000>,
@@ -128,11 +148,25 @@ pio: pinctrl@1001f000 {
#interrupt-cells = <2>;
};
sgmiisys0: syscon@10060000 {
compatible = "mediatek,mt7986-sgmiisys_0",
"syscon";
reg = <0 0x10060000 0 0x1000>;
#clock-cells = <1>;
};
sgmiisys1: syscon@10070000 {
compatible = "mediatek,mt7986-sgmiisys_1",
"syscon";
reg = <0 0x10070000 0 0x1000>;
#clock-cells = <1>;
};
trng: trng@1020f000 {
compatible = "mediatek,mt7986-rng",
"mediatek,mt7623-rng";
reg = <0 0x1020f000 0 0x100>;
clocks = <&system_clk>;
clocks = <&infracfg CLK_INFRA_TRNG_CK>;
clock-names = "rng";
status = "disabled";
};
@@ -142,7 +176,13 @@ uart0: serial@11002000 {
"mediatek,mt6577-uart";
reg = <0 0x11002000 0 0x400>;
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&system_clk>;
clocks = <&infracfg CLK_INFRA_UART0_SEL>,
<&infracfg CLK_INFRA_UART0_CK>;
clock-names = "baud", "bus";
assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
<&infracfg CLK_INFRA_UART0_SEL>;
assigned-clock-parents = <&topckgen CLK_TOP_XTAL>,
<&topckgen CLK_TOP_UART_SEL>;
status = "disabled";
};
@@ -151,7 +191,11 @@ uart1: serial@11003000 {
"mediatek,mt6577-uart";
reg = <0 0x11003000 0 0x400>;
interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&system_clk>;
clocks = <&infracfg CLK_INFRA_UART1_SEL>,
<&infracfg CLK_INFRA_UART1_CK>;
clock-names = "baud", "bus";
assigned-clocks = <&infracfg CLK_INFRA_UART1_SEL>;
assigned-clock-parents = <&topckgen CLK_TOP_F26M_SEL>;
status = "disabled";
};
@@ -160,10 +204,24 @@ uart2: serial@11004000 {
"mediatek,mt6577-uart";
reg = <0 0x11004000 0 0x400>;
interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&system_clk>;
clocks = <&infracfg CLK_INFRA_UART2_SEL>,
<&infracfg CLK_INFRA_UART2_CK>;
clock-names = "baud", "bus";
assigned-clocks = <&infracfg CLK_INFRA_UART2_SEL>;
assigned-clock-parents = <&topckgen CLK_TOP_F26M_SEL>;
status = "disabled";
};
ethsys: syscon@15000000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "mediatek,mt7986-ethsys",
"syscon";
reg = <0 0x15000000 0 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
};
};
};

3
arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts
View File

@@ -19,7 +19,8 @@ chosen {
stdout-path = "serial0:115200n8";
};
memory {
memory@40000000 {
device_type = "memory";
reg = <0 0x40000000 0 0x40000000>;
};
};

12
arch/arm64/boot/dts/mediatek/mt8183.dtsi
View File

@@ -1594,6 +1594,18 @@ larb4: larb@17010000 {
power-domains = <&spm MT8183_POWER_DOMAIN_VENC>;
};
venc_jpg: venc_jpg@17030000 {
compatible = "mediatek,mt8183-jpgenc", "mediatek,mtk-jpgenc";
reg = <0 0x17030000 0 0x1000>;
interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_LOW>;
mediatek,larb = <&larb4>;
iommus = <&iommu M4U_PORT_JPGENC_RDMA>,
<&iommu M4U_PORT_JPGENC_BSDMA>;
power-domains = <&spm MT8183_POWER_DOMAIN_VENC>;
clocks = <&vencsys CLK_VENC_JPGENC>;
clock-names = "jpgenc";
};
ipu_conn: syscon@19000000 {
compatible = "mediatek,mt8183-ipu_conn", "syscon";
reg = <0 0x19000000 0 0x1000>;

299
arch/arm64/boot/dts/mediatek/mt8192.dtsi
View File

@@ -9,6 +9,7 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pinctrl/mt8192-pinfunc.h>
#include <dt-bindings/power/mt8192-power.h>
/ {
compatible = "mediatek,mt8192";
@@ -301,6 +302,212 @@ pio: pinctrl@10005000 {
#interrupt-cells = <2>;
};
scpsys: syscon@10006000 {
compatible = "syscon", "simple-mfd";
reg = <0 0x10006000 0 0x1000>;
#power-domain-cells = <1>;
/* System Power Manager */
spm: power-controller {
compatible = "mediatek,mt8192-power-controller";
#address-cells = <1>;
#size-cells = <0>;
#power-domain-cells = <1>;
/* power domain of the SoC */
power-domain@MT8192_POWER_DOMAIN_AUDIO {
reg = <MT8192_POWER_DOMAIN_AUDIO>;
clocks = <&topckgen CLK_TOP_AUD_INTBUS_SEL>,
<&infracfg CLK_INFRA_AUDIO_26M_B>,
<&infracfg CLK_INFRA_AUDIO>;
clock-names = "audio", "audio1", "audio2";
mediatek,infracfg = <&infracfg>;
#power-domain-cells = <0>;
};
power-domain@MT8192_POWER_DOMAIN_CONN {
reg = <MT8192_POWER_DOMAIN_CONN>;
clocks = <&infracfg CLK_INFRA_PMIC_CONN>;
clock-names = "conn";
mediatek,infracfg = <&infracfg>;
#power-domain-cells = <0>;
};
power-domain@MT8192_POWER_DOMAIN_MFG0 {
reg = <MT8192_POWER_DOMAIN_MFG0>;
clocks = <&topckgen CLK_TOP_MFG_PLL_SEL>;
clock-names = "mfg";
#address-cells = <1>;
#size-cells = <0>;
#power-domain-cells = <1>;
power-domain@MT8192_POWER_DOMAIN_MFG1 {
reg = <MT8192_POWER_DOMAIN_MFG1>;
mediatek,infracfg = <&infracfg>;
#address-cells = <1>;
#size-cells = <0>;
#power-domain-cells = <1>;
power-domain@MT8192_POWER_DOMAIN_MFG2 {
reg = <MT8192_POWER_DOMAIN_MFG2>;
#power-domain-cells = <0>;
};
power-domain@MT8192_POWER_DOMAIN_MFG3 {
reg = <MT8192_POWER_DOMAIN_MFG3>;
#power-domain-cells = <0>;
};
power-domain@MT8192_POWER_DOMAIN_MFG4 {
reg = <MT8192_POWER_DOMAIN_MFG4>;
#power-domain-cells = <0>;
};
power-domain@MT8192_POWER_DOMAIN_MFG5 {
reg = <MT8192_POWER_DOMAIN_MFG5>;
#power-domain-cells = <0>;
};
power-domain@MT8192_POWER_DOMAIN_MFG6 {
reg = <MT8192_POWER_DOMAIN_MFG6>;
#power-domain-cells = <0>;
};
};
};
power-domain@MT8192_POWER_DOMAIN_DISP {
reg = <MT8192_POWER_DOMAIN_DISP>;
clocks = <&topckgen CLK_TOP_DISP_SEL>,
<&mmsys CLK_MM_SMI_INFRA>,
<&mmsys CLK_MM_SMI_COMMON>,
<&mmsys CLK_MM_SMI_GALS>,
<&mmsys CLK_MM_SMI_IOMMU>;
clock-names = "disp", "disp-0", "disp-1", "disp-2",
"disp-3";
mediatek,infracfg = <&infracfg>;
#address-cells = <1>;
#size-cells = <0>;
#power-domain-cells = <1>;
power-domain@MT8192_POWER_DOMAIN_IPE {
reg = <MT8192_POWER_DOMAIN_IPE>;
clocks = <&topckgen CLK_TOP_IPE_SEL>,
<&ipesys CLK_IPE_LARB19>,
<&ipesys CLK_IPE_LARB20>,
<&ipesys CLK_IPE_SMI_SUBCOM>,
<&ipesys CLK_IPE_GALS>;
clock-names = "ipe", "ipe-0", "ipe-1", "ipe-2",
"ipe-3";
mediatek,infracfg = <&infracfg>;
#power-domain-cells = <0>;
};
power-domain@MT8192_POWER_DOMAIN_ISP {
reg = <MT8192_POWER_DOMAIN_ISP>;
clocks = <&topckgen CLK_TOP_IMG1_SEL>,
<&imgsys CLK_IMG_LARB9>,
<&imgsys CLK_IMG_GALS>;
clock-names = "isp", "isp-0", "isp-1";
mediatek,infracfg = <&infracfg>;
#power-domain-cells = <0>;
};
power-domain@MT8192_POWER_DOMAIN_ISP2 {
reg = <MT8192_POWER_DOMAIN_ISP2>;
clocks = <&topckgen CLK_TOP_IMG2_SEL>,
<&imgsys2 CLK_IMG2_LARB11>,
<&imgsys2 CLK_IMG2_GALS>;
clock-names = "isp2", "isp2-0", "isp2-1";
mediatek,infracfg = <&infracfg>;
#power-domain-cells = <0>;
};
power-domain@MT8192_POWER_DOMAIN_MDP {
reg = <MT8192_POWER_DOMAIN_MDP>;
clocks = <&topckgen CLK_TOP_MDP_SEL>,
<&mdpsys CLK_MDP_SMI0>;
clock-names = "mdp", "mdp-0";
mediatek,infracfg = <&infracfg>;
#power-domain-cells = <0>;
};
power-domain@MT8192_POWER_DOMAIN_VENC {
reg = <MT8192_POWER_DOMAIN_VENC>;
clocks = <&topckgen CLK_TOP_VENC_SEL>,
<&vencsys CLK_VENC_SET1_VENC>;
clock-names = "venc", "venc-0";
mediatek,infracfg = <&infracfg>;
#power-domain-cells = <0>;
};
power-domain@MT8192_POWER_DOMAIN_VDEC {
reg = <MT8192_POWER_DOMAIN_VDEC>;
clocks = <&topckgen CLK_TOP_VDEC_SEL>,
<&vdecsys_soc CLK_VDEC_SOC_VDEC>,
<&vdecsys_soc CLK_VDEC_SOC_LAT>,
<&vdecsys_soc CLK_VDEC_SOC_LARB1>;
clock-names = "vdec", "vdec-0", "vdec-1", "vdec-2";
mediatek,infracfg = <&infracfg>;
#address-cells = <1>;
#size-cells = <0>;
#power-domain-cells = <1>;
power-domain@MT8192_POWER_DOMAIN_VDEC2 {
reg = <MT8192_POWER_DOMAIN_VDEC2>;
clocks = <&vdecsys CLK_VDEC_VDEC>,
<&vdecsys CLK_VDEC_LAT>,
<&vdecsys CLK_VDEC_LARB1>;
clock-names = "vdec2-0", "vdec2-1",
"vdec2-2";
#power-domain-cells = <0>;
};
};
power-domain@MT8192_POWER_DOMAIN_CAM {
reg = <MT8192_POWER_DOMAIN_CAM>;
clocks = <&topckgen CLK_TOP_CAM_SEL>,
<&camsys CLK_CAM_LARB13>,
<&camsys CLK_CAM_LARB14>,
<&camsys CLK_CAM_CCU_GALS>,
<&camsys CLK_CAM_CAM2MM_GALS>;
clock-names = "cam", "cam-0", "cam-1", "cam-2",
"cam-3";
mediatek,infracfg = <&infracfg>;
#address-cells = <1>;
#size-cells = <0>;
#power-domain-cells = <1>;
power-domain@MT8192_POWER_DOMAIN_CAM_RAWA {
reg = <MT8192_POWER_DOMAIN_CAM_RAWA>;
clocks = <&camsys_rawa CLK_CAM_RAWA_LARBX>;
clock-names = "cam_rawa-0";
#power-domain-cells = <0>;
};
power-domain@MT8192_POWER_DOMAIN_CAM_RAWB {
reg = <MT8192_POWER_DOMAIN_CAM_RAWB>;
clocks = <&camsys_rawb CLK_CAM_RAWB_LARBX>;
clock-names = "cam_rawb-0";
#power-domain-cells = <0>;
};
power-domain@MT8192_POWER_DOMAIN_CAM_RAWC {
reg = <MT8192_POWER_DOMAIN_CAM_RAWC>;
clocks = <&camsys_rawc CLK_CAM_RAWC_LARBX>;
clock-names = "cam_rawc-0";
#power-domain-cells = <0>;
};
};
};
};
};
watchdog: watchdog@10007000 {
compatible = "mediatek,mt8192-wdt";
reg = <0 0x10007000 0 0x100>;
#reset-cells = <1>;
};
apmixedsys: syscon@1000c000 {
compatible = "mediatek,mt8192-apmixedsys", "syscon";
reg = <0 0x1000c000 0 0x1000>;
@@ -312,7 +519,7 @@ systimer: timer@10017000 {
"mediatek,mt6765-timer";
reg = <0 0x10017000 0 0x1000>;
interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&clk26m>;
clocks = <&topckgen CLK_TOP_CSW_F26M_D2>;
clock-names = "clk13m";
};
@@ -327,7 +534,7 @@ uart0: serial@11002000 {
"mediatek,mt6577-uart";
reg = <0 0x11002000 0 0x1000>;
interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&clk26m>, <&clk26m>;
clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>;
clock-names = "baud", "bus";
status = "disabled";
};
@@ -337,7 +544,7 @@ uart1: serial@11003000 {
"mediatek,mt6577-uart";
reg = <0 0x11003000 0 0x1000>;
interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&clk26m>, <&clk26m>;
clocks = <&clk26m>, <&infracfg CLK_INFRA_UART1>;
clock-names = "baud", "bus";
status = "disabled";
};
@@ -355,9 +562,9 @@ spi0: spi@1100a000 {
#size-cells = <0>;
reg = <0 0x1100a000 0 0x1000>;
interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&clk26m>,
<&clk26m>,
<&clk26m>;
clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>,
<&topckgen CLK_TOP_SPI_SEL>,
<&infracfg CLK_INFRA_SPI0>;
clock-names = "parent-clk", "sel-clk", "spi-clk";
status = "disabled";
};
@@ -369,9 +576,9 @@ spi1: spi@11010000 {
#size-cells = <0>;
reg = <0 0x11010000 0 0x1000>;
interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&clk26m>,
<&clk26m>,
<&clk26m>;
clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>,
<&topckgen CLK_TOP_SPI_SEL>,
<&infracfg CLK_INFRA_SPI1>;
clock-names = "parent-clk", "sel-clk", "spi-clk";
status = "disabled";
};
@@ -383,9 +590,9 @@ spi2: spi@11012000 {
#size-cells = <0>;
reg = <0 0x11012000 0 0x1000>;
interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&clk26m>,
<&clk26m>,
<&clk26m>;
clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>,
<&topckgen CLK_TOP_SPI_SEL>,
<&infracfg CLK_INFRA_SPI2>;
clock-names = "parent-clk", "sel-clk", "spi-clk";
status = "disabled";
};
@@ -397,9 +604,9 @@ spi3: spi@11013000 {
#size-cells = <0>;
reg = <0 0x11013000 0 0x1000>;
interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&clk26m>,
<&clk26m>,
<&clk26m>;
clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>,
<&topckgen CLK_TOP_SPI_SEL>,
<&infracfg CLK_INFRA_SPI3>;
clock-names = "parent-clk", "sel-clk", "spi-clk";
status = "disabled";
};
@@ -411,9 +618,9 @@ spi4: spi@11018000 {
#size-cells = <0>;
reg = <0 0x11018000 0 0x1000>;
interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&clk26m>,
<&clk26m>,
<&clk26m>;
clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>,
<&topckgen CLK_TOP_SPI_SEL>,
<&infracfg CLK_INFRA_SPI4>;
clock-names = "parent-clk", "sel-clk", "spi-clk";
status = "disabled";
};
@@ -425,9 +632,9 @@ spi5: spi@11019000 {
#size-cells = <0>;
reg = <0 0x11019000 0 0x1000>;
interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&clk26m>,
<&clk26m>,
<&clk26m>;
clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>,
<&topckgen CLK_TOP_SPI_SEL>,
<&infracfg CLK_INFRA_SPI5>;
clock-names = "parent-clk", "sel-clk", "spi-clk";
status = "disabled";
};
@@ -439,9 +646,9 @@ spi6: spi@1101d000 {
#size-cells = <0>;
reg = <0 0x1101d000 0 0x1000>;
interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&clk26m>,
<&clk26m>,
<&clk26m>;
clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>,
<&topckgen CLK_TOP_SPI_SEL>,
<&infracfg CLK_INFRA_SPI6>;
clock-names = "parent-clk", "sel-clk", "spi-clk";
status = "disabled";
};
@@ -453,9 +660,9 @@ spi7: spi@1101e000 {
#size-cells = <0>;
reg = <0 0x1101e000 0 0x1000>;
interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&clk26m>,
<&clk26m>,
<&clk26m>;
clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>,
<&topckgen CLK_TOP_SPI_SEL>,
<&infracfg CLK_INFRA_SPI7>;
clock-names = "parent-clk", "sel-clk", "spi-clk";
status = "disabled";
};
@@ -464,10 +671,12 @@ nor_flash: spi@11234000 {
compatible = "mediatek,mt8192-nor";
reg = <0 0x11234000 0 0xe0>;
interrupts = <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&clk26m>,
<&clk26m>,
<&clk26m>;
clocks = <&topckgen CLK_TOP_SFLASH_SEL>,
<&infracfg CLK_INFRA_FLASHIF_SFLASH>,
<&infracfg CLK_INFRA_FLASHIF_TOP_H_133M>;
clock-names = "spi", "sf", "axi";
assigned-clocks = <&topckgen CLK_TOP_SFLASH_SEL>;
assigned-clock-parents = <&clk26m>;
#address-cells = <1>;
#size-cells = <0>;
status = "disable";
@@ -484,7 +693,8 @@ i2c3: i2c@11cb0000 {
reg = <0 0x11cb0000 0 0x1000>,
<0 0x10217300 0 0x80>;
interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&clk26m>, <&clk26m>;
clocks = <&imp_iic_wrap_e CLK_IMP_IIC_WRAP_E_I2C3>,
<&infracfg CLK_INFRA_AP_DMA>;
clock-names = "main", "dma";
clock-div = <1>;
#address-cells = <1>;
@@ -503,7 +713,8 @@ i2c7: i2c@11d00000 {
reg = <0 0x11d00000 0 0x1000>,
<0 0x10217600 0 0x180>;
interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&clk26m>, <&clk26m>;
clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C7>,
<&infracfg CLK_INFRA_AP_DMA>;
clock-names = "main", "dma";
clock-div = <1>;
#address-cells = <1>;
@@ -516,7 +727,8 @@ i2c8: i2c@11d01000 {
reg = <0 0x11d01000 0 0x1000>,
<0 0x10217780 0 0x180>;
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&clk26m>, <&clk26m>;
clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C8>,
<&infracfg CLK_INFRA_AP_DMA>;
clock-names = "main", "dma";
clock-div = <1>;
#address-cells = <1>;
@@ -529,7 +741,8 @@ i2c9: i2c@11d02000 {
reg = <0 0x11d02000 0 0x1000>,
<0 0x10217900 0 0x180>;
interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&clk26m>, <&clk26m>;
clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C9>,
<&infracfg CLK_INFRA_AP_DMA>;
clock-names = "main", "dma";
clock-div = <1>;
#address-cells = <1>;
@@ -548,7 +761,8 @@ i2c1: i2c@11d20000 {
reg = <0 0x11d20000 0 0x1000>,
<0 0x10217100 0 0x80>;
interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&clk26m>, <&clk26m>;
clocks = <&imp_iic_wrap_ws CLK_IMP_IIC_WRAP_WS_I2C1>,
<&infracfg CLK_INFRA_AP_DMA>;
clock-names = "main", "dma";
clock-div = <1>;
#address-cells = <1>;
@@ -561,7 +775,8 @@ i2c2: i2c@11d21000 {
reg = <0 0x11d21000 0 0x1000>,
<0 0x10217180 0 0x180>;
interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&clk26m>, <&clk26m>;
clocks = <&imp_iic_wrap_ws CLK_IMP_IIC_WRAP_WS_I2C2>,
<&infracfg CLK_INFRA_AP_DMA>;
clock-names = "main", "dma";
clock-div = <1>;
#address-cells = <1>;
@@ -574,7 +789,8 @@ i2c4: i2c@11d22000 {
reg = <0 0x11d22000 0 0x1000>,
<0 0x10217380 0 0x180>;
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&clk26m>, <&clk26m>;
clocks = <&imp_iic_wrap_ws CLK_IMP_IIC_WRAP_WS_I2C4>,
<&infracfg CLK_INFRA_AP_DMA>;
clock-names = "main", "dma";
clock-div = <1>;
#address-cells = <1>;
@@ -593,7 +809,8 @@ i2c5: i2c@11e00000 {
reg = <0 0x11e00000 0 0x1000>,
<0 0x10217500 0 0x80>;
interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&clk26m>, <&clk26m>;
clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C5>,
<&infracfg CLK_INFRA_AP_DMA>;
clock-names = "main", "dma";
clock-div = <1>;
#address-cells = <1>;
@@ -612,7 +829,8 @@ i2c0: i2c@11f00000 {
reg = <0 0x11f00000 0 0x1000>,
<0 0x10217080 0 0x80>;
interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&clk26m>, <&clk26m>;
clocks = <&imp_iic_wrap_n CLK_IMP_IIC_WRAP_N_I2C0>,
<&infracfg CLK_INFRA_AP_DMA>;
clock-names = "main", "dma";
clock-div = <1>;
#address-cells = <1>;
@@ -625,7 +843,8 @@ i2c6: i2c@11f01000 {
reg = <0 0x11f01000 0 0x1000>,
<0 0x10217580 0 0x80>;
interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&clk26m>, <&clk26m>;
clocks = <&imp_iic_wrap_n CLK_IMP_IIC_WRAP_N_I2C6>,
<&infracfg CLK_INFRA_AP_DMA>;
clock-names = "main", "dma";
clock-div = <1>;
#address-cells = <1>;