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Merge tag 'qcom-arm64-for-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into arm/dt

Browse Source 
Qualcomm ARM64 DeviceTree updates for v5.18

New platforms: Snapdragon 625 and Snapdragon 632
New boards: Google Herobrine R1, Fairphone FP3, SHIFT6mq, Samsung Galaxy
Book2 and Snapdragon 8 Gen 1 Hardware Development Kit (HDK)

On IPQ6018 the USB reference period is corrected, GICv2m support is
enabled and the max-link-speed for PCIe is specified.

IPQ8074 adds description of GIVv2m and SMEM, and ensures that TrustZone
related memory is reserved from Linux.

On the Snapdragon 7c Gen 3 (SC7280) description of display, displayport,
L3 interconnect, bluetooth, CPU opp-tables are added. Another revision
of the Google Herobrine is introduced and a bunch of cleanups are
introduced.

On Snapdragon 845 new support for the SHIFT6mq device is introduced, the
OnePlus devices gains fuel gauge and the platform gains GSI DMA support,
which is enabled for SPI (for now).

On the Snapdragon 850 based WindowsOnSnapdragon laptops, initial support
for Samsugn Galaxy Book2 is introduced and the Lenovo Yoga C630 gains
description of its backlight controls.

The Snapdragon 625 platform (MSM8953) the thereof derrived Snapdragon
632 platform is introduced, with initial description of the Fairphone 3.

Fairphone 4 on the SM7225 platform gains proper WLED configuration.

On Snapdragon 855 (SM8150) description of the limits hardware (LMh) is
introduced and the SPI and I2C devices are wired to the GSI DMA controller.

On Snapdragon 865 (SM8250) the CPU and cluster idle states are
introduced, the MSI interrupts for PCIe 1 and 2 are corrected and the
CPUfreq driver gains knowledge about thermal pressure interrupts.

On Snapdragon 8 Gen 1 (SM8450) LLCC, interconnect and remoteproc
descriptions are added. The SM8450 Hardware Development Kit is
introduced and the QRD has its remoteproc instances enabled.

Cluster idle and RPMh parameters are corrected on SM8150, SM8350 and
SM8540.

The IPA device on SC7180, SC7280 and SM8350 gains knowledge of the AOSS
QMP mailbox, allowing it to enable retention of IPA registers during
power collapse.

DeviceTree validation issues related to thermal zone naming, missing
CPU, device and platform compatibles, APR, Google EC PWM, DB410c sound,
QCS404 opp-tables and SM8250 PCIe nodes are corrected.

A bunch of cleanups and style fixes for MSM8992, MSM8994, MSM8996 and
MSM8916 are introduced as well.

* tag 'qcom-arm64-for-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (96 commits)
  arm64: dts: qcom: sdm632: Add device tree for Fairphone 3
  dt-bindings: arm: qcom: Document sdm632 and fairphone,fp3 board
  arm64: dts: qcom: Add SDM632 device tree
  arm64: dts: qcom: Add PM8953 PMIC
  arm64: dts: qcom: Add MSM8953 device tree
  dt-bindings: arm: cpus: Add Kryo 250 CPUs
  arm64: dts: qcom: msm8916-longcheer-l8150: Add light and proximity sensor
  arm64: dts: qcom: align Google CROS EC PWM node name with dtschema
  arm64: dts: qcom: Add support for Samsung Galaxy Book2
  arm64: dts: qcom: msm8996: convert xo_board to RPM_SMD_BB_CLK1
  arm64: dts: qcom: msm8996: add cxo and sleep-clk to gcc node
  arm64: dts: qcom: sdm845: add bi_tcxo to camcc
  arm64: dts: qcom: sdm845: enable dma for spi
  arm64: dts: qcom: sdm845: Add gsi dma node
  arm64: dts: qcom: sc7280: Add cpu OPP tables
  arm64: dts: qcom: sc7280: Add EPSS L3 interconnect provider
  arm64: dts: qcom: sm8450: Add LLCC/system-cache-controller node
  arm64: dts: qcom: ipq6018: drop the clock-frequency property
  arm64: dts: qcom: ipq8074: drop the clock-frequency property
  arm64: dts: qcom: sm8450: add interconnect nodes
  ...

Link: https://lore.kernel.org/r/20220301053929.1809684-1-bjorn.andersson@linaro.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
2022-03-01 11:12:25 +01:00
parent 40c13296f8 308b26cddb
commit 29cefaaf2b
59 changed files with 8204 additions and 1321 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
Documentation/devicetree/bindings/arm/cpus.yaml
View File

@@ -173,6 +173,7 @@ properties:
- nvidia,tegra194-carmel
- qcom,krait
- qcom,kryo
- qcom,kryo250
- qcom,kryo260
- qcom,kryo280
- qcom,kryo385

23
Documentation/devicetree/bindings/arm/qcom.yaml
View File

@@ -42,6 +42,7 @@ description: |
sc7180
sc7280
sdm630
sdm632
sdm660
sdm845
sdx55
@@ -173,7 +174,21 @@ properties:
- const: qcom,apq8094
- items:
- const: qcom,msm8996-mtp
- enum:
- arrow,apq8096-db820c
- inforce,ifc6640
- const: qcom,apq8096-sbc
- const: qcom,apq8096
- items:
- enum:
- qcom,msm8996-mtp
- sony,dora-row
- sony,kagura-row
- sony,keyaki-row
- xiaomi,gemini
- xiaomi,scorpio
- const: qcom,msm8996
- items:
- enum:
@@ -211,6 +226,11 @@ properties:
- google,senor
- const: qcom,sc7280
- items:
- enum:
- fairphone,fp3
- const: qcom,sdm632
- items:
- enum:
- xiaomi,lavender
@@ -268,6 +288,7 @@ properties:
- items:
- enum:
- qcom,sm8450-hdk
- qcom,sm8450-qrd
- const: qcom,sm8450

12
arch/arm64/boot/dts/qcom/Makefile
View File

@@ -18,10 +18,11 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-a5u-eur.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-j5.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8916-samsung-serranove.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8916-wingtech-wt88047.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8992-bullhead-rev-101.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8992-lg-bullhead-rev-10.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8992-lg-bullhead-rev-101.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8992-msft-lumia-octagon-talkman.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8992-xiaomi-libra.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8994-angler-rev-101.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8994-huawei-angler-rev-101.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8994-msft-lumia-octagon-cityman.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8994-sony-xperia-kitakami-ivy.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8994-sony-xperia-kitakami-karin.dtb
@@ -82,7 +83,8 @@ dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pompom-r3.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-pompom-r3-lte.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-r1.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7180-trogdor-r1-lte.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7280-herobrine.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7280-herobrine-herobrine-r0.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7280-herobrine-herobrine-r1.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7280-idp.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7280-idp2.dtb
dtb-$(CONFIG_ARCH_QCOM) += sc7280-crd.dtb
@@ -90,6 +92,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sdm630-sony-xperia-ganges-kirin.dtb
dtb-$(CONFIG_ARCH_QCOM) += sdm630-sony-xperia-nile-discovery.dtb
dtb-$(CONFIG_ARCH_QCOM) += sdm630-sony-xperia-nile-pioneer.dtb
dtb-$(CONFIG_ARCH_QCOM) += sdm630-sony-xperia-nile-voyager.dtb
dtb-$(CONFIG_ARCH_QCOM) += sdm632-fairphone-fp3.dtb
dtb-$(CONFIG_ARCH_QCOM) += sdm636-sony-xperia-ganges-mermaid.dtb
dtb-$(CONFIG_ARCH_QCOM) += sdm660-xiaomi-lavender.dtb
dtb-$(CONFIG_ARCH_QCOM) += sdm845-cheza-r1.dtb
@@ -103,7 +106,9 @@ dtb-$(CONFIG_ARCH_QCOM) += sdm845-sony-xperia-tama-akari.dtb
dtb-$(CONFIG_ARCH_QCOM) += sdm845-sony-xperia-tama-akatsuki.dtb
dtb-$(CONFIG_ARCH_QCOM) += sdm845-sony-xperia-tama-apollo.dtb
dtb-$(CONFIG_ARCH_QCOM) += sdm845-xiaomi-beryllium.dtb
dtb-$(CONFIG_ARCH_QCOM) += sdm845-shift-axolotl.dtb
dtb-$(CONFIG_ARCH_QCOM) += sdm850-lenovo-yoga-c630.dtb
dtb-$(CONFIG_ARCH_QCOM) += sdm850-samsung-w737.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm6125-sony-xperia-seine-pdx201.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm6350-sony-xperia-lena-pdx213.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm7225-fairphone-fp4.dtb
@@ -121,4 +126,5 @@ dtb-$(CONFIG_ARCH_QCOM) += sm8350-microsoft-surface-duo2.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8350-mtp.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8350-sony-xperia-sagami-pdx214.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8350-sony-xperia-sagami-pdx215.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8450-hdk.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8450-qrd.dtb

12
arch/arm64/boot/dts/qcom/apq8016-sbc.dts
View File

@@ -253,7 +253,6 @@ ports {
port@0 {
reg = <0>;
csiphy0_ep: endpoint {
clock-lanes = <1>;
data-lanes = <0 2>;
remote-endpoint = <&ov5640_ep>;
status = "okay";
@@ -289,7 +288,6 @@ camera_rear@3b {
port {
ov5640_ep: endpoint {
clock-lanes = <1>;
data-lanes = <0 2>;
remote-endpoint = <&csiphy0_ep>;
};
@@ -351,12 +349,12 @@ &sound {
pinctrl-0 = <&cdc_pdm_lines_act &ext_sec_tlmm_lines_act &ext_mclk_tlmm_lines_act>;
pinctrl-1 = <&cdc_pdm_lines_sus &ext_sec_tlmm_lines_sus &ext_mclk_tlmm_lines_sus>;
pinctrl-names = "default", "sleep";
qcom,model = "DB410c";
qcom,audio-routing =
model = "DB410c";
audio-routing =
"AMIC2", "MIC BIAS Internal2",
"AMIC3", "MIC BIAS External1";
external-dai-link@0 {
quaternary-dai-link {
link-name = "ADV7533";
cpu {
sound-dai = <&lpass MI2S_QUATERNARY>;
@@ -366,7 +364,7 @@ codec {
};
};
internal-codec-playback-dai-link@0 {
primary-dai-link {
link-name = "WCD";
cpu {
sound-dai = <&lpass MI2S_PRIMARY>;
@@ -376,7 +374,7 @@ codec {
};
};
internal-codec-capture-dai-link@0 {
tertiary-dai-link {
link-name = "WCD-Capture";
cpu {
sound-dai = <&lpass MI2S_TERTIARY>;

13
arch/arm64/boot/dts/qcom/ipq6018.dtsi
View File

@@ -373,6 +373,8 @@ qpic_nand: nand@79b0000 {
intc: interrupt-controller@b000000 {
compatible = "qcom,msm-qgic2";
#address-cells = <2>;
#size-cells = <2>;
interrupt-controller;
#interrupt-cells = <0x3>;
reg = <0x0 0x0b000000 0x0 0x1000>, /*GICD*/
@@ -380,6 +382,13 @@ intc: interrupt-controller@b000000 {
<0x0 0x0b001000 0x0 0x1000>, /*GICH*/
<0x0 0x0b004000 0x0 0x1000>; /*GICV*/
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
ranges = <0 0 0 0xb00a000 0 0xffd>;
v2m@0 {
compatible = "arm,gic-v2m-frame";
msi-controller;
reg = <0x0 0x0 0x0 0xffd>;
};
};
pcie_phy: phy@84000 {
@@ -425,6 +434,7 @@ pcie0: pci@20000000 {
linux,pci-domain = <0>;
bus-range = <0x00 0xff>;
num-lanes = <1>;
max-link-speed = <3>;
#address-cells = <3>;
#size-cells = <2>;
@@ -520,7 +530,6 @@ timer@b120000 {
ranges;
compatible = "arm,armv7-timer-mem";
reg = <0x0 0x0b120000 0x0 0x1000>;
clock-frequency = <19200000>;
frame@b120000 {
frame-number = <0>;
@@ -748,7 +757,7 @@ dwc_0: usb@8A00000 {
snps,hird-threshold = /bits/ 8 <0x0>;
snps,dis_u2_susphy_quirk;
snps,dis_u3_susphy_quirk;
snps,ref-clock-period-ns = <0x32>;
snps,ref-clock-period-ns = <0x29>;
dr_mode = "host";
};
};

35
arch/arm64/boot/dts/qcom/ipq8074.dtsi
View File

@@ -76,6 +76,25 @@ psci {
method = "smc";
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
smem@4ab00000 {
compatible = "qcom,smem";
reg = <0x0 0x4ab00000 0x0 0x00100000>;
no-map;
hwlocks = <&tcsr_mutex 0>;
};
memory@4ac00000 {
no-map;
reg = <0x0 0x4ac00000 0x0 0x00400000>;
};
};
firmware {
scm {
compatible = "qcom,scm-ipq8074", "qcom,scm";
@@ -331,6 +350,12 @@ gcc: gcc@1800000 {
#reset-cells = <0x1>;
};
tcsr_mutex: hwlock@1905000 {
compatible = "qcom,tcsr-mutex";
reg = <0x01905000 0x20000>;
#hwlock-cells = <1>;
};
spmi_bus: spmi@200f000 {
compatible = "qcom,spmi-pmic-arb";
reg = <0x0200f000 0x001000>,
@@ -609,9 +634,18 @@ dwc_1: dwc3@8c00000 {
intc: interrupt-controller@b000000 {
compatible = "qcom,msm-qgic2";
#address-cells = <1>;
#size-cells = <1>;
interrupt-controller;
#interrupt-cells = <0x3>;
reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>;
ranges = <0 0xb00a000 0xffd>;
v2m@0 {
compatible = "arm,gic-v2m-frame";
msi-controller;
reg = <0x0 0xffd>;
};
};
timer {
@@ -636,7 +670,6 @@ timer@b120000 {
ranges;
compatible = "arm,armv7-timer-mem";
reg = <0x0b120000 0x1000>;
clock-frequency = <19200000>;
frame@b120000 {
frame-number = <0>;

23
arch/arm64/boot/dts/qcom/msm8916-longcheer-l8150.dts
View File

@@ -151,6 +151,21 @@ magnetometer@12 {
vddio-supply = <&pm8916_l6>;
};
light-sensor@23 {
compatible = "liteon,ltr559";
reg = <0x23>;
proximity-near-level = <75>;
interrupt-parent = <&msmgpio>;
interrupts = <115 IRQ_TYPE_EDGE_FALLING>;
pinctrl-names = "default";
pinctrl-0 = <&light_int_default>;
vdd-supply = <&pm8916_l17>;
vio-supply = <&pm8916_l6>;
};
gyroscope@68 {
compatible = "bosch,bmg160";
reg = <0x68>;
@@ -392,6 +407,14 @@ gyro_int_default: gyro-int-default {
bias-disable;
};
light_int_default: light-int-default {
pins = "gpio115";
function = "gpio";
drive-strength = <2>;
bias-disable;
};
magn_int_default: magn-int-default {
pins = "gpio113";
function = "gpio";

2
arch/arm64/boot/dts/qcom/msm8916-samsung-j5.dts
View File

@@ -41,7 +41,7 @@ volume-up {
};
home-key {
lable = "Home Key";
label = "Home Key";
gpios = <&msmgpio 109 GPIO_ACTIVE_LOW>;
linux,code = <KEY_HOMEPAGE>;
};

6
arch/arm64/boot/dts/qcom/msm8916.dtsi
View File

@@ -1731,8 +1731,10 @@ usb_hs_phy: phy {
clock-names = "ref", "sleep";
resets = <&gcc GCC_USB2A_PHY_BCR>, <&usb 0>;
reset-names = "phy", "por";
qcom,init-seq = /bits/ 8 <0x0 0x44
0x1 0x6b 0x2 0x24 0x3 0x13>;
qcom,init-seq = /bits/ 8 <0x0 0x44>,
<0x1 0x6b>,
<0x2 0x24>,
<0x3 0x13>;
};
};
};

1326
arch/arm64/boot/dts/qcom/msm8953.dtsi Normal file
View File

File diff suppressed because it is too large Load Diff

14
arch/arm64/boot/dts/qcom/msm8992-lg-bullhead-rev-10.dts Normal file
View File

@@ -0,0 +1,14 @@
// SPDX-License-Identifier: GPL-2.0-only
/* Copyright (c) Jean Thomas <virgule@jeanthomas.me>
*/
/dts-v1/;
#include "msm8992-lg-bullhead.dtsi"
/ {
model = "LG Nexus 5X rev 1.0";
/* required for bootloader to select correct board */
qcom,board-id = <0xa64 0>;
};

14
arch/arm64/boot/dts/qcom/msm8992-lg-bullhead-rev-101.dts Normal file
View File

@@ -0,0 +1,14 @@
// SPDX-License-Identifier: GPL-2.0-only
/* Copyright (c) Jean Thomas <virgule@jeanthomas.me>
*/
/dts-v1/;
#include "msm8992-lg-bullhead.dtsi"
/ {
model = "LG Nexus 5X rev 1.01";
/* required for bootloader to select correct board */
qcom,board-id = <0xb64 0>;
};

2
arch/arm64/boot/dts/qcom/msm8992-bullhead-rev-101.dts → arch/arm64/boot/dts/qcom/msm8992-lg-bullhead.dtsi
View File

@@ -18,9 +18,7 @@ / {
compatible = "lg,bullhead", "qcom,msm8992";
chassis-type = "handset";
/* required for bootloader to select correct board */
qcom,msm-id = <251 0>, <252 0>;
qcom,board-id = <0xb64 0>;
qcom,pmic-id = <0x10009 0x1000A 0x0 0x0>;
/* Bullhead firmware doesn't support PSCI */

0
arch/arm64/boot/dts/qcom/msm8994-angler-rev-101.dts → arch/arm64/boot/dts/qcom/msm8994-huawei-angler-rev-101.dts
View File

7
arch/arm64/boot/dts/qcom/msm8994.dtsi
View File

@@ -444,7 +444,7 @@ usb@f9200000 {
};
sdhc1: sdhci@f9824900 {
compatible = "qcom,sdhci-msm-v4";
compatible = "qcom,msm8994-sdhci", "qcom,sdhci-msm-v4";
reg = <0xf9824900 0x1a0>, <0xf9824000 0x800>;
reg-names = "hc_mem", "core_mem";
@@ -467,7 +467,7 @@ sdhc1: sdhci@f9824900 {
};
sdhc2: sdhci@f98a4900 {
compatible = "qcom,sdhci-msm-v4";
compatible = "qcom,msm8994-sdhci", "qcom,sdhci-msm-v4";
reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
reg-names = "hc_mem", "core_mem";
@@ -713,6 +713,9 @@ gcc: clock-controller@fc400000 {
#reset-cells = <1>;
#power-domain-cells = <1>;
reg = <0xfc400000 0x2000>;
clock-names = "xo", "sleep_clk";
clocks = <&xo_board>, <&sleep_clk>;
};
rpm_msg_ram: sram@fc428000 {

2
arch/arm64/boot/dts/qcom/msm8996-mtp.dts
View File

@@ -9,7 +9,7 @@
/ {
model = "Qualcomm Technologies, Inc. MSM 8996 MTP";
compatible = "qcom,msm8996-mtp";
compatible = "qcom,msm8996-mtp", "qcom,msm8996";
aliases {
serial0 = &blsp2_uart2;

34
arch/arm64/boot/dts/qcom/msm8996.dtsi
View File

@@ -134,7 +134,7 @@ CPU_SLEEP_0: cpu-sleep-0 {
};
};
cluster0_opp: opp_table0 {
cluster0_opp: opp-table-cluster0 {
compatible = "operating-points-v2-kryo-cpu";
nvmem-cells = <&speedbin_efuse>;
opp-shared;
@@ -222,7 +222,7 @@ opp-1593600000 {
};
};
cluster1_opp: opp_table1 {
cluster1_opp: opp-table-cluster1 {
compatible = "operating-points-v2-kryo-cpu";
nvmem-cells = <&speedbin_efuse>;
opp-shared;
@@ -679,8 +679,10 @@ gcc: clock-controller@300000 {
#power-domain-cells = <1>;
reg = <0x00300000 0x90000>;
clocks = <&rpmcc RPM_SMD_LN_BB_CLK>;
clock-names = "cxo2";
clocks = <&rpmcc RPM_SMD_BB_CLK1>,
<&rpmcc RPM_SMD_LN_BB_CLK>,
<&sleep_clk>;
clock-names = "cxo", "cxo2", "sleep_clk";
};
tsens0: thermal-sensor@4a9000 {
@@ -713,7 +715,7 @@ cryptobam: dma@644000 {
clock-names = "bam_clk";
#dma-cells = <1>;
qcom,ee = <0>;
qcom,controlled-remotely = <1>;
qcom,controlled-remotely;
};
crypto: crypto@67a000 {
@@ -887,7 +889,7 @@ dsi0_phy: dsi-phy@994400 {
#clock-cells = <1>;
#phy-cells = <0>;
clocks = <&mmcc MDSS_AHB_CLK>, <&xo_board>;
clocks = <&mmcc MDSS_AHB_CLK>, <&rpmcc RPM_SMD_BB_CLK1>;
clock-names = "iface", "ref";
status = "disabled";
};
@@ -1546,7 +1548,7 @@ sram@290000 {
reg = <0x00290000 0x10000>;
};
spmi_bus: qcom,spmi@400f000 {
spmi_bus: spmi@400f000 {
compatible = "qcom,spmi-pmic-arb";
reg = <0x0400f000 0x1000>,
<0x04400000 0x800000>,
@@ -2593,7 +2595,7 @@ kryocc: clock-controller@6400000 {
reg = <0x06400000 0x90000>;
clock-names = "xo";
clocks = <&xo_board>;
clocks = <&rpmcc RPM_SMD_BB_CLK1>;
#clock-cells = <1>;
};
@@ -2693,7 +2695,7 @@ hsusb_phy2: phy@7412000 {
};
sdhc1: sdhci@7464900 {
compatible = "qcom,sdhci-msm-v4";
compatible = "qcom,msm8996-sdhci", "qcom,sdhci-msm-v4";
reg = <0x07464900 0x11c>, <0x07464000 0x800>;
reg-names = "hc_mem", "core_mem";
@@ -2704,7 +2706,7 @@ sdhc1: sdhci@7464900 {
clock-names = "iface", "core", "xo";
clocks = <&gcc GCC_SDCC1_AHB_CLK>,
<&gcc GCC_SDCC1_APPS_CLK>,
<&xo_board>;
<&rpmcc RPM_SMD_BB_CLK1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&sdc1_state_on>;
@@ -2716,7 +2718,7 @@ sdhc1: sdhci@7464900 {
};
sdhc2: sdhci@74a4900 {
compatible = "qcom,sdhci-msm-v4";
compatible = "qcom,msm8996-sdhci", "qcom,sdhci-msm-v4";
reg = <0x074a4900 0x314>, <0x074a4000 0x800>;
reg-names = "hc_mem", "core_mem";
@@ -2727,7 +2729,7 @@ sdhc2: sdhci@74a4900 {
clock-names = "iface", "core", "xo";
clocks = <&gcc GCC_SDCC2_AHB_CLK>,
<&gcc GCC_SDCC2_APPS_CLK>,
<&xo_board>;
<&rpmcc RPM_SMD_BB_CLK1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&sdc2_state_on>;
@@ -3028,7 +3030,7 @@ adsp_pil: remoteproc@9300000 {
interrupt-names = "wdog", "fatal", "ready",
"handover", "stop-ack";
clocks = <&xo_board>;
clocks = <&rpmcc RPM_SMD_BB_CLK1>;
clock-names = "xo";
memory-region = <&adsp_region>;
@@ -3054,7 +3056,7 @@ apr {
power-domains = <&gcc HLOS1_VOTE_LPASS_ADSP_GDSC>;
compatible = "qcom,apr-v2";
qcom,smd-channels = "apr_audio_svc";
qcom,apr-domain = <APR_DOMAIN_ADSP>;
qcom,domain = <APR_DOMAIN_ADSP>;
#address-cells = <1>;
#size-cells = <0>;
@@ -3273,7 +3275,7 @@ cpu3_crit: cpu_crit {
};
};
gpu-thermal-top {
gpu-top-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
@@ -3295,7 +3297,7 @@ map0 {
};
};
gpu-thermal-bottom {
gpu-bottom-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;

56
arch/arm64/boot/dts/qcom/msm8998.dtsi
View File

@@ -138,15 +138,9 @@ CPU0: cpu@0 {
cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
next-level-cache = <&L2_0>;
L2_0: l2-cache {
compatible = "arm,arch-cache";
compatible = "cache";
cache-level = <2>;
};
L1_I_0: l1-icache {
compatible = "arm,arch-cache";
};
L1_D_0: l1-dcache {
compatible = "arm,arch-cache";
};
};
CPU1: cpu@1 {
@@ -157,12 +151,6 @@ CPU1: cpu@1 {
capacity-dmips-mhz = <1024>;
cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
next-level-cache = <&L2_0>;
L1_I_1: l1-icache {
compatible = "arm,arch-cache";
};
L1_D_1: l1-dcache {
compatible = "arm,arch-cache";
};
};
CPU2: cpu@2 {
@@ -173,12 +161,6 @@ CPU2: cpu@2 {
capacity-dmips-mhz = <1024>;
cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
next-level-cache = <&L2_0>;
L1_I_2: l1-icache {
compatible = "arm,arch-cache";
};
L1_D_2: l1-dcache {
compatible = "arm,arch-cache";
};
};
CPU3: cpu@3 {
@@ -189,12 +171,6 @@ CPU3: cpu@3 {
capacity-dmips-mhz = <1024>;
cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
next-level-cache = <&L2_0>;
L1_I_3: l1-icache {
compatible = "arm,arch-cache";
};
L1_D_3: l1-dcache {
compatible = "arm,arch-cache";
};
};
CPU4: cpu@100 {
@@ -206,15 +182,9 @@ CPU4: cpu@100 {
cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
next-level-cache = <&L2_1>;
L2_1: l2-cache {
compatible = "arm,arch-cache";
compatible = "cache";
cache-level = <2>;
};
L1_I_100: l1-icache {
compatible = "arm,arch-cache";
};
L1_D_100: l1-dcache {
compatible = "arm,arch-cache";
};
};
CPU5: cpu@101 {
@@ -225,12 +195,6 @@ CPU5: cpu@101 {
capacity-dmips-mhz = <1536>;
cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
next-level-cache = <&L2_1>;
L1_I_101: l1-icache {
compatible = "arm,arch-cache";
};
L1_D_101: l1-dcache {
compatible = "arm,arch-cache";
};
};
CPU6: cpu@102 {
@@ -241,12 +205,6 @@ CPU6: cpu@102 {
capacity-dmips-mhz = <1536>;
cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
next-level-cache = <&L2_1>;
L1_I_102: l1-icache {
compatible = "arm,arch-cache";
};
L1_D_102: l1-dcache {
compatible = "arm,arch-cache";
};
};
CPU7: cpu@103 {
@@ -257,12 +215,6 @@ CPU7: cpu@103 {
capacity-dmips-mhz = <1536>;
cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
next-level-cache = <&L2_1>;
L1_I_103: l1-icache {
compatible = "arm,arch-cache";
};
L1_D_103: l1-dcache {
compatible = "arm,arch-cache";
};
};
cpu-map {
@@ -674,7 +626,7 @@ cpu7_crit: cpu_crit {
};
};
gpu-thermal-bottom {
gpu-bottom-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
@@ -689,7 +641,7 @@ gpu1_alert0: trip-point0 {
};
};
gpu-thermal-top {
gpu-top-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;

10
arch/arm64/boot/dts/qcom/pm6150l.dtsi
View File

@@ -52,5 +52,15 @@ pm6150l_lsid5: pmic@5 {
reg = <0x5 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
pm6150l_wled: leds@d800 {
compatible = "qcom,pm6150l-wled";
reg = <0xd800>, <0xd900>;
interrupts = <0x5 0xd8 0x1 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "ovp";
label = "backlight";
status = "disabled";
};
};
};

90
arch/arm64/boot/dts/qcom/pm8953.dtsi Normal file
View File

@@ -0,0 +1,90 @@
// SPDX-License-Identifier: BSD-3-Clause
/* Copyright (c) 2022, The Linux Foundation. All rights reserved. */
#include <dt-bindings/iio/qcom,spmi-vadc.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/input/linux-event-codes.h>
#include <dt-bindings/spmi/spmi.h>
&spmi_bus {
pmic@0 {
compatible = "qcom,pm8953", "qcom,spmi-pmic";
reg = <0 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
pm8953_pon: pon@800 {
compatible = "qcom,pm8916-pon";
reg = <0x800>;
mode-bootloader = <0x2>;
mode-recovery = <0x1>;
pwrkey {
compatible = "qcom,pm8941-pwrkey";
interrupts = <0x00 0x08 0 IRQ_TYPE_EDGE_BOTH>;
debounce = <15625>;
bias-pull-up;
linux,code = <KEY_POWER>;
};
pm8953_resin: resin {
compatible = "qcom,pm8941-resin";
interrupts = <0x00 0x08 1 IRQ_TYPE_EDGE_BOTH>;
debounce = <15625>;
bias-pull-up;
status = "disabled";
};
};
temp-alarm@2400 {
compatible = "qcom,spmi-temp-alarm";
reg = <0x2400>;
interrupts = <0x0 0x24 0x0 IRQ_TYPE_EDGE_RISING>;
io-channels = <&pm8953_vadc VADC_DIE_TEMP>;
io-channel-names = "thermal";
#thermal-sensor-cells = <0>;
};
pm8953_vadc: vadc@3100 {
compatible = "qcom,spmi-vadc";
reg = <0x3100>;
interrupts = <0x00 0x31 0x00 0x01>;
#address-cells = <1>;
#size-cells = <0>;
#io-channel-cells = <1>;
adc-chan@8 {
reg = <VADC_DIE_TEMP>;
};
adc-chan@9 {
reg = <VADC_REF_625MV>;
};
adc-chan@a {
reg = <VADC_REF_1250MV>;
};
adc-chan@c {
reg = <VADC_SPARE1>;
};
adc-chan@e {
reg = <VADC_GND_REF>;
};
adc-chan@f {
reg = <VADC_VDD_VADC>;
};
};
rtc@6000 {
compatible = "qcom,pm8941-rtc";
reg = <0x6000>, <0x6100>;
reg-names = "rtc", "alarm";
interrupts = <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>;
};
};
pmic@1 {
compatible = "qcom,pm8953", "qcom,spmi-pmic";
reg = <1 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
};
};

4
arch/arm64/boot/dts/qcom/pms405.dtsi
View File

@@ -32,7 +32,7 @@ pms405_crit: pms405-crit {
&spmi_bus {
pms405_0: pms405@0 {
compatible = "qcom,spmi-pmic";
compatible = "qcom,pms405", "qcom,spmi-pmic";
reg = <0x0 SPMI_USID>;
#address-cells = <1>;
#size-cells = <0>;
@@ -139,7 +139,7 @@ rtc@6000 {
};
pms405_1: pms405@1 {
compatible = "qcom,spmi-pmic";
compatible = "qcom,pms405", "qcom,spmi-pmic";
reg = <0x1 SPMI_USID>;
pms405_spmi_regulators: regulators {

4
arch/arm64/boot/dts/qcom/qcs404.dtsi
View File

@@ -110,7 +110,7 @@ CPU_SLEEP_0: cpu-sleep-0 {
};
};
cpu_opp_table: cpu-opp-table {
cpu_opp_table: opp-table-cpu {
compatible = "operating-points-v2-kryo-cpu";
opp-shared;
@@ -128,7 +128,7 @@ opp-1401600000 {
};
};
cpr_opp_table: cpr-opp-table {
cpr_opp_table: opp-table-cpr {
compatible = "operating-points-v2-qcom-level";
cpr_opp1: opp1 {

16
arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz.dtsi
View File

@@ -142,6 +142,22 @@ skin-temp-thermistor@1 {
};
};
&pp1800_uf_cam {
status = "okay";
};
&pp1800_wf_cam {
status = "okay";
};
&pp2800_uf_cam {
status = "okay";
};
&pp2800_wf_cam {
status = "okay";
};
&pp3300_dx_edp {
gpio = <&tlmm 67 GPIO_ACTIVE_HIGH>;
};

16
arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi
View File

@@ -146,6 +146,22 @@ skin-temp-thermistor@1 {
};
};
&pp1800_uf_cam {
status = "okay";
};
&pp1800_wf_cam {
status = "okay";
};
&pp2800_uf_cam {
status = "okay";
};
&pp2800_wf_cam {
status = "okay";
};
&pp3300_dx_edp {
gpio = <&tlmm 67 GPIO_ACTIVE_HIGH>;
};

126
arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi
View File

@@ -144,6 +144,100 @@ pp3300_a: pp3300-a-regulator {
vin-supply = <&ppvar_sys>;
};
pp1800_ec:
pp1800_sensors:
pp1800_ldo: pp1800-ldo-regulator {
compatible = "regulator-fixed";
regulator-name = "pp1800_ldo";
/* EC turns on with hibernate_l; always on for AP */
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
/*
* Actually should be pp1800_h1 but we don't have any need to
* model that so we use the parent of pp1800_h1.
*/
vin-supply = <&pp3300_a>;
};
pp1800_uf_cam: pp1800-uf-cam-regulator {
compatible = "regulator-fixed";
regulator-name = "pp1800_uf_cam";
status = "disabled";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
gpio = <&tlmm 6 GPIO_ACTIVE_HIGH>;
enable-active-high;
pinctrl-names = "default";
pinctrl-0 = <&uf_cam_en>;
vin-supply = <&pp1800_ldo>;
regulator-enable-ramp-delay = <1000>;
};
pp1800_wf_cam: pp1800-wf-cam-regulator {
compatible = "regulator-fixed";
regulator-name = "pp1800_wf_cam";
status = "disabled";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
gpio = <&tlmm 7 GPIO_ACTIVE_HIGH>;
enable-active-high;
pinctrl-names = "default";
pinctrl-0 = <&wf_cam_en>;
vin-supply = <&pp1800_ldo>;
regulator-enable-ramp-delay = <1000>;
};
pp2800_uf_cam: pp2800-uf-cam-regulator {
compatible = "regulator-fixed";
regulator-name = "pp2800_uf_cam";
status = "disabled";
regulator-min-microvolt = <2850000>;
regulator-max-microvolt = <2850000>;
gpio = <&tlmm 6 GPIO_ACTIVE_HIGH>;
enable-active-high;
/*
* The pinconf can only be referenced once so we put it on the
* first regulator and comment it out here.
* pinctrl-names = "default";
* pinctrl-0 = <&uf_cam_en>;
*/
vin-supply = <&pp3300_a>;
};
pp2800_vcm_wf_cam:
pp2800_wf_cam: pp2800-wf-cam-regulator {
compatible = "regulator-fixed";
regulator-name = "pp2800_wf_cam";
status = "disabled";
regulator-min-microvolt = <2850000>;
regulator-max-microvolt = <2850000>;
gpio = <&tlmm 7 GPIO_ACTIVE_HIGH>;
enable-active-high;
/*
* The pinconf can only be referenced once so we put it on the
* first regulator and comment it out here.
* pinctrl-names = "default";
* pinctrl-0 = <&wf_cam_en>;
*/
vin-supply = <&pp3300_a>;
};
pp3300_audio:
pp3300_codec: pp3300-codec-regulator {
compatible = "regulator-fixed";
@@ -190,7 +284,7 @@ pp3300_fp_tp: pp3300-fp-tp-regulator {
vin-supply = <&pp3300_a>;
};
pp3300_hub: pp3300-hub {
pp3300_hub: pp3300-hub-regulator {
compatible = "regulator-fixed";
regulator-name = "pp3300_hub";
@@ -543,7 +637,7 @@ cros_ec: ec@0 {
pinctrl-0 = <&ap_ec_int_l>;
spi-max-frequency = <3000000>;
cros_ec_pwm: ec-pwm {
cros_ec_pwm: pwm {
compatible = "google,cros-ec-pwm";
#pwm-cells = <1>;
};
@@ -1521,4 +1615,32 @@ pinconf-sd-cd {
drive-strength = <2>;
};
};
uf_cam_en: uf-cam-en {
pinmux {
pins = "gpio6";
function = "gpio";
};
pinconf {
pins = "gpio6";
drive-strength = <2>;
/* External pull down */
bias-disable;
};
};
wf_cam_en: wf-cam-en {
pinmux {
pins = "gpio7";
function = "gpio";
};
pinconf {
pins = "gpio7";
drive-strength = <2>;
/* External pull down */
bias-disable;
};
};
};

2
arch/arm64/boot/dts/qcom/sc7180.dtsi
View File

@@ -1459,6 +1459,8 @@ ipa: ipa@1e40000 {
"imem",
"config";
qcom,qmp = <&aoss_qmp>;
qcom,smem-states = <&ipa_smp2p_out 0>,
<&ipa_smp2p_out 1>;
qcom,smem-state-names = "ipa-clock-enabled-valid",

97
arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi Normal file
View File

@@ -0,0 +1,97 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* sc7280 fragment for devices with Chrome bootloader
*
* This file mainly tries to abstract out the memory protections put into
* place by the Chrome bootloader which are different than what's put into
* place by Qualcomm's typical bootloader. It also has a smattering of other
* things that will hold true for any conceivable Chrome design
*
* Copyright 2022 Google LLC.
*/
/*
* Reserved memory changes
*
* Delete all unused memory nodes and define the peripheral memory regions
* required by the setup for Chrome boards.
*/
/delete-node/ &hyp_mem;
/delete-node/ &xbl_mem;
/delete-node/ &reserved_xbl_uefi_log;
/delete-node/ &sec_apps_mem;
/ {
reserved-memory {
adsp_mem: memory@86700000 {
reg = <0x0 0x86700000 0x0 0x2800000>;
no-map;
};
camera_mem: memory@8ad00000 {
reg = <0x0 0x8ad00000 0x0 0x500000>;
no-map;
};
venus_mem: memory@8b200000 {
reg = <0x0 0x8b200000 0x0 0x500000>;
no-map;
};
mpss_mem: memory@8b800000 {
reg = <0x0 0x8b800000 0x0 0xf600000>;
no-map;
};
wpss_mem: memory@9ae00000 {
reg = <0x0 0x9ae00000 0x0 0x1900000>;
no-map;
};
mba_mem: memory@9c700000 {
reg = <0x0 0x9c700000 0x0 0x200000>;
no-map;
};
};
};
/* The PMIC PON code isn't compatible w/ how Chrome EC/BIOS handle things. */
&pmk8350_pon {
status = "disabled";
};
/*
* Chrome designs always boot from SPI flash hooked up to the qspi.
*
* It's expected that all boards will support "dual SPI" at 37.5 MHz.
* If some boards need a different speed or have a package that allows
* Quad SPI together with WP then those boards can easily override.
*/
&qspi {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&qspi_clk>, <&qspi_cs0>, <&qspi_data01>;
spi_flash: flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <37500000>;
spi-tx-bus-width = <2>;
spi-rx-bus-width = <2>;
};
};
/* Modem setup is different on Chrome setups than typical Qualcomm setup */
&remoteproc_mpss {
status = "okay";
compatible = "qcom,sc7280-mss-pil";
iommus = <&apps_smmu 0x124 0x0>, <&apps_smmu 0x488 0x7>;
memory-region = <&mba_mem>, <&mpss_mem>;
};
/* Increase the size from 2.5MB to 8MB */
&rmtfs_mem {
reg = <0x0 0x9c900000 0x0 0x800000>;
};

12
arch/arm64/boot/dts/qcom/sc7280-crd.dts
View File

@@ -23,6 +23,18 @@ chosen {
};
};
&apps_rsc {
pmg1110-regulators {
compatible = "qcom,pmg1110-rpmh-regulators";
qcom,pmic-id = "k";
vreg_s1k_1p0: smps1 {
regulator-min-microvolt = <1010000>;
regulator-max-microvolt = <1170000>;
};
};
};
ap_tp_i2c: &i2c0 {
status = "okay";
clock-frequency = <400000>;

1352
arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r0.dts Normal file
View File

File diff suppressed because it is too large Load Diff

313
arch/arm64/boot/dts/qcom/sc7280-herobrine-herobrine-r1.dts Normal file
View File

@@ -0,0 +1,313 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Google Herobrine board device tree source
*
* Copyright 2022 Google LLC.
*/
/dts-v1/;
#include "sc7280-herobrine.dtsi"
/ {
model = "Google Herobrine (rev1+)";
compatible = "google,herobrine", "qcom,sc7280";
};
/* ADDITIONS TO NODES DEFINED IN PARENT DEVICE TREE FILES */
&ap_spi_fp {
status = "okay";
};
/*
* Although the trackpad is really part of the herobrine baseboard, we'll
* put the actual definition in the board device tree since different boards
* might hook up different trackpads (or no i2c trackpad at all in the case
* of tablets / detachables).
*/
ap_tp_i2c: &i2c0 {
status = "okay";
clock-frequency = <400000>;
trackpad: trackpad@15 {
compatible = "elan,ekth3000";
reg = <0x15>;
pinctrl-names = "default";
pinctrl-0 = <&tp_int_odl>;
interrupt-parent = <&tlmm>;
interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
vcc-supply = <&pp3300_z1>;
wakeup-source;
};
};
/*
* The touchscreen connector might come off the Qcard, at least in the case of
* eDP. Like the trackpad, we'll put it in the board device tree file since
* different boards have different touchscreens.
*/
ts_i2c: &i2c13 {
status = "okay";
clock-frequency = <400000>;
ap_ts: touchscreen@5c {
compatible = "hid-over-i2c";
reg = <0x5c>;
pinctrl-names = "default";
pinctrl-0 = <&ts_int_conn>, <&ts_rst_conn>;
interrupt-parent = <&tlmm>;
interrupts = <55 IRQ_TYPE_LEVEL_LOW>;
post-power-on-delay-ms = <500>;
hid-descr-addr = <0x0000>;
vdd-supply = <&ts_avdd>;
};
};
/* For nvme */
&pcie1 {
status = "okay";
};
/* For nvme */
&pcie1_phy {
status = "okay";
};
/* For eMMC */
&sdhc_1 {
status = "okay";
};
/* For SD Card */
&sdhc_2 {
status = "okay";
};
/* PINCTRL - BOARD-SPECIFIC */
/*
* Methodology for gpio-line-names:
* - If a pin goes to herobrine board and is named it gets that name.
* - If a pin goes to herobrine board and is not named, it gets no name.
* - If a pin is totally internal to Qcard then it gets Qcard name.
* - If a pin is not hooked up on Qcard, it gets no name.
*/
&pm8350c_gpios {
gpio-line-names = "FLASH_STROBE_1", /* 1 */
"AP_SUSPEND",
"PM8008_1_RST_N",
"",
"",
"",
"PMIC_EDP_BL_EN",
"PMIC_EDP_BL_PWM",
"";
};
&tlmm {
gpio-line-names = "AP_TP_I2C_SDA", /* 0 */
"AP_TP_I2C_SCL",
"SSD_RST_L",
"PE_WAKE_ODL",
"AP_SAR_SDA",
"AP_SAR_SCL",
"PRB_SC_GPIO_6",
"TP_INT_ODL",
"HP_I2C_SDA",
"HP_I2C_SCL",
"GNSS_L1_EN", /* 10 */
"GNSS_L5_EN",
"SPI_AP_MOSI",
"SPI_AP_MISO",
"SPI_AP_CLK",
"SPI_AP_CS0_L",
/*
* AP_FLASH_WP is crossystem ABI. Schematics
* call it BIOS_FLASH_WP_OD.
*/
"AP_FLASH_WP",
"",
"AP_EC_INT_L",
"",
"UF_CAM_RST_L", /* 20 */
"WF_CAM_RST_L",
"UART_AP_TX_DBG_RX",
"UART_DBG_TX_AP_RX",
"",
"PM8008_IRQ_1",
"HOST2WLAN_SOL",
"WLAN2HOST_SOL",
"MOS_BT_UART_CTS",
"MOS_BT_UART_RFR",
"MOS_BT_UART_TX", /* 30 */
"MOS_BT_UART_RX",
"PRB_SC_GPIO_32",
"HUB_RST_L",
"",
"",
"AP_SPI_FP_MISO",
"AP_SPI_FP_MOSI",
"AP_SPI_FP_CLK",
"AP_SPI_FP_CS_L",
"AP_EC_SPI_MISO", /* 40 */
"AP_EC_SPI_MOSI",
"AP_EC_SPI_CLK",
"AP_EC_SPI_CS_L",
"LCM_RST_L",
"EARLY_EUD_N",
"",
"DP_HOT_PLUG_DET",
"IO_BRD_MLB_ID0",
"IO_BRD_MLB_ID1",
"IO_BRD_MLB_ID2", /* 50 */
"SSD_EN",
"TS_I2C_SDA_CONN",
"TS_I2C_CLK_CONN",
"TS_RST_CONN",
"TS_INT_CONN",
"AP_I2C_TPM_SDA",
"AP_I2C_TPM_SCL",
"PRB_SC_GPIO_58",
"PRB_SC_GPIO_59",
"EDP_HOT_PLUG_DET_N", /* 60 */
"FP_TO_AP_IRQ_L",
"",
"AMP_EN",
"CAM0_MCLK_GPIO_64",
"CAM1_MCLK_GPIO_65",
"WF_CAM_MCLK",
"PRB_SC_GPIO_67",
"FPMCU_BOOT0",
"UF_CAM_SDA",
"UF_CAM_SCL", /* 70 */
"",
"",
"WF_CAM_SDA",
"WF_CAM_SCL",
"",
"",
"EN_FP_RAILS",
"FP_RST_L",
"PCIE1_CLKREQ_ODL",
"EN_PP3300_DX_EDP", /* 80 */
"SC_GPIO_81",
"FORCED_USB_BOOT",
"WCD_RESET_N",
"MOS_WLAN_EN",
"MOS_BT_EN",
"MOS_SW_CTRL",
"MOS_PCIE0_RST",
"MOS_PCIE0_CLKREQ_N",
"MOS_PCIE0_WAKE_N",
"MOS_LAA_AS_EN", /* 90 */
"SD_CD_ODL",
"",
"",
"MOS_BT_WLAN_SLIMBUS_CLK",
"MOS_BT_WLAN_SLIMBUS_DAT0",
"HP_MCLK",
"HP_BCLK",
"HP_DOUT",
"HP_DIN",
"HP_LRCLK", /* 100 */
"HP_IRQ",
"",
"",
"GSC_AP_INT_ODL",
"EN_PP3300_CODEC",
"AMP_BCLK",
"AMP_DIN",
"AMP_LRCLK",
"UIM1_DATA_GPIO_109",
"UIM1_CLK_GPIO_110", /* 110 */
"UIM1_RESET_GPIO_111",
"PRB_SC_GPIO_112",
"UIM0_DATA",
"UIM0_CLK",
"UIM0_RST",
"UIM0_PRESENT_ODL",
"SDM_RFFE0_CLK",
"SDM_RFFE0_DATA",
"WF_CAM_EN",
"FASTBOOT_SEL_0", /* 120 */
"SC_GPIO_121",
"FASTBOOT_SEL_1",
"SC_GPIO_123",
"FASTBOOT_SEL_2",
"SM_RFFE4_CLK_GRFC_8",
"SM_RFFE4_DATA_GRFC_9",
"WLAN_COEX_UART1_RX",
"WLAN_COEX_UART1_TX",
"PRB_SC_GPIO_129",
"LCM_ID0", /* 130 */
"LCM_ID1",
"",
"SDR_QLINK_REQ",
"SDR_QLINK_EN",
"QLINK0_WMSS_RESET_N",
"SMR526_QLINK1_REQ",
"SMR526_QLINK1_EN",
"SMR526_QLINK1_WMSS_RESET_N",
"PRB_SC_GPIO_139",
"SAR1_IRQ_ODL", /* 140 */
"SAR0_IRQ_ODL",
"PRB_SC_GPIO_142",
"",
"WCD_SWR_TX_CLK",
"WCD_SWR_TX_DATA0",
"WCD_SWR_TX_DATA1",
"WCD_SWR_RX_CLK",
"WCD_SWR_RX_DATA0",
"WCD_SWR_RX_DATA1",
"DMIC01_CLK", /* 150 */
"DMIC01_DATA",
"DMIC23_CLK",
"DMIC23_DATA",
"",
"",
"EC_IN_RW_ODL",
"HUB_EN",
"WCD_SWR_TX_DATA2",
"",
"", /* 160 */
"",
"",
"",
"",
"",
"",
"",
"",
"",
"", /* 170 */
"MOS_BLE_UART_TX",
"MOS_BLE_UART_RX",
"",
"",
"";
};

14
arch/arm64/boot/dts/qcom/sc7280-herobrine.dts
View File

@@ -1,14 +0,0 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Google Herobrine board device tree source
*
* Copyright 2021 Google LLC.
*/
#include "sc7280-herobrine.dtsi"
/ {
model = "Google Herobrine";
compatible = "google,herobrine",
"qcom,sc7280";
};

1153
arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi
View File

File diff suppressed because it is too large Load Diff

2
arch/arm64/boot/dts/qcom/sc7280-idp-ec-h1.dtsi
View File

@@ -20,7 +20,7 @@ cros_ec: ec@0 {
pinctrl-0 = <&ap_ec_int_l>;
spi-max-frequency = <3000000>;
cros_ec_pwm: ec-pwm {
cros_ec_pwm: pwm {
compatible = "google,cros-ec-pwm";
#pwm-cells = <1>;
};

20
arch/arm64/boot/dts/qcom/sc7280-idp.dts
View File

@@ -56,6 +56,10 @@ vreg_l6e_0p8: ldo6 {
};
};
&bluetooth {
vddio-supply = <&vreg_l19b_1p8>;
};
&ipa {
status = "okay";
modem-init;
@@ -80,3 +84,19 @@ pmr735a_die_temp {
qcom,pre-scaling = <1 1>;
};
};
&usb_2 {
status = "okay";
};
&usb_2_dwc3 {
dr_mode = "host";
};
&usb_2_hsphy {
status = "okay";
vdda-pll-supply = <&vreg_l10c_0p8>;
vdda33-supply = <&vreg_l2b_3p0>;
vdda18-supply = <&vreg_l1c_1p8>;
};

215
arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
View File

@@ -5,7 +5,6 @@
* Copyright (c) 2021, The Linux Foundation. All rights reserved.
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/iio/qcom,spmi-adc7-pmk8350.h>
#include <dt-bindings/input/linux-event-codes.h>
#include "sc7280.dtsi"
@@ -13,7 +12,14 @@
#include "pm8350c.dtsi"
#include "pmk8350.dtsi"
#include "sc7280-chrome-common.dtsi"
/ {
aliases {
bluetooth0 = &bluetooth;
serial1 = &uart7;
};
gpio-keys {
compatible = "gpio-keys";
label = "gpio-keys";
@@ -45,58 +51,6 @@ nvme_3v3_regulator: nvme-3v3-regulator {
};
};
/*
* Reserved memory changes
*
* Delete all unused memory nodes and define the peripheral memory regions
* required by the board dts.
*
*/
/delete-node/ &hyp_mem;
/delete-node/ &xbl_mem;
/delete-node/ &reserved_xbl_uefi_log;
/delete-node/ &sec_apps_mem;
/* Increase the size from 2.5MB to 8MB */
&rmtfs_mem {
reg = <0x0 0x9c900000 0x0 0x800000>;
};
/ {
reserved-memory {
adsp_mem: memory@86700000 {
reg = <0x0 0x86700000 0x0 0x2800000>;
no-map;
};
camera_mem: memory@8ad00000 {
reg = <0x0 0x8ad00000 0x0 0x500000>;
no-map;
};
venus_mem: memory@8b200000 {
reg = <0x0 0x8b200000 0x0 0x500000>;
no-map;
};
mpss_mem: memory@8b800000 {
reg = <0x0 0x8b800000 0x0 0xf600000>;
no-map;
};
wpss_mem: memory@9ae00000 {
reg = <0x0 0x9ae00000 0x0 0x1900000>;
no-map;
};
mba_mem: memory@9c700000 {
reg = <0x0 0x9c700000 0x0 0x200000>;
no-map;
};
};
};
&apps_rsc {
pm7325-regulators {
compatible = "qcom,pm7325-rpmh-regulators";
@@ -313,20 +267,6 @@ &qfprom {
vcc-supply = <&vreg_l1c_1p8>;
};
&qspi {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&qspi_clk>, <&qspi_cs0>, <&qspi_data01>;
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <37500000>;
spi-tx-bus-width = <2>;
spi-rx-bus-width = <2>;
};
};
&qupv3_id_0 {
status = "okay";
};
@@ -335,20 +275,9 @@ &qupv3_id_1 {
status = "okay";
};
&remoteproc_mpss {
status = "okay";
compatible = "qcom,sc7280-mss-pil";
iommus = <&apps_smmu 0x124 0x0>, <&apps_smmu 0x488 0x7>;
memory-region = <&mba_mem &mpss_mem>;
};
&sdhc_1 {
status = "okay";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&sdc1_on>;
pinctrl-1 = <&sdc1_off>;
non-removable;
no-sd;
no-sdio;
@@ -360,9 +289,8 @@ &sdhc_1 {
&sdhc_2 {
status = "okay";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&sdc2_on>;
pinctrl-1 = <&sdc2_off>;
pinctrl-0 = <&sdc2_clk>, <&sdc2_cmd>, <&sdc2_data>, <&sd_cd>;
pinctrl-1 = <&sdc2_clk_sleep>, <&sdc2_cmd_sleep>, <&sdc2_data_sleep>, <&sd_cd>;
vmmc-supply = <&vreg_l9c_2p9>;
vqmmc-supply = <&vreg_l6c_2p9>;
@@ -398,22 +326,6 @@ &usb_1_qmpphy {
vdda-pll-supply = <&vreg_l1b_0p8>;
};
&usb_2 {
status = "okay";
};
&usb_2_dwc3 {
dr_mode = "peripheral";
};
&usb_2_hsphy {
status = "okay";
vdda-pll-supply = <&vreg_l10c_0p8>;
vdda33-supply = <&vreg_l2b_3p0>;
vdda18-supply = <&vreg_l1c_1p8>;
};
&uart7 {
status = "okay";
@@ -422,10 +334,31 @@ &uart7 {
<&tlmm 31 IRQ_TYPE_EDGE_FALLING>;
pinctrl-names = "default", "sleep";
pinctrl-1 = <&qup_uart7_sleep_cts>, <&qup_uart7_sleep_rts>, <&qup_uart7_sleep_tx>, <&qup_uart7_sleep_rx>;
bluetooth: bluetooth {
compatible = "qcom,wcn6750-bt";
pinctrl-names = "default";
pinctrl-0 = <&bt_en>, <&sw_ctrl>;
enable-gpios = <&tlmm 85 GPIO_ACTIVE_HIGH>;
swctrl-gpios = <&tlmm 86 GPIO_ACTIVE_HIGH>;
vddaon-supply = <&vreg_s7b_0p9>;
vddbtcxmx-supply = <&vreg_s7b_0p9>;
vddrfacmn-supply = <&vreg_s7b_0p9>;
vddrfa0p8-supply = <&vreg_s7b_0p9>;
vddrfa1p7-supply = <&vreg_s1b_1p8>;
vddrfa1p2-supply = <&vreg_s8b_1p2>;
vddrfa2p2-supply = <&vreg_s1c_2p2>;
vddasd-supply = <&vreg_l11c_2p8>;
max-speed = <3200000>;
};
};
/* PINCTRL - additions to nodes defined in sc7280.dtsi */
&dp_hot_plug_det {
bias-disable;
};
&pm7325_gpios {
key_vol_up_default: key-vol-up-default {
pins = "gpio6";
@@ -437,6 +370,11 @@ key_vol_up_default: key-vol-up-default {
};
};
&pcie1_clkreq_n {
bias-pull-up;
drive-strength = <2>;
};
&qspi_cs0 {
bias-disable;
};
@@ -490,7 +428,48 @@ &qup_uart7_rx {
bias-pull-up;
};
&sdc1_clk {
bias-disable;
drive-strength = <16>;
};
&sdc1_cmd {
bias-pull-up;
drive-strength = <10>;
};
&sdc1_data {
bias-pull-up;
drive-strength = <10>;
};
&sdc1_rclk {
bias-pull-down;
};
&sdc2_clk {
bias-disable;
drive-strength = <16>;
};
&sdc2_cmd {
bias-pull-up;
drive-strength = <10>;
};
&sdc2_data {
bias-pull-up;
drive-strength = <10>;
};
&tlmm {
bt_en: bt-en {
pins = "gpio85";
function = "gpio";
output-low;
bias-disable;
};
nvme_pwren: nvme-pwren {
function = "gpio";
};
@@ -554,47 +533,17 @@ qup_uart7_sleep_rx: qup-uart7-sleep-rx {
*/
bias-pull-up;
};
};
&sdc1_on {
clk {
bias-disable;
drive-strength = <16>;
};
cmd {
sd_cd: sd-cd {
pins = "gpio91";
function = "gpio";
bias-pull-up;
drive-strength = <10>;
};
data {
bias-pull-up;
drive-strength = <10>;
};
rclk {
sw_ctrl: sw-ctrl {
pins = "gpio86";
function = "gpio";
bias-pull-down;
};
};
&sdc2_on {
clk {
bias-disable;
drive-strength = <16>;
};
cmd {
bias-pull-up;
drive-strength = <10>;
};
data {
bias-pull-up;
drive-strength = <10>;
};
sd-cd {
pins = "gpio91";
bias-pull-up;
};
};

4
arch/arm64/boot/dts/qcom/sc7280-idp2.dts
View File

@@ -23,6 +23,10 @@ chosen {
};
};
&bluetooth {
vddio-supply = <&vreg_l18b_1p8>;
};
&nvme_pwren {
pins = "gpio51";
};

547
arch/arm64/boot/dts/qcom/sc7280-qcard.dtsi Normal file
View File

@@ -0,0 +1,547 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* sc7280 Qcard device tree source
*
* Qcard PCB has the processor, RAM, eMMC (if stuffed), and eDP connector (if
* stuffed) on it. This device tree tries to encapsulate all the things that
* all boards using Qcard will have in common. Given that there are stuffing
* options, some things may be left with status "disabled" and enabled in
* the actual board device tree files.
*
* Copyright 2022 Google LLC.
*/
#include <dt-bindings/iio/qcom,spmi-adc7-pmk8350.h>
#include <dt-bindings/iio/qcom,spmi-adc7-pmr735a.h>
#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
#include "sc7280.dtsi"
/* PMICs depend on spmi_bus label and so must come after SoC */
#include "pm7325.dtsi"
#include "pm8350c.dtsi"
#include "pmk8350.dtsi"
/ {
aliases {
bluetooth0 = &bluetooth;
serial0 = &uart5;
serial1 = &uart7;
};
};
&apps_rsc {
/*
* Regulators are given labels corresponding to the various names
* they are referred to on schematics. They are also given labels
* corresponding to named voltage inputs on the SoC or components
* bundled with the SoC (like radio companion chips). We totally
* ignore it when one regulator is the input to another regulator.
* That's handled automatically by the initial config given to
* RPMH by the firmware.
*
* Regulators that the HLOS (High Level OS) doesn't touch at all
* are left out of here since they are managed elsewhere.
*/
pm7325-regulators {
compatible = "qcom,pm7325-rpmh-regulators";
qcom,pmic-id = "b";
vdd19_pmu_pcie_i:
vdd19_pmu_rfa_i:
vreg_s1b_1p856: smps1 {
regulator-min-microvolt = <1856000>;
regulator-max-microvolt = <2040000>;
};
vdd_pmu_aon_i:
vdd09_pmu_rfa_i:
vdd095_mx_pmu:
vdd095_pmu:
vreg_s7b_0p952: smps7 {
regulator-min-microvolt = <535000>;
regulator-max-microvolt = <1120000>;
};
vdd13_pmu_rfa_i:
vdd13_pmu_pcie_i:
vreg_s8b_1p256: smps8 {
regulator-min-microvolt = <1256000>;
regulator-max-microvolt = <1500000>;
};
vdd_a_usbssdp_0_core:
vreg_l1b_0p912: ldo1 {
regulator-min-microvolt = <825000>;
regulator-max-microvolt = <925000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vdd_a_usbhs_3p1:
vreg_l2b_3p072: ldo2 {
regulator-min-microvolt = <2700000>;
regulator-max-microvolt = <3544000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vdd_a_csi_0_1_1p2:
vdd_a_csi_2_3_1p2:
vdd_a_csi_4_1p2:
vdd_a_dsi_0_1p2:
vdd_a_edp_0_1p2:
vdd_a_qlink_0_1p2:
vdd_a_qlink_1_1p2:
vdd_a_pcie_0_1p2:
vdd_a_pcie_1_1p2:
vdd_a_ufs_0_1p2:
vdd_a_usbssdp_0_1p2:
vreg_l6b_1p2: ldo6 {
regulator-min-microvolt = <1140000>;
regulator-max-microvolt = <1260000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
/*
* Despite the fact that this is named to be 2.5V on the
* schematic, it powers eMMC which doesn't accept 2.5V
*/
vreg_l7b_2p5: ldo7 {
regulator-min-microvolt = <2960000>;
regulator-max-microvolt = <2960000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vdd_px_wcd9385:
vdd_txrx:
vddpx_0:
vddpx_3:
vddpx_7:
vreg_l18b_1p8: ldo18 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <2000000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vdd_1p8:
vdd_px_sdr735:
vdd_pxm:
vdd18_io:
vddio_px_1:
vddio_px_2:
vddio_px_3:
vddpx_ts:
vddpx_wl4otp:
vreg_l19b_1p8: ldo19 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
pm8350c-regulators {
compatible = "qcom,pm8350c-rpmh-regulators";
qcom,pmic-id = "c";
vdd22_wlbtpa_ch0:
vdd22_wlbtpa_ch1:
vdd22_wlbtppa_ch0:
vdd22_wlbtppa_ch1:
vdd22_wlpa5g_ch0:
vdd22_wlpa5g_ch1:
vdd22_wlppa5g_ch0:
vdd22_wlppa5g_ch1:
vreg_s1c_2p2: smps1 {
regulator-min-microvolt = <2190000>;
regulator-max-microvolt = <2210000>;
};
lp4_vdd2_1p052:
vreg_s9c_0p676: smps9 {
regulator-min-microvolt = <1010000>;
regulator-max-microvolt = <1170000>;
};
vdda_apc_cs_1p8:
vdda_gfx_cs_1p8:
vdda_turing_q6_cs_1p8:
vdd_a_cxo_1p8:
vdd_a_qrefs_1p8:
vdd_a_usbhs_1p8:
vdd_qfprom:
vreg_l1c_1p8: ldo1 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1980000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l2c_1p8: ldo2 {
regulator-min-microvolt = <1620000>;
regulator-max-microvolt = <1980000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l3c_3p0: ldo3 {
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <3540000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vddpx_5:
vreg_l4c_1p8_3p0: ldo4 {
regulator-min-microvolt = <1620000>;
regulator-max-microvolt = <3300000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vddpx_6:
vreg_l5c_1p8_3p0: ldo5 {
regulator-min-microvolt = <1620000>;
regulator-max-microvolt = <3300000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vddpx_2:
vreg_l6c_2p96: ldo6 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <2950000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l7c_3p0: ldo7 {
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3544000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l8c_1p8: ldo8 {
regulator-min-microvolt = <1620000>;
regulator-max-microvolt = <2000000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l9c_2p96: ldo9 {
regulator-min-microvolt = <2960000>;
regulator-max-microvolt = <2960000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vdd_a_csi_0_1_0p9:
vdd_a_csi_2_3_0p9:
vdd_a_csi_4_0p9:
vdd_a_dsi_0_0p9:
vdd_a_dsi_0_pll_0p9:
vdd_a_edp_0_0p9:
vdd_a_gnss_0p9:
vdd_a_pcie_0_core:
vdd_a_pcie_1_core:
vdd_a_qlink_0_0p9:
vdd_a_qlink_0_0p9_ck:
vdd_a_qlink_1_0p9:
vdd_a_qlink_1_0p9_ck:
vdd_a_qrefs_0p875_0:
vdd_a_qrefs_0p875_1:
vdd_a_qrefs_0p875_2:
vdd_a_qrefs_0p875_3:
vdd_a_qrefs_0p875_4_5:
vdd_a_qrefs_0p875_6:
vdd_a_qrefs_0p875_7:
vdd_a_qrefs_0p875_8:
vdd_a_qrefs_0p875_9:
vdd_a_ufs_0_core:
vdd_a_usbhs_core:
vreg_l10c_0p88: ldo10 {
regulator-min-microvolt = <720000>;
regulator-max-microvolt = <1050000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l11c_2p8: ldo11 {
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <3544000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l12c_1p8: ldo12 {
regulator-min-microvolt = <1650000>;
regulator-max-microvolt = <2000000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l13c_3p0: ldo13 {
regulator-min-microvolt = <2700000>;
regulator-max-microvolt = <3544000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vdd_flash:
vdd_iris_rgb:
vdd_mic_bias:
vreg_bob: bob {
regulator-min-microvolt = <3008000>;
regulator-max-microvolt = <3960000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
};
};
};
/* ADDITIONS TO NODES DEFINED IN PARENT DEVICE TREE FILES */
&ipa {
status = "okay";
modem-init;
};
&pcie1_phy {
vdda-phy-supply = <&vreg_l10c_0p88>;
vdda-pll-supply = <&vreg_l6b_1p2>;
};
&pmk8350_vadc {
pmk8350-die-temp@3 {
reg = <PMK8350_ADC7_DIE_TEMP>;
label = "pmk8350_die_temp";
qcom,pre-scaling = <1 1>;
};
pmr735a-die-temp@403 {
reg = <PMR735A_ADC7_DIE_TEMP>;
label = "pmr735a_die_temp";
qcom,pre-scaling = <1 1>;
};
};
&qfprom {
vcc-supply = <&vdd_qfprom>;
};
/* For eMMC. NOTE: not all Qcards have eMMC stuffed */
&sdhc_1 {
vmmc-supply = <&vreg_l7b_2p5>;
vqmmc-supply = <&vreg_l19b_1p8>;
non-removable;
no-sd;
no-sdio;
};
uart_dbg: &uart5 {
compatible = "qcom,geni-debug-uart";
status = "okay";
};
mos_bt_uart: &uart7 {
status = "okay";
/delete-property/ interrupts;
interrupts-extended = <&intc GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>,
<&tlmm 31 IRQ_TYPE_EDGE_FALLING>;
pinctrl-names = "default", "sleep";
pinctrl-1 = <&qup_uart7_sleep_cts>, <&qup_uart7_sleep_rts>, <&qup_uart7_sleep_tx>, <&qup_uart7_sleep_rx>;
bluetooth: bluetooth {
compatible = "qcom,wcn6750-bt";
pinctrl-names = "default";
pinctrl-0 = <&mos_bt_en>;
enable-gpios = <&tlmm 85 GPIO_ACTIVE_HIGH>;
swctrl-gpios = <&tlmm 86 GPIO_ACTIVE_HIGH>;
vddaon-supply = <&vreg_s7b_0p952>;
vddbtcxmx-supply = <&vreg_s7b_0p952>;
vddrfacmn-supply = <&vreg_s7b_0p952>;
vddrfa0p8-supply = <&vreg_s7b_0p952>;
vddrfa1p7-supply = <&vdd19_pmu_rfa_i>;
vddrfa1p2-supply = <&vdd13_pmu_rfa_i>;
vddrfa2p2-supply = <&vreg_s1c_2p2>;
vddasd-supply = <&vreg_l11c_2p8>;
vddio-supply = <&vreg_l18b_1p8>;
max-speed = <3200000>;
};
};
&usb_1_hsphy {
vdda-pll-supply = <&vdd_a_usbhs_core>;
vdda33-supply = <&vdd_a_usbhs_3p1>;
vdda18-supply = <&vdd_a_usbhs_1p8>;
};
&usb_1_qmpphy {
vdda-phy-supply = <&vdd_a_usbssdp_0_1p2>;
vdda-pll-supply = <&vdd_a_usbssdp_0_core>;
};
&usb_2_hsphy {
vdda-pll-supply = <&vdd_a_usbhs_core>;
vdda33-supply = <&vdd_a_usbhs_3p1>;
vdda18-supply = <&vdd_a_usbhs_1p8>;
};
/*
* PINCTRL - ADDITIONS TO NODES IN PARENT DEVICE TREE FILES
*
* NOTE: In general if pins leave the Qcard then the pinctrl goes in the
* baseboard or board device tree, not here.
*/
/*
* For ts_i2c
*
* Technically this i2c bus actually leaves the Qcard, but it leaves directly
* via the eDP connector (it doesn't hit the baseboard). The external pulls
* are on Qcard.
*/
&qup_i2c13_data_clk {
/* Has external pull */
bias-disable;
drive-strength = <2>;
};
/* For mos_bt_uart */
&qup_uart7_cts {
/* Configure a pull-down on CTS to match the pull of the Bluetooth module. */
bias-pull-down;
};
/* For mos_bt_uart */
&qup_uart7_rts {
/* We'll drive RTS, so no pull */
bias-disable;
drive-strength = <2>;
};
/* For mos_bt_uart */
&qup_uart7_tx {
/* We'll drive TX, so no pull */
bias-disable;
drive-strength = <2>;
};
/* For mos_bt_uart */
&qup_uart7_rx {
/*
* Configure a pull-up on RX. This is needed to avoid
* garbage data when the TX pin of the Bluetooth module is
* in tri-state (module powered off or not driving the
* signal yet).
*/
bias-pull-up;
};
/* eMMC, if stuffed, is straight on the Qcard */
&sdc1_clk {
bias-disable;
drive-strength = <16>;
};
&sdc1_cmd {
bias-pull-up;
drive-strength = <10>;
};
&sdc1_data {
bias-pull-up;
drive-strength = <10>;
};
&sdc1_rclk {
bias-pull-down;
};
/*
* PINCTRL - QCARD
*
* This has entries that are defined by Qcard even if they go to the main
* board. In cases where the pulls may be board dependent we defer those
* settings to the board device tree. Drive strengths tend to be assinged here
* but could conceivably be overwridden by board device trees.
*/
&pm8350c_gpios {
pmic_edp_bl_en: pmic-edp-bl-en {
pins = "gpio7";
function = "normal";
bias-disable;
qcom,drive-strength = <PMIC_GPIO_STRENGTH_LOW>;
/* Force backlight to be disabled to match state at boot. */
output-low;
};
pmic_edp_bl_pwm: pmic-edp-bl-pwm {
pins = "gpio8";
function = "func1";
bias-disable;
qcom,drive-strength = <PMIC_GPIO_STRENGTH_LOW>;
output-low;
power-source = <0>;
};
};
&tlmm {
mos_bt_en: mos-bt-en {
pins = "gpio85";
function = "gpio";
drive-strength = <2>;
output-low;
};
/* For mos_bt_uart */
qup_uart7_sleep_cts: qup-uart7-sleep-cts {
pins = "gpio28";
function = "gpio";
/*
* Configure a pull-down on CTS to match the pull of
* the Bluetooth module.
*/
bias-pull-down;
};
/* For mos_bt_uart */
qup_uart7_sleep_rts: qup-uart7-sleep-rts {
pins = "gpio29";
function = "gpio";
/*
* Configure pull-down on RTS. As RTS is active low
* signal, pull it low to indicate the BT SoC that it
* can wakeup the system anytime from suspend state by
* pulling RX low (by sending wakeup bytes).
*/
bias-pull-down;
};
/* For mos_bt_uart */
qup_uart7_sleep_rx: qup-uart7-sleep-rx {
pins = "gpio31";
function = "gpio";
/*
* Configure a pull-up on RX. This is needed to avoid
* garbage data when the TX pin of the Bluetooth module
* is floating which may cause spurious wakeups.
*/
bias-pull-up;
};
/* For mos_bt_uart */
qup_uart7_sleep_tx: qup-uart7-sleep-tx {
pins = "gpio30";
function = "gpio";
/*
* Configure pull-up on TX when it isn't actively driven
* to prevent BT SoC from receiving garbage during sleep.
*/
bias-pull-up;
};
ts_int_conn: ts-int-conn {
pins = "gpio55";
function = "gpio";
bias-pull-up;
};
ts_rst_conn: ts-rst-conn {
pins = "gpio54";
function = "gpio";
bias-pull-up;
drive-strength = <2>;
};
};

815
arch/arm64/boot/dts/qcom/sc7280.dtsi
View File

@@ -4,12 +4,14 @@
*
* Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
*/
#include <dt-bindings/clock/qcom,camcc-sc7280.h>
#include <dt-bindings/clock/qcom,dispcc-sc7280.h>
#include <dt-bindings/clock/qcom,gcc-sc7280.h>
#include <dt-bindings/clock/qcom,gpucc-sc7280.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,videocc-sc7280.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interconnect/qcom,osm-l3.h>
#include <dt-bindings/interconnect/qcom,sc7280.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/mailbox/qcom-ipcc.h>
@@ -162,6 +164,9 @@ CPU0: cpu@0 {
&LITTLE_CPU_SLEEP_1
&CLUSTER_SLEEP_0>;
next-level-cache = <&L2_0>;
operating-points-v2 = <&cpu0_opp_table>;
interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
<&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
qcom,freq-domain = <&cpufreq_hw 0>;
#cooling-cells = <2>;
L2_0: l2-cache {
@@ -182,6 +187,9 @@ CPU1: cpu@100 {
&LITTLE_CPU_SLEEP_1
&CLUSTER_SLEEP_0>;
next-level-cache = <&L2_100>;
operating-points-v2 = <&cpu0_opp_table>;
interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
<&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
qcom,freq-domain = <&cpufreq_hw 0>;
#cooling-cells = <2>;
L2_100: l2-cache {
@@ -199,6 +207,9 @@ CPU2: cpu@200 {
&LITTLE_CPU_SLEEP_1
&CLUSTER_SLEEP_0>;
next-level-cache = <&L2_200>;
operating-points-v2 = <&cpu0_opp_table>;
interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
<&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
qcom,freq-domain = <&cpufreq_hw 0>;
#cooling-cells = <2>;
L2_200: l2-cache {
@@ -216,6 +227,9 @@ CPU3: cpu@300 {
&LITTLE_CPU_SLEEP_1
&CLUSTER_SLEEP_0>;
next-level-cache = <&L2_300>;
operating-points-v2 = <&cpu0_opp_table>;
interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
<&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
qcom,freq-domain = <&cpufreq_hw 0>;
#cooling-cells = <2>;
L2_300: l2-cache {
@@ -233,6 +247,9 @@ CPU4: cpu@400 {
&BIG_CPU_SLEEP_1
&CLUSTER_SLEEP_0>;
next-level-cache = <&L2_400>;
operating-points-v2 = <&cpu4_opp_table>;
interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
<&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
qcom,freq-domain = <&cpufreq_hw 1>;
#cooling-cells = <2>;
L2_400: l2-cache {
@@ -250,6 +267,9 @@ CPU5: cpu@500 {
&BIG_CPU_SLEEP_1
&CLUSTER_SLEEP_0>;
next-level-cache = <&L2_500>;
operating-points-v2 = <&cpu4_opp_table>;
interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
<&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
qcom,freq-domain = <&cpufreq_hw 1>;
#cooling-cells = <2>;
L2_500: l2-cache {
@@ -267,6 +287,9 @@ CPU6: cpu@600 {
&BIG_CPU_SLEEP_1
&CLUSTER_SLEEP_0>;
next-level-cache = <&L2_600>;
operating-points-v2 = <&cpu4_opp_table>;
interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
<&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
qcom,freq-domain = <&cpufreq_hw 1>;
#cooling-cells = <2>;
L2_600: l2-cache {
@@ -284,6 +307,9 @@ CPU7: cpu@700 {
&BIG_CPU_SLEEP_1
&CLUSTER_SLEEP_0>;
next-level-cache = <&L2_700>;
operating-points-v2 = <&cpu7_opp_table>;
interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
<&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>;
qcom,freq-domain = <&cpufreq_hw 2>;
#cooling-cells = <2>;
L2_700: l2-cache {
@@ -383,6 +409,211 @@ CLUSTER_SLEEP_0: cluster-sleep-0 {
};
};
cpu0_opp_table: cpu0-opp-table {
compatible = "operating-points-v2";
opp-shared;
cpu0_opp_300mhz: opp-300000000 {
opp-hz = /bits/ 64 <300000000>;
opp-peak-kBps = <800000 9600000>;
};
cpu0_opp_691mhz: opp-691200000 {
opp-hz = /bits/ 64 <691200000>;
opp-peak-kBps = <800000 17817600>;
};
cpu0_opp_806mhz: opp-806400000 {
opp-hz = /bits/ 64 <806400000>;
opp-peak-kBps = <800000 20889600>;
};
cpu0_opp_941mhz: opp-940800000 {
opp-hz = /bits/ 64 <940800000>;
opp-peak-kBps = <1804000 24576000>;
};
cpu0_opp_1152mhz: opp-1152000000 {
opp-hz = /bits/ 64 <1152000000>;
opp-peak-kBps = <2188000 27033600>;
};
cpu0_opp_1325mhz: opp-1324800000 {
opp-hz = /bits/ 64 <1324800000>;
opp-peak-kBps = <2188000 33792000>;
};
cpu0_opp_1517mhz: opp-1516800000 {
opp-hz = /bits/ 64 <1516800000>;
opp-peak-kBps = <3072000 38092800>;
};
cpu0_opp_1651mhz: opp-1651200000 {
opp-hz = /bits/ 64 <1651200000>;
opp-peak-kBps = <3072000 41779200>;
};
cpu0_opp_1805mhz: opp-1804800000 {
opp-hz = /bits/ 64 <1804800000>;
opp-peak-kBps = <4068000 48537600>;
};
cpu0_opp_1958mhz: opp-1958400000 {
opp-hz = /bits/ 64 <1958400000>;
opp-peak-kBps = <4068000 48537600>;
};
cpu0_opp_2016mhz: opp-2016000000 {
opp-hz = /bits/ 64 <2016000000>;
opp-peak-kBps = <6220000 48537600>;
};
};
cpu4_opp_table: cpu4-opp-table {
compatible = "operating-points-v2";
opp-shared;
cpu4_opp_691mhz: opp-691200000 {
opp-hz = /bits/ 64 <691200000>;
opp-peak-kBps = <1804000 9600000>;
};
cpu4_opp_941mhz: opp-940800000 {
opp-hz = /bits/ 64 <940800000>;
opp-peak-kBps = <2188000 17817600>;
};
cpu4_opp_1229mhz: opp-1228800000 {
opp-hz = /bits/ 64 <1228800000>;
opp-peak-kBps = <4068000 24576000>;
};
cpu4_opp_1344mhz: opp-1344000000 {
opp-hz = /bits/ 64 <1344000000>;
opp-peak-kBps = <4068000 24576000>;
};
cpu4_opp_1517mhz: opp-1516800000 {
opp-hz = /bits/ 64 <1516800000>;
opp-peak-kBps = <4068000 24576000>;
};
cpu4_opp_1651mhz: opp-1651200000 {
opp-hz = /bits/ 64 <1651200000>;
opp-peak-kBps = <6220000 38092800>;
};
cpu4_opp_1901mhz: opp-1900800000 {
opp-hz = /bits/ 64 <1900800000>;
opp-peak-kBps = <6220000 44851200>;
};
cpu4_opp_2054mhz: opp-2054400000 {
opp-hz = /bits/ 64 <2054400000>;
opp-peak-kBps = <6220000 44851200>;
};
cpu4_opp_2112mhz: opp-2112000000 {
opp-hz = /bits/ 64 <2112000000>;
opp-peak-kBps = <6220000 44851200>;
};
cpu4_opp_2131mhz: opp-2131200000 {
opp-hz = /bits/ 64 <2131200000>;
opp-peak-kBps = <6220000 44851200>;
};
cpu4_opp_2208mhz: opp-2208000000 {
opp-hz = /bits/ 64 <2208000000>;
opp-peak-kBps = <6220000 44851200>;
};
cpu4_opp_2400mhz: opp-2400000000 {
opp-hz = /bits/ 64 <2400000000>;
opp-peak-kBps = <8532000 48537600>;
};
cpu4_opp_2611mhz: opp-2611200000 {
opp-hz = /bits/ 64 <2611200000>;
opp-peak-kBps = <8532000 48537600>;
};
};
cpu7_opp_table: cpu7-opp-table {
compatible = "operating-points-v2";
opp-shared;
cpu7_opp_806mhz: opp-806400000 {
opp-hz = /bits/ 64 <806400000>;
opp-peak-kBps = <1804000 9600000>;
};
cpu7_opp_1056mhz: opp-1056000000 {
opp-hz = /bits/ 64 <1056000000>;
opp-peak-kBps = <2188000 17817600>;
};
cpu7_opp_1325mhz: opp-1324800000 {
opp-hz = /bits/ 64 <1324800000>;
opp-peak-kBps = <4068000 24576000>;
};
cpu7_opp_1517mhz: opp-1516800000 {
opp-hz = /bits/ 64 <1516800000>;
opp-peak-kBps = <4068000 24576000>;
};
cpu7_opp_1766mhz: opp-1766400000 {
opp-hz = /bits/ 64 <1766400000>;
opp-peak-kBps = <6220000 38092800>;
};
cpu7_opp_1862mhz: opp-1862400000 {
opp-hz = /bits/ 64 <1862400000>;
opp-peak-kBps = <6220000 38092800>;
};
cpu7_opp_2035mhz: opp-2035200000 {
opp-hz = /bits/ 64 <2035200000>;
opp-peak-kBps = <6220000 38092800>;
};
cpu7_opp_2112mhz: opp-2112000000 {
opp-hz = /bits/ 64 <2112000000>;
opp-peak-kBps = <6220000 44851200>;
};
cpu7_opp_2208mhz: opp-2208000000 {
opp-hz = /bits/ 64 <2208000000>;
opp-peak-kBps = <6220000 44851200>;
};
cpu7_opp_2381mhz: opp-2380800000 {
opp-hz = /bits/ 64 <2380800000>;
opp-peak-kBps = <6832000 44851200>;
};
cpu7_opp_2400mhz: opp-2400000000 {
opp-hz = /bits/ 64 <2400000000>;
opp-peak-kBps = <8532000 48537600>;
};
cpu7_opp_2515mhz: opp-2515200000 {
opp-hz = /bits/ 64 <2515200000>;
opp-peak-kBps = <8532000 48537600>;
};
cpu7_opp_2707mhz: opp-2707200000 {
opp-hz = /bits/ 64 <2707200000>;
opp-peak-kBps = <8532000 48537600>;
};
cpu7_opp_3014mhz: opp-3014400000 {
opp-hz = /bits/ 64 <3014400000>;
opp-peak-kBps = <8532000 48537600>;
};
};
memory@80000000 {
device_type = "memory";
/* We expect the bootloader to fill in the size */
@@ -615,6 +846,9 @@ qfprom: efuse@784000 {
sdhc_1: sdhci@7c4000 {
compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&sdc1_clk>, <&sdc1_cmd>, <&sdc1_data>, <&sdc1_rclk>;
pinctrl-1 = <&sdc1_clk_sleep>, <&sdc1_cmd_sleep>, <&sdc1_data_sleep>, <&sdc1_rclk_sleep>;
status = "disabled";
reg = <0 0x007c4000 0 0x1000>,
@@ -1714,6 +1948,8 @@ ipa: ipa@1e40000 {
interconnect-names = "memory",
"config";
qcom,qmp = <&aoss_qmp>;
qcom,smem-states = <&ipa_smp2p_out 0>,
<&ipa_smp2p_out 1>;
qcom,smem-state-names = "ipa-clock-enabled-valid",
@@ -1790,7 +2026,7 @@ opp-550000000 {
};
};
gmu: gmu@3d69000 {
gmu: gmu@3d6a000 {
compatible="qcom,adreno-gmu-635.0", "qcom,adreno-gmu";
reg = <0 0x03d6a000 0 0x34000>,
<0 0x3de0000 0 0x10000>,
@@ -2424,6 +2660,9 @@ apss_merge_funnel_in: endpoint {
sdhc_2: sdhci@8804000 {
compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&sdc2_clk>, <&sdc2_cmd>, <&sdc2_data>;
pinctrl-1 = <&sdc2_clk_sleep>, <&sdc2_cmd_sleep>, <&sdc2_data_sleep>;
status = "disabled";
reg = <0 0x08804000 0 0x1000>;
@@ -2761,13 +3000,31 @@ videocc: clock-controller@aaf0000 {
#power-domain-cells = <1>;
};
camcc: clock-controller@ad00000 {
compatible = "qcom,sc7280-camcc";
reg = <0 0x0ad00000 0 0x10000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&rpmhcc RPMH_CXO_CLK_A>,
<&sleep_clk>;
clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
dispcc: clock-controller@af00000 {
compatible = "qcom,sc7280-dispcc";
reg = <0 0xaf00000 0 0x20000>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_DISP_GPLL0_CLK_SRC>,
<0>, <0>, <0>, <0>, <0>, <0>;
clock-names = "bi_tcxo", "gcc_disp_gpll0_clk",
<&mdss_dsi_phy 0>,
<&mdss_dsi_phy 1>,
<&dp_phy 0>,
<&dp_phy 1>,
<&mdss_edp_phy 0>,
<&mdss_edp_phy 1>;
clock-names = "bi_tcxo",
"gcc_disp_gpll0_clk",
"dsi0_phy_pll_out_byteclk",
"dsi0_phy_pll_out_dsiclk",
"dp_phy_pll_link_clk",
@@ -2779,6 +3036,389 @@ dispcc: clock-controller@af00000 {
#power-domain-cells = <1>;
};
mdss: display-subsystem@ae00000 {
compatible = "qcom,sc7280-mdss";
reg = <0 0x0ae00000 0 0x1000>;
reg-names = "mdss";
power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>;
clocks = <&gcc GCC_DISP_AHB_CLK>,
<&dispcc DISP_CC_MDSS_AHB_CLK>,
<&dispcc DISP_CC_MDSS_MDP_CLK>;
clock-names = "iface",
"ahb",
"core";
assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>;
assigned-clock-rates = <300000000>;
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <1>;
interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "mdp0-mem";
iommus = <&apps_smmu 0x900 0x402>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
status = "disabled";
mdss_mdp: display-controller@ae01000 {
compatible = "qcom,sc7280-dpu";
reg = <0 0x0ae01000 0 0x8f030>,
<0 0x0aeb0000 0 0x2008>;
reg-names = "mdp", "vbif";
clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
<&gcc GCC_DISP_SF_AXI_CLK>,
<&dispcc DISP_CC_MDSS_AHB_CLK>,
<&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
<&dispcc DISP_CC_MDSS_MDP_CLK>,
<&dispcc DISP_CC_MDSS_VSYNC_CLK>;
clock-names = "bus",
"nrt_bus",
"iface",
"lut",
"core",
"vsync";
assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>,
<&dispcc DISP_CC_MDSS_VSYNC_CLK>,
<&dispcc DISP_CC_MDSS_AHB_CLK>;
assigned-clock-rates = <300000000>,
<19200000>,
<19200000>;
operating-points-v2 = <&mdp_opp_table>;
power-domains = <&rpmhpd SC7280_CX>;
interrupt-parent = <&mdss>;
interrupts = <0>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dpu_intf1_out: endpoint {
remote-endpoint = <&dsi0_in>;
};
};
port@1 {
reg = <1>;
dpu_intf5_out: endpoint {
remote-endpoint = <&edp_in>;
};
};
port@2 {
reg = <2>;
dpu_intf0_out: endpoint {
remote-endpoint = <&dp_in>;
};
};
};
mdp_opp_table: opp-table {
compatible = "operating-points-v2";
opp-200000000 {
opp-hz = /bits/ 64 <200000000>;
required-opps = <&rpmhpd_opp_low_svs>;
};
opp-300000000 {
opp-hz = /bits/ 64 <300000000>;
required-opps = <&rpmhpd_opp_svs>;
};
opp-380000000 {
opp-hz = /bits/ 64 <380000000>;
required-opps = <&rpmhpd_opp_svs_l1>;
};
opp-506666667 {
opp-hz = /bits/ 64 <506666667>;
required-opps = <&rpmhpd_opp_nom>;
};
};
};
mdss_dsi: dsi@ae94000 {
compatible = "qcom,mdss-dsi-ctrl";
reg = <0 0x0ae94000 0 0x400>;
reg-names = "dsi_ctrl";
interrupt-parent = <&mdss>;
interrupts = <4>;
clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
<&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
<&dispcc DISP_CC_MDSS_PCLK0_CLK>,
<&dispcc DISP_CC_MDSS_ESC0_CLK>,
<&dispcc DISP_CC_MDSS_AHB_CLK>,
<&gcc GCC_DISP_HF_AXI_CLK>;
clock-names = "byte",
"byte_intf",
"pixel",
"core",
"iface",
"bus";
operating-points-v2 = <&dsi_opp_table>;
power-domains = <&rpmhpd SC7280_CX>;
phys = <&mdss_dsi_phy>;
phy-names = "dsi";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dsi0_in: endpoint {
remote-endpoint = <&dpu_intf1_out>;
};
};
port@1 {
reg = <1>;
dsi0_out: endpoint {
};
};
};
dsi_opp_table: opp-table {
compatible = "operating-points-v2";
opp-187500000 {
opp-hz = /bits/ 64 <187500000>;
required-opps = <&rpmhpd_opp_low_svs>;
};
opp-300000000 {
opp-hz = /bits/ 64 <300000000>;
required-opps = <&rpmhpd_opp_svs>;
};
opp-358000000 {
opp-hz = /bits/ 64 <358000000>;
required-opps = <&rpmhpd_opp_svs_l1>;
};
};
};
mdss_dsi_phy: phy@ae94400 {
compatible = "qcom,sc7280-dsi-phy-7nm";
reg = <0 0x0ae94400 0 0x200>,
<0 0x0ae94600 0 0x280>,
<0 0x0ae94900 0 0x280>;
reg-names = "dsi_phy",
"dsi_phy_lane",
"dsi_pll";
#clock-cells = <1>;
#phy-cells = <0>;
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
<&rpmhcc RPMH_CXO_CLK>;
clock-names = "iface", "ref";
status = "disabled";
};
mdss_edp: edp@aea0000 {
compatible = "qcom,sc7280-edp";
pinctrl-names = "default";
pinctrl-0 = <&edp_hot_plug_det>;
reg = <0 0xaea0000 0 0x200>,
<0 0xaea0200 0 0x200>,
<0 0xaea0400 0 0xc00>,
<0 0xaea1000 0 0x400>;
interrupt-parent = <&mdss>;
interrupts = <14>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_EDP_CLKREF_EN>,
<&dispcc DISP_CC_MDSS_AHB_CLK>,
<&dispcc DISP_CC_MDSS_EDP_AUX_CLK>,
<&dispcc DISP_CC_MDSS_EDP_LINK_CLK>,
<&dispcc DISP_CC_MDSS_EDP_LINK_INTF_CLK>,
<&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK>;
clock-names = "core_xo",
"core_ref",
"core_iface",
"core_aux",
"ctrl_link",
"ctrl_link_iface",
"stream_pixel";
#clock-cells = <1>;
assigned-clocks = <&dispcc DISP_CC_MDSS_EDP_LINK_CLK_SRC>,
<&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK_SRC>;
assigned-clock-parents = <&mdss_edp_phy 0>, <&mdss_edp_phy 1>;
phys = <&mdss_edp_phy>;
phy-names = "dp";
operating-points-v2 = <&edp_opp_table>;
power-domains = <&rpmhpd SC7280_CX>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
edp_in: endpoint {
remote-endpoint = <&dpu_intf5_out>;
};
};
port@1 {
reg = <1>;
edp_out: endpoint { };
};
};
edp_opp_table: opp-table {
compatible = "operating-points-v2";
opp-160000000 {
opp-hz = /bits/ 64 <160000000>;
required-opps = <&rpmhpd_opp_low_svs>;
};
opp-270000000 {
opp-hz = /bits/ 64 <270000000>;
required-opps = <&rpmhpd_opp_svs>;
};
opp-540000000 {
opp-hz = /bits/ 64 <540000000>;
required-opps = <&rpmhpd_opp_nom>;
};
opp-810000000 {
opp-hz = /bits/ 64 <810000000>;
required-opps = <&rpmhpd_opp_nom>;
};
};
};
mdss_edp_phy: phy@aec2a00 {
compatible = "qcom,sc7280-edp-phy";
reg = <0 0xaec2a00 0 0x19c>,
<0 0xaec2200 0 0xa0>,
<0 0xaec2600 0 0xa0>,
<0 0xaec2000 0 0x1c0>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_EDP_CLKREF_EN>;
clock-names = "aux",
"cfg_ahb";
#clock-cells = <1>;
#phy-cells = <0>;
status = "disabled";
};
mdss_dp: displayport-controller@ae90000 {
compatible = "qcom,sc7280-dp";
reg = <0 0x0ae90000 0 0x1400>;
interrupt-parent = <&mdss>;
interrupts = <12>;
clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
<&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
<&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
<&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
<&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
clock-names = "core_iface",
"core_aux",
"ctrl_link",
"ctrl_link_iface",
"stream_pixel";
#clock-cells = <1>;
assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
<&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
phys = <&dp_phy>;
phy-names = "dp";
operating-points-v2 = <&dp_opp_table>;
power-domains = <&rpmhpd SC7280_CX>;
#sound-dai-cells = <0>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dp_in: endpoint {
remote-endpoint = <&dpu_intf0_out>;
};
};
port@1 {
reg = <1>;
dp_out: endpoint { };
};
};
dp_opp_table: opp-table {
compatible = "operating-points-v2";
opp-160000000 {
opp-hz = /bits/ 64 <160000000>;
required-opps = <&rpmhpd_opp_low_svs>;
};
opp-270000000 {
opp-hz = /bits/ 64 <270000000>;
required-opps = <&rpmhpd_opp_svs>;
};
opp-540000000 {
opp-hz = /bits/ 64 <540000000>;
required-opps = <&rpmhpd_opp_svs_l1>;
};
opp-810000000 {
opp-hz = /bits/ 64 <810000000>;
required-opps = <&rpmhpd_opp_nom>;
};
};
};
};
pdc: interrupt-controller@b220000 {
compatible = "qcom,sc7280-pdc", "qcom,pdc";
reg = <0 0x0b220000 0 0x30000>;
@@ -2872,11 +3512,19 @@ tlmm: pinctrl@f100000 {
gpio-ranges = <&tlmm 0 0 175>;
wakeup-parent = <&pdc>;
dp_hot_plug_det: dp-hot-plug-det {
pins = "gpio47";
function = "dp_hot";
};
edp_hot_plug_det: edp-hot-plug-det {
pins = "gpio60";
function = "edp_hot";
};
pcie1_clkreq_n: pcie1-clkreq-n {
pins = "gpio79";
function = "pcie1_clkreqn";
drive-strength = <2>;
bias-pull-up;
};
qspi_clk: qspi-clk {
@@ -3384,83 +4032,6 @@ qup_uart7_rx: qup-uart7-rx {
function = "qup07";
};
sdc1_on: sdc1-on {
clk {
pins = "sdc1_clk";
};
cmd {
pins = "sdc1_cmd";
};
data {
pins = "sdc1_data";
};
rclk {
pins = "sdc1_rclk";
};
};
sdc1_off: sdc1-off {
clk {
pins = "sdc1_clk";
drive-strength = <2>;
bias-bus-hold;
};
cmd {
pins = "sdc1_cmd";
drive-strength = <2>;
bias-bus-hold;
};
data {
pins = "sdc1_data";
drive-strength = <2>;
bias-bus-hold;
};
rclk {
pins = "sdc1_rclk";
bias-bus-hold;
};
};
sdc2_on: sdc2-on {
clk {
pins = "sdc2_clk";
};
cmd {
pins = "sdc2_cmd";
};
data {
pins = "sdc2_data";
};
};
sdc2_off: sdc2-off {
clk {
pins = "sdc2_clk";
drive-strength = <2>;
bias-bus-hold;
};
cmd {
pins ="sdc2_cmd";
drive-strength = <2>;
bias-bus-hold;
};
data {
pins ="sdc2_data";
drive-strength = <2>;
bias-bus-hold;
};
};
qup_uart8_cts: qup-uart8-cts {
pins = "gpio32";
function = "qup10";
@@ -3620,6 +4191,76 @@ qup_uart15_rx: qup-uart15-rx {
pins = "gpio63";
function = "qup17";
};
sdc1_clk: sdc1-clk {
pins = "sdc1_clk";
};
sdc1_cmd: sdc1-cmd {
pins = "sdc1_cmd";
};
sdc1_data: sdc1-data {
pins = "sdc1_data";
};
sdc1_rclk: sdc1-rclk {
pins = "sdc1_rclk";
};
sdc1_clk_sleep: sdc1-clk-sleep {
pins = "sdc1_clk";
drive-strength = <2>;
bias-bus-hold;
};
sdc1_cmd_sleep: sdc1-cmd-sleep {
pins = "sdc1_cmd";
drive-strength = <2>;
bias-bus-hold;
};
sdc1_data_sleep: sdc1-data-sleep {
pins = "sdc1_data";
drive-strength = <2>;
bias-bus-hold;
};
sdc1_rclk_sleep: sdc1-rclk-sleep {
pins = "sdc1_rclk";
drive-strength = <2>;
bias-bus-hold;
};
sdc2_clk: sdc2-clk {
pins = "sdc2_clk";
};
sdc2_cmd: sdc2-cmd {
pins = "sdc2_cmd";
};
sdc2_data: sdc2-data {
pins = "sdc2_data";
};
sdc2_clk_sleep: sdc2-clk-sleep {
pins = "sdc2_clk";
drive-strength = <2>;
bias-bus-hold;
};
sdc2_cmd_sleep: sdc2-cmd-sleep {
pins = "sdc2_cmd";
drive-strength = <2>;
bias-bus-hold;
};
sdc2_data_sleep: sdc2-data-sleep {
pins = "sdc2_data";
drive-strength = <2>;
bias-bus-hold;
};
};
imem@146a5000 {
@@ -3885,6 +4526,14 @@ rpmhcc: clock-controller {
};
};
epss_l3: interconnect@18590000 {
compatible = "qcom,sc7280-epss-l3";
reg = <0 0x18590000 0 0x1000>;
clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
clock-names = "xo", "alternate";
#interconnect-cells = <1>;
};
cpufreq_hw: cpufreq@18591000 {
compatible = "qcom,cpufreq-epss";
reg = <0 0x18591000 0 0x1000>,

2
arch/arm64/boot/dts/qcom/sdm630.dtsi
View File

@@ -2160,7 +2160,7 @@ glink-edge {
apr {
compatible = "qcom,apr-v2";
qcom,glink-channels = "apr_audio_svc";
qcom,apr-domain = <APR_DOMAIN_ADSP>;
qcom,domain = <APR_DOMAIN_ADSP>;
#address-cells = <1>;
#size-cells = <0>;

183
arch/arm64/boot/dts/qcom/sdm632-fairphone-fp3.dts Normal file
View File

@@ -0,0 +1,183 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2022, Luca Weiss <luca@z3ntu.xyz>
*/
/dts-v1/;
#include "sdm632.dtsi"
#include "pm8953.dtsi"
/ {
model = "Fairphone 3";
compatible = "fairphone,fp3", "qcom,sdm632";
chassis-type = "handset";
qcom,msm-id = <349 0>;
qcom,board-id = <8 0x10000>;
aliases {
mmc0 = &sdhc_1;
mmc1 = &sdhc_2;
serial0 = &uart_0;
};
chosen {
stdout-path = "serial0:115200n8";
};
gpio-keys {
compatible = "gpio-keys";
volume-up {
label = "volume_up";
linux,code = <KEY_VOLUMEUP>;
gpios = <&tlmm 85 GPIO_ACTIVE_LOW>;
};
};
vph_pwr: vph-pwr-regulator {
compatible = "regulator-fixed";
regulator-name = "vph_pwr";
regulator-always-on;
regulator-boot-on;
};
};
&hsusb_phy {
status = "okay";
vdd-supply = <&pm8953_l3>;
vdda-pll-supply = <&pm8953_l7>;
vdda-phy-dpdm-supply = <&pm8953_l13>;
};
&pm8953_resin {
status = "okay";
linux,code = <KEY_VOLUMEDOWN>;
};
&sdhc_1 {
status = "okay";
vmmc-supply = <&pm8953_l8>;
vqmmc-supply = <&pm8953_l5>;
};
&sdhc_2 {
status = "okay";
vmmc-supply = <&pm8953_l11>;
vqmmc-supply = <&pm8953_l12>;
cd-gpios = <&tlmm 133 GPIO_ACTIVE_LOW>;
};
&rpm_requests {
pm8953-regulators {
compatible = "qcom,rpm-pm8953-regulators";
vdd_l1-supply = <&pm8953_s3>;
vdd_l2_l3-supply = <&pm8953_s3>;
vdd_l4_l5_l6_l7_l16_l19-supply = <&pm8953_s4>;
vdd_l8_l11_l12_l13_l14_l15-supply = <&vph_pwr>;
vdd_l9_l10_l17_l18_l22-supply = <&vph_pwr>;
pm8953_s3: s3 {
regulator-min-microvolt = <984000>;
regulator-max-microvolt = <1240000>;
};
pm8953_s4: s4 {
regulator-min-microvolt = <1036000>;
regulator-max-microvolt = <2040000>;
};
pm8953_s5: s5 {
regulator-min-microvolt = <1036000>;
regulator-max-microvolt = <2040000>;
};
pm8953_l1: l1 {
regulator-min-microvolt = <975000>;
regulator-max-microvolt = <1050000>;
};
pm8953_l2: l2 {
regulator-min-microvolt = <975000>;
regulator-max-microvolt = <1175000>;
};
pm8953_l3: l3 {
regulator-min-microvolt = <925000>;
regulator-max-microvolt = <925000>;
};
pm8953_l5: l5 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
pm8953_l6: l6 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
pm8953_l7: l7 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1900000>;
};
pm8953_l8: l8 {
regulator-min-microvolt = <2900000>;
regulator-max-microvolt = <2900000>;
};
pm8953_l9: l9 {
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3300000>;
};
pm8953_l10: l10 {
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <3000000>;
};
pm8953_l11: l11 {
regulator-min-microvolt = <2950000>;
regulator-max-microvolt = <2950000>;
};
pm8953_l12: l12 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <2950000>;
};
pm8953_l13: l13 {
regulator-min-microvolt = <3125000>;
regulator-max-microvolt = <3125000>;
};
pm8953_l16: l16 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
pm8953_l17: l17 {
regulator-min-microvolt = <2850000>;
regulator-max-microvolt = <2850000>;
};
pm8953_l19: l19 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1350000>;
};
pm8953_l22: l22 {
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
};
pm8953_l23: l23 {
regulator-min-microvolt = <975000>;
regulator-max-microvolt = <1225000>;
};
};
};
&tlmm {
/*
* 0-3: unused but protected by TZ
* 135-138: fingerprint reader (SPI)
*/
gpio-reserved-ranges = <0 4>, <135 4>;
};
&uart_0 {
status = "okay";
};
&usb3 {
status = "okay";
};
&usb3_dwc3 {
dr_mode = "peripheral";
};

81
arch/arm64/boot/dts/qcom/sdm632.dtsi Normal file
View File

@@ -0,0 +1,81 @@
// SPDX-License-Identifier: BSD-3-Clause
/* Copyright (c) 2022, The Linux Foundation. All rights reserved. */
#include "msm8953.dtsi"
/ {
thermal-zones {
/delete-node/cpu1-thermal;
/delete-node/cpu2-thermal;
/delete-node/cpu3-thermal;
cpu0-thermal {
thermal-sensors = <&tsens0 13>;
cooling-maps {
map0 {
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
cpu4-thermal {
thermal-sensors = <&tsens0 5>;
};
cpu5-thermal {
thermal-sensors = <&tsens0 6>;
};
cpu6-thermal {
thermal-sensors = <&tsens0 7>;
};
cpu7-thermal {
thermal-sensors = <&tsens0 8>;
};
};
};
/*
* SDM632 uses Kryo 250 instead of Cortex A53
* CPU0-3 are efficiency cores, CPU4-7 are performance cores
*/
&CPU0 {
compatible = "qcom,kryo250";
};
&CPU1 {
compatible = "qcom,kryo250";
};
&CPU2 {
compatible = "qcom,kryo250";
};
&CPU3 {
compatible = "qcom,kryo250";
};
&CPU4 {
compatible = "qcom,kryo250";
capacity-dmips-mhz = <1980>;
};
&CPU5 {
compatible = "qcom,kryo250";
capacity-dmips-mhz = <1980>;
};
&CPU6 {
compatible = "qcom,kryo250";
capacity-dmips-mhz = <1980>;
};
&CPU7 {
compatible = "qcom,kryo250";
capacity-dmips-mhz = <1980>;
};

2
arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi
View File

@@ -708,7 +708,7 @@ cros_ec: ec@0 {
pinctrl-0 = <&ec_ap_int_l>;
spi-max-frequency = <3000000>;
cros_ec_pwm: ec-pwm {
cros_ec_pwm: pwm {
compatible = "google,cros-ec-pwm";
#pwm-cells = <1>;
};

7
arch/arm64/boot/dts/qcom/sdm845-db845c.dts
View File

@@ -425,6 +425,10 @@ &gmu {
status = "okay";
};
&gpi_dma0 {
status = "okay";
};
&gpu {
status = "okay";
zap-shader {
@@ -1125,7 +1129,6 @@ ports {
port@0 {
reg = <0>;
csiphy0_ep: endpoint {
clock-lanes = <7>;
data-lanes = <0 1 2 3>;
remote-endpoint = <&ov8856_ep>;
};
@@ -1166,7 +1169,6 @@ camera@10 {
port {
ov8856_ep: endpoint {
clock-lanes = <1>;
link-frequencies = /bits/ 64
<360000000 180000000>;
data-lanes = <1 2 3 4>;
@@ -1211,7 +1213,6 @@ camera@60 {
port {
ov7251_ep: endpoint {
clock-lanes = <1>;
data-lanes = <0 1>;
// remote-endpoint = <&csiphy3_ep>;
};

19
arch/arm64/boot/dts/qcom/sdm845-oneplus-common.dtsi
View File

@@ -54,7 +54,7 @@ reserved-memory {
* it is otherwise possible for an allocation adjacent to the
* rmtfs_mem region to trigger an XPU violation, causing a crash.
*/
rmtfs_lower_guard: memory@f5b00000 {
rmtfs_lower_guard: rmtfs-lower-guard@f5b00000 {
no-map;
reg = <0 0xf5b00000 0 0x1000>;
};
@@ -63,7 +63,7 @@ rmtfs_lower_guard: memory@f5b00000 {
* but given the same address every time. Hard code it as this address is
* where the modem firmware expects it to be.
*/
rmtfs_mem: memory@f5b01000 {
rmtfs_mem: rmtfs-mem@f5b01000 {
compatible = "qcom,rmtfs-mem";
reg = <0 0xf5b01000 0 0x200000>;
no-map;
@@ -71,7 +71,7 @@ rmtfs_mem: memory@f5b01000 {
qcom,client-id = <1>;
qcom,vmid = <15>;
};
rmtfs_upper_guard: memory@f5d01000 {
rmtfs_upper_guard: rmtfs-upper-guard@f5d01000 {
no-map;
reg = <0 0xf5d01000 0 0x1000>;
};
@@ -80,7 +80,7 @@ rmtfs_upper_guard: memory@f5d01000 {
* It seems like reserving the old rmtfs_mem region is also needed to prevent
* random crashes which are most likely modem related, more testing needed.
*/
removed_region: memory@88f00000 {
removed_region: removed-region@88f00000 {
no-map;
reg = <0 0x88f00000 0 0x1c00000>;
};
@@ -376,6 +376,17 @@ zap-shader {
};
};
&i2c10 {
status = "okay";
clock-frequency = <100000>;
bq27441_fg: bq27441-battery@55 {
compatible = "ti,bq27411";
status = "okay";
reg = <0x55>;
};
};
&i2c12 {
status = "okay";
clock-frequency = <400000>;

12
arch/arm64/boot/dts/qcom/sdm845-oneplus-enchilada.dts
View File

@@ -13,6 +13,14 @@ / {
chassis-type = "handset";
qcom,msm-id = <0x141 0x20001>;
qcom,board-id = <8 0 17819 22>;
battery: battery {
compatible = "simple-battery";
charge-full-design-microamp-hours = <3300000>;
voltage-min-design-microvolt = <3400000>;
voltage-max-design-microvolt = <4400000>;
};
};
&display_panel {
@@ -20,3 +28,7 @@ &display_panel {
compatible = "samsung,sofef00";
};
&bq27441_fg {
monitored-battery = <&battery>;
};

12
arch/arm64/boot/dts/qcom/sdm845-oneplus-fajita.dts
View File

@@ -13,6 +13,14 @@ / {
chassis-type = "handset";
qcom,msm-id = <0x141 0x20001>;
qcom,board-id = <8 0 18801 41>;
battery: battery {
compatible = "simple-battery";
charge-full-design-microamp-hours = <3700000>;
voltage-min-design-microvolt = <3400000>;
voltage-max-design-microvolt = <4400000>;
};
};
&display_panel {
@@ -21,6 +29,10 @@ &display_panel {
compatible = "samsung,s6e3fc2x01";
};
&bq27441_fg {
monitored-battery = <&battery>;
};
&rmi4_f12 {
touchscreen-y-mm = <148>;
};

736
arch/arm64/boot/dts/qcom/sdm845-shift-axolotl.dts Normal file
View File

@@ -0,0 +1,736 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2022, Alexander Martinz <amartinz@shiftphones.com>
* Copyright (c) 2022, Caleb Connolly <caleb@connolly.tech>
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
#include "sdm845.dtsi"
#include "pm8998.dtsi"
#include "pmi8998.dtsi"
/ {
model = "SHIFT SHIFT6mq";
compatible = "shift,axolotl", "qcom,sdm845";
qcom,msm-id = <321 0x20001>;
qcom,board-id = <11 0>;
aliases {
display0 = &framebuffer0;
serial0 = &uart9;
};
chosen {
#address-cells = <2>;
#size-cells = <2>;
ranges;
stdout-path = "serial0";
/* Use framebuffer setup by the bootloader. */
framebuffer0: framebuffer@9d400000 {
compatible = "simple-framebuffer";
reg = <0x0 0x9d400000 0x0 (1080 * 2160 * 4)>;
width = <1080>;
height = <2160>;
stride = <(1080 * 4)>;
format = "a8r8g8b8";
};
};
gpio-keys {
compatible = "gpio-keys";
autorepeat;
pinctrl-names = "default";
pinctrl-0 = <&volume_up_gpio>;
vol-up {
label = "volume_up";
linux,code = <KEY_VOLUMEUP>;
gpios = <&pm8998_gpio 6 GPIO_ACTIVE_LOW>;
debounce-interval = <15>;
};
};
reserved-memory {
framebuffer_region@9d400000 {
reg = <0x0 0x9d400000 0x0 (1080 * 2160 * 4)>;
no-map;
};
ramoops: ramoops@b0000000 {
compatible = "ramoops";
reg = <0 0xb0000000 0 0x00400000>;
record-size = <0x40000>;
console-size = <0x40000>;
ftrace-size = <0x40000>;
pmsg-size = <0x200000>;
ecc-size = <0x0>;
};
};
battery: battery {
compatible = "simple-battery";
charge-full-design-microamp-hours = <3850000>;
voltage-min-design-microvolt = <3600000>;
voltage-max-design-microvolt = <4400000>;
};
vph_pwr: vph-pwr-regulator {
compatible = "regulator-fixed";
regulator-name = "vph_pwr";
regulator-min-microvolt = <3700000>;
regulator-max-microvolt = <3700000>;
};
vreg_s4a_1p8: pm8998-smps4 {
compatible = "regulator-fixed";
regulator-name = "vreg_s4a_1p8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
vin-supply = <&vph_pwr>;
};
};
&adsp_pas {
status = "okay";
firmware-name = "qcom/sdm845/axolotl/adsp.mbn";
};
&apps_rsc {
pm8998-rpmh-regulators {
compatible = "qcom,pm8998-rpmh-regulators";
qcom,pmic-id = "a";
vdd-s1-supply = <&vph_pwr>;
vdd-s2-supply = <&vph_pwr>;
vdd-s3-supply = <&vph_pwr>;
vdd-s4-supply = <&vph_pwr>;
vdd-s5-supply = <&vph_pwr>;
vdd-s6-supply = <&vph_pwr>;
vdd-s7-supply = <&vph_pwr>;
vdd-s8-supply = <&vph_pwr>;
vdd-s9-supply = <&vph_pwr>;
vdd-s10-supply = <&vph_pwr>;
vdd-s11-supply = <&vph_pwr>;
vdd-s12-supply = <&vph_pwr>;
vdd-s13-supply = <&vph_pwr>;
vdd-l1-l27-supply = <&vreg_s7a_1p025>;
vdd-l2-l8-l17-supply = <&vreg_s3a_1p35>;
vdd-l3-l11-supply = <&vreg_s7a_1p025>;
vdd-l4-l5-supply = <&vreg_s7a_1p025>;
vdd-l6-supply = <&vph_pwr>;
vdd-l7-l12-l14-l15-supply = <&vreg_s5a_2p04>;
vdd-l9-supply = <&vreg_bob>;
vdd-l10-l23-l25-supply = <&vreg_bob>;
vdd-l13-l19-l21-supply = <&vreg_bob>;
vdd-l16-l28-supply = <&vreg_bob>;
vdd-l18-l22-supply = <&vreg_bob>;
vdd-l20-l24-supply = <&vreg_bob>;
vdd-l26-supply = <&vreg_s3a_1p35>;
vin-lvs-1-2-supply = <&vreg_s4a_1p8>;
vreg_s2a_1p125: smps2 {
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
};
vreg_s3a_1p35: smps3 {
regulator-min-microvolt = <1352000>;
regulator-max-microvolt = <1352000>;
};
vreg_s5a_2p04: smps5 {
regulator-min-microvolt = <1904000>;
regulator-max-microvolt = <2040000>;
};
vreg_s7a_1p025: smps7 {
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <1028000>;
};
vdd_qusb_hs0:
vdda_hp_pcie_core:
vdda_mipi_csi0_0p9:
vdda_mipi_csi1_0p9:
vdda_mipi_csi2_0p9:
vdda_mipi_dsi0_pll:
vdda_mipi_dsi1_pll:
vdda_qlink_lv:
vdda_qlink_lv_ck:
vdda_qrefs_0p875:
vdda_pcie_core:
vdda_pll_cc_ebi01:
vdda_pll_cc_ebi23:
vdda_sp_sensor:
vdda_ufs1_core:
vdda_ufs2_core:
vdda_usb1_ss_core:
vdda_usb2_ss_core:
vreg_l1a_0p875: ldo1 {
regulator-min-microvolt = <880000>;
regulator-max-microvolt = <880000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vddpx_10:
vreg_l2a_1p2: ldo2 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-always-on;
};
vreg_l3a_1p0: ldo3 {
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vdd_wcss_cx:
vdd_wcss_mx:
vdda_wcss_pll:
vreg_l5a_0p8: ldo5 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <800000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vddpx_13:
vreg_l6a_1p8: ldo6 {
regulator-min-microvolt = <1856000>;
regulator-max-microvolt = <1856000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l7a_1p8: ldo7 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l8a_1p2: ldo8 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1248000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l9a_1p8: ldo9 {
regulator-min-microvolt = <1704000>;
regulator-max-microvolt = <2928000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l10a_1p8: ldo10 {
regulator-min-microvolt = <1704000>;
regulator-max-microvolt = <2928000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l11a_1p0: ldo11 {
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1048000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vdd_qfprom:
vdd_qfprom_sp:
vdda_apc1_cs_1p8:
vdda_gfx_cs_1p8:
vdda_qrefs_1p8:
vdda_qusb_hs0_1p8:
vddpx_11:
vreg_l12a_1p8: ldo12 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vddpx_2:
vreg_l13a_2p95: ldo13 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <2960000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l14a_1p88: ldo14 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l15a_1p8: ldo15 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l16a_2p7: ldo16 {
regulator-min-microvolt = <2704000>;
regulator-max-microvolt = <2704000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l17a_1p3: ldo17 {
regulator-min-microvolt = <1304000>;
regulator-max-microvolt = <1304000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l18a_2p7: ldo18 {
regulator-min-microvolt = <2704000>;
regulator-max-microvolt = <2960000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l19a_3p0: ldo19 {
regulator-min-microvolt = <2856000>;
regulator-max-microvolt = <3104000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l20a_2p95: ldo20 {
regulator-min-microvolt = <2704000>;
regulator-max-microvolt = <2960000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l21a_2p95: ldo21 {
regulator-min-microvolt = <2704000>;
regulator-max-microvolt = <2960000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l22a_2p85: ldo22 {
regulator-min-microvolt = <2864000>;
regulator-max-microvolt = <3312000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l23a_3p3: ldo23 {
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3312000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vdda_qusb_hs0_3p1:
vreg_l24a_3p075: ldo24 {
regulator-min-microvolt = <3088000>;
regulator-max-microvolt = <3088000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l25a_3p3: ldo25 {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3312000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vdda_hp_pcie_1p2:
vdda_hv_ebi0:
vdda_hv_ebi1:
vdda_hv_ebi2:
vdda_hv_ebi3:
vdda_mipi_csi_1p25:
vdda_mipi_dsi0_1p2:
vdda_mipi_dsi1_1p2:
vdda_pcie_1p2:
vdda_ufs1_1p2:
vdda_ufs2_1p2:
vdda_usb1_ss_1p2:
vdda_usb2_ss_1p2:
vreg_l26a_1p2: ldo26 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l28a_3p0: ldo28 {
regulator-min-microvolt = <2856000>;
regulator-max-microvolt = <3008000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_lvs1a_1p8: lvs1 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
vreg_lvs2a_1p8: lvs2 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
};
pmi8998-rpmh-regulators {
compatible = "qcom,pmi8998-rpmh-regulators";
qcom,pmic-id = "b";
vdd-bob-supply = <&vph_pwr>;
vreg_bob: bob {
regulator-min-microvolt = <3312000>;
regulator-max-microvolt = <3600000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
regulator-allow-bypass;
};
};
pm8005-rpmh-regulators {
compatible = "qcom,pm8005-rpmh-regulators";
qcom,pmic-id = "c";
vdd-s1-supply = <&vph_pwr>;
vdd-s2-supply = <&vph_pwr>;
vdd-s3-supply = <&vph_pwr>;
vdd-s4-supply = <&vph_pwr>;
vreg_s3c_0p6: smps3 {
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <600000>;
};
};
};
&cdsp_pas {
status = "okay";
firmware-name = "qcom/sdm845/axolotl/cdsp.mbn";
};
&dsi0 {
status = "okay";
vdda-supply = <&vdda_mipi_dsi0_1p2>;
panel@0 {
compatible = "visionox,rm69299-shift";
status = "okay";
reg = <0>;
vdda-supply = <&vreg_l14a_1p88>;
vdd3p3-supply = <&vreg_l28a_3p0>;
#address-cells = <1>;
#size-cells = <0>;
reset-gpios = <&tlmm 6 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&sde_dsi_active &sde_te_active>;
pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
port {
panel_in_0: endpoint {
remote-endpoint = <&dsi0_out>;
};
};
};
};
&dsi0_out {
remote-endpoint = <&panel_in_0>;
data-lanes = <0 1 2 3>;
};
&dsi0_phy {
status = "okay";
vdds-supply = <&vdda_mipi_dsi0_pll>;
};
&gcc {
protected-clocks = <GCC_QSPI_CORE_CLK>,
<GCC_QSPI_CORE_CLK_SRC>,
<GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
<GCC_LPASS_Q6_AXI_CLK>,
<GCC_LPASS_SWAY_CLK>;
};
&gmu {
status = "okay";
};
&gpu {
status = "okay";
zap-shader {
memory-region = <&gpu_mem>;
firmware-name = "qcom/sdm845/axolotl/a630_zap.mbn";
};
};
&i2c5 {
status="okay";
touchscreen@38 {
compatible = "focaltech,fts8719";
reg = <0x38>;
wakeup-source;
interrupt-parent = <&tlmm>;
interrupts = <125 0x2>;
vdd-supply = <&vreg_l28a_3p0>;
vcc-i2c-supply = <&vreg_l14a_1p88>;
pinctrl-names = "default", "suspend";
pinctrl-0 = <&ts_int_active &ts_reset_active>;
pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>;
reset-gpio = <&tlmm 99 GPIO_ACTIVE_HIGH>;
irq-gpio = <&tlmm 125 GPIO_TRANSITORY>;
touchscreen-size-x = <1080>;
touchscreen-size-y = <2160>;
focaltech,max-touch-number = <5>;
};
};
&ipa {
status = "okay";
memory-region = <&ipa_fw_mem>;
firmware-name = "qcom/sdm845/axolotl/ipa_fws.mbn";
};
&mdss {
status = "okay";
};
&mss_pil {
status = "okay";
firmware-name = "qcom/sdm845/axolotl/mba.mbn", "qcom/sdm845/axolotl/modem.mbn";
};
&pm8998_gpio {
volume_up_gpio: pm8998_gpio6 {
pinconf {
pins = "gpio6";
function = "normal";
input-enable;
bias-pull-up;
qcom,drive-strength = <0>;
};
};
};
&pm8998_pon {
volume_down_resin: resin {
compatible = "qcom,pm8941-resin";
interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>;
debounce = <15625>;
bias-pull-up;
linux,code = <KEY_VOLUMEDOWN>;
};
};
&qup_uart9_default {
pinconf-rx {
pins = "gpio5";
drive-strength = <2>;
bias-pull-up;
};
pinconf-tx {
pins = "gpio4";
drive-strength = <2>;
bias-disable;
};
};
&qupv3_id_0 {
status = "okay";
};
&qupv3_id_1 {
status = "okay";
};
&tlmm {
gpio-reserved-ranges = <0 4>, <81 4>;
sde_dsi_active: sde-dsi-active {
mux {
pins = "gpio6", "gpio11";
function = "gpio";
};
config {
pins = "gpio6", "gpio11";
drive-strength = <8>;
bias-disable = <0>;
};
};
sde_dsi_suspend: sde-dsi-suspend {
mux {
pins = "gpio6", "gpio11";
function = "gpio";
};
config {
pins = "gpio6", "gpio11";
drive-strength = <2>;
bias-pull-down;
};
};
sde_te_active: sde-te-active {
mux {
pins = "gpio10";
function = "mdp_vsync";
};
config {
pins = "gpio10";
drive-strength = <2>;
bias-pull-down;
};
};
sde_te_suspend: sde-te-suspend {
mux {
pins = "gpio10";
function = "mdp_vsync";
};
config {
pins = "gpio10";
drive-strength = <2>;
bias-pull-down;
};
};
ts_int_active: ts-int-active {
mux {
pins = "gpio125";
function = "gpio";
};
config {
pins = "gpio125";
drive-strength = <8>;
bias-pull-up;
input-enable;
};
};
ts_int_suspend: ts-int-suspend {
mux {
pins = "gpio125";
function = "gpio";
};
config {
pins = "gpio125";
drive-strength = <2>;
bias-pull-down;
input-enable;
};
};
ts_reset_active: ts-reset-active {
mux {
pins = "gpio99";
function = "gpio";
};
config {
pins = "gpio99";
drive-strength = <8>;
bias-pull-up;
};
};
ts_reset_suspend: ts-reset-suspend {
mux {
pins = "gpio99";
function = "gpio";
};
config {
pins = "gpio99";
drive-strength = <2>;
bias-pull-down;
};
};
};
&uart6 {
status = "okay";
bluetooth {
compatible = "qcom,wcn3990-bt";
vddio-supply = <&vreg_s4a_1p8>;
vddxo-supply = <&vreg_l7a_1p8>;
vddrf-supply = <&vreg_l17a_1p3>;
vddch0-supply = <&vreg_l25a_3p3>;
max-speed = <3200000>;
};
};
&uart9 {
status = "okay";
};
&ufs_mem_hc {
status = "okay";
reset-gpios = <&tlmm 150 GPIO_ACTIVE_LOW>;
vcc-supply = <&vreg_l20a_2p95>;
vcc-max-microamp = <600000>;
};
&ufs_mem_phy {
status = "okay";
vdda-phy-supply = <&vdda_ufs1_core>;
vdda-pll-supply = <&vdda_ufs1_1p2>;
};
&usb_1 {
status = "okay";
};
&usb_1_dwc3 {
dr_mode = "peripheral";
};
&usb_1_hsphy {
status = "okay";
vdd-supply = <&vreg_l1a_0p875>;
vdda-phy-dpdm-supply = <&vreg_l24a_3p075>;
vdda-pll-supply = <&vreg_l12a_1p8>;
};
&usb_1_qmpphy {
status = "okay";
vdda-phy-supply = <&vreg_l26a_1p2>;
vdda-pll-supply = <&vreg_l1a_0p875>;
};
&venus {
status = "okay";
firmware-name = "qcom/sdm845/axolotl/venus.mbn";
};
&wifi {
status = "okay";
vdd-0.8-cx-mx-supply = <&vreg_l5a_0p8>;
vdd-1.3-rfa-supply = <&vreg_l17a_1p3>;
vdd-1.8-xo-supply = <&vreg_l7a_1p8>;
vdd-3.3-ch0-supply = <&vreg_l25a_3p3>;
vdd-3.3-ch1-supply = <&vreg_l23a_3p3>;
qcom,snoc-host-cap-8bit-quirk;
};

115
arch/arm64/boot/dts/qcom/sdm845.dtsi
View File

@@ -12,6 +12,7 @@
#include <dt-bindings/clock/qcom,lpass-sdm845.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,videocc-sdm845.h>
#include <dt-bindings/dma/qcom-gpi.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interconnect/qcom,osm-l3.h>
#include <dt-bindings/interconnect/qcom,sdm845.h>
@@ -79,22 +80,22 @@ reserved-memory {
#size-cells = <2>;
ranges;
hyp_mem: memory@85700000 {
hyp_mem: hyp-mem@85700000 {
reg = <0 0x85700000 0 0x600000>;
no-map;
};
xbl_mem: memory@85e00000 {
xbl_mem: xbl-mem@85e00000 {
reg = <0 0x85e00000 0 0x100000>;
no-map;
};
aop_mem: memory@85fc0000 {
aop_mem: aop-mem@85fc0000 {
reg = <0 0x85fc0000 0 0x20000>;
no-map;
};
aop_cmd_db_mem: memory@85fe0000 {
aop_cmd_db_mem: aop-cmd-db-mem@85fe0000 {
compatible = "qcom,cmd-db";
reg = <0x0 0x85fe0000 0 0x20000>;
no-map;
@@ -107,12 +108,12 @@ smem@86000000 {
hwlocks = <&tcsr_mutex 3>;
};
tz_mem: memory@86200000 {
tz_mem: tz@86200000 {
reg = <0 0x86200000 0 0x2d00000>;
no-map;
};
rmtfs_mem: memory@88f00000 {
rmtfs_mem: rmtfs@88f00000 {
compatible = "qcom,rmtfs-mem";
reg = <0 0x88f00000 0 0x200000>;
no-map;
@@ -121,67 +122,67 @@ rmtfs_mem: memory@88f00000 {
qcom,vmid = <15>;
};
qseecom_mem: memory@8ab00000 {
qseecom_mem: qseecom@8ab00000 {
reg = <0 0x8ab00000 0 0x1400000>;
no-map;
};
camera_mem: memory@8bf00000 {
camera_mem: camera-mem@8bf00000 {
reg = <0 0x8bf00000 0 0x500000>;
no-map;
};
ipa_fw_mem: memory@8c400000 {
ipa_fw_mem: ipa-fw@8c400000 {
reg = <0 0x8c400000 0 0x10000>;
no-map;
};
ipa_gsi_mem: memory@8c410000 {
ipa_gsi_mem: ipa-gsi@8c410000 {
reg = <0 0x8c410000 0 0x5000>;
no-map;
};
gpu_mem: memory@8c415000 {
gpu_mem: gpu@8c415000 {
reg = <0 0x8c415000 0 0x2000>;
no-map;
};
adsp_mem: memory@8c500000 {
adsp_mem: adsp@8c500000 {
reg = <0 0x8c500000 0 0x1a00000>;
no-map;
};
wlan_msa_mem: memory@8df00000 {
wlan_msa_mem: wlan-msa@8df00000 {
reg = <0 0x8df00000 0 0x100000>;
no-map;
};
mpss_region: memory@8e000000 {
mpss_region: mpss@8e000000 {
reg = <0 0x8e000000 0 0x7800000>;
no-map;
};
venus_mem: memory@95800000 {
venus_mem: venus@95800000 {
reg = <0 0x95800000 0 0x500000>;
no-map;
};
cdsp_mem: memory@95d00000 {
cdsp_mem: cdsp@95d00000 {
reg = <0 0x95d00000 0 0x800000>;
no-map;
};
mba_region: memory@96500000 {
mba_region: mba@96500000 {
reg = <0 0x96500000 0 0x200000>;
no-map;
};
slpi_mem: memory@96700000 {
slpi_mem: slpi@96700000 {
reg = <0 0x96700000 0 0x1400000>;
no-map;
};
spss_mem: memory@97b00000 {
spss_mem: spss@97b00000 {
reg = <0 0x97b00000 0 0x100000>;
no-map;
};
@@ -787,7 +788,7 @@ glink-edge {
apr {
compatible = "qcom,apr-v2";
qcom,glink-channels = "apr_audio_svc";
qcom,apr-domain = <APR_DOMAIN_ADSP>;
qcom,domain = <APR_DOMAIN_ADSP>;
#address-cells = <1>;
#size-cells = <0>;
qcom,intents = <512 20>;
@@ -1125,6 +1126,29 @@ opp-128000000 {
};
};
gpi_dma0: dma-controller@800000 {
#dma-cells = <3>;
compatible = "qcom,sdm845-gpi-dma";
reg = <0 0x00800000 0 0x60000>;
interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
dma-channels = <13>;
dma-channel-mask = <0xfa>;
iommus = <&apps_smmu 0x0016 0x0>;
status = "disabled";
};
qupv3_id_0: geniqup@8c0000 {
compatible = "qcom,geni-se-qup";
reg = <0 0x008c0000 0 0x6000>;
@@ -1171,6 +1195,9 @@ spi0: spi@880000 {
interconnects = <&aggre1_noc MASTER_QUP_1 0 &config_noc SLAVE_BLSP_1 0>,
<&gladiator_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_BLSP_1 0>;
interconnect-names = "qup-core", "qup-config";
dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
<&gpi_dma0 1 0 QCOM_GPI_SPI>;
dma-names = "tx", "rx";
status = "disabled";
};
@@ -1544,6 +1571,29 @@ uart7: serial@89c000 {
};
};
gpi_dma1: dma-controller@0xa00000 {
#dma-cells = <3>;
compatible = "qcom,sdm845-gpi-dma";
reg = <0 0x00a00000 0 0x60000>;
interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
dma-channels = <13>;
dma-channel-mask = <0xfa>;
iommus = <&apps_smmu 0x06d6 0x0>;
status = "disabled";
};
qupv3_id_1: geniqup@ac0000 {
compatible = "qcom,geni-se-qup";
reg = <0 0x00ac0000 0 0x6000>;
@@ -1967,7 +2017,7 @@ uart15: serial@a9c000 {
};
};
system-cache-controller@1100000 {
llcc: system-cache-controller@1100000 {
compatible = "qcom,sdm845-llcc";
reg = <0 0x01100000 0 0x200000>, <0 0x01300000 0 0x50000>;
reg-names = "llcc_base", "llcc_broadcast_base";
@@ -2587,6 +2637,13 @@ pinmux {
"gpio2", "gpio3";
function = "qup0";
};
config {
pins = "gpio0", "gpio1",
"gpio2", "gpio3";
drive-strength = <6>;
bias-disable;
};
};
qup_spi1_default: qup-spi1-default {
@@ -3613,10 +3670,10 @@ wcd9340: codec@1{
#clock-cells = <0>;
clock-frequency = <9600000>;
clock-output-names = "mclk";
qcom,micbias1-millivolt = <1800>;
qcom,micbias2-millivolt = <1800>;
qcom,micbias3-millivolt = <1800>;
qcom,micbias4-millivolt = <1800>;
qcom,micbias1-microvolt = <1800000>;
qcom,micbias2-microvolt = <1800000>;
qcom,micbias3-microvolt = <1800000>;
qcom,micbias4-microvolt = <1800000>;
#address-cells = <1>;
#size-cells = <1>;
@@ -4139,6 +4196,8 @@ clock_camcc: clock-controller@ad00000 {
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "bi_tcxo";
};
dsi_opp_table: dsi-opp-table {
@@ -4619,7 +4678,7 @@ aoss_reset: reset-controller@c2a0000 {
};
aoss_qmp: power-controller@c300000 {
compatible = "qcom,sdm845-aoss-qmp";
compatible = "qcom,sdm845-aoss-qmp", "qcom,aoss-qmp";
reg = <0 0x0c300000 0 0x100000>;
interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;
mboxes = <&apss_shared 0>;
@@ -5258,7 +5317,7 @@ cluster1_crit: cluster1_crit {
};
};
gpu-thermal-top {
gpu-top-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
@@ -5273,7 +5332,7 @@ gpu1_alert0: trip-point0 {
};
};
gpu-thermal-bottom {
gpu-bottom-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;

33
arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts
View File

@@ -56,19 +56,6 @@ mode {
};
};
panel {
compatible = "boe,nv133fhm-n61";
no-hpd;
ports {
port {
panel_in_edp: endpoint {
remote-endpoint = <&sn65dsi86_out>;
};
};
};
};
/* Reserved memory changes for IPA */
reserved-memory {
wlan_msa_mem: memory@8c400000 {
@@ -98,6 +85,12 @@ sn65dsi86_refclk: sn65dsi86-refclk {
clock-frequency = <19200000>;
};
backlight: backlight {
compatible = "pwm-backlight";
pwms = <&sn65dsi86 1000000>;
enable-gpios = <&tlmm 11 GPIO_ACTIVE_HIGH>;
};
};
&adsp_pas {
@@ -419,6 +412,7 @@ sn65dsi86: bridge@2c {
clock-names = "refclk";
no-hpd;
#pwm-cells = <1>;
ports {
#address-cells = <1>;
@@ -438,6 +432,19 @@ sn65dsi86_out: endpoint {
};
};
};
aux-bus {
panel: panel {
compatible = "boe,nv133fhm-n61";
backlight = <&backlight>;
port {
panel_in_edp: endpoint {
remote-endpoint = <&sn65dsi86_out>;
};
};
};
};
};
};

748
arch/arm64/boot/dts/qcom/sdm850-samsung-w737.dts Normal file
View File

@@ -0,0 +1,748 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Samsung Galaxy Book2
*
* Copyright (c) 2022, Xilin Wu <strongtz@yeah.net>
*/
/dts-v1/;
#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
#include <dt-bindings/input/gpio-keys.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
#include <dt-bindings/sound/qcom,q6afe.h>
#include <dt-bindings/sound/qcom,q6asm.h>
#include "sdm850.dtsi"
#include "pm8998.dtsi"
/*
* Update following upstream (sdm845.dtsi) reserved
* memory mappings for firmware loading to succeed
*/
/delete-node/ &qseecom_mem;
/delete-node/ &wlan_msa_mem;
/delete-node/ &slpi_mem;
/delete-node/ &ipa_fw_mem;
/delete-node/ &ipa_gsi_mem;
/delete-node/ &gpu_mem;
/delete-node/ &mpss_region;
/delete-node/ &adsp_mem;
/delete-node/ &cdsp_mem;
/delete-node/ &venus_mem;
/delete-node/ &mba_region;
/delete-node/ &spss_mem;
/ {
model = "Samsung Galaxy Book2";
compatible = "samsung,w737", "qcom,sdm845";
chassis-type = "convertible";
chosen {
#address-cells = <2>;
#size-cells = <2>;
ranges;
// Firmware initialized the display at 1280p instead of 1440p
framebuffer0: framebuffer@80400000 {
compatible = "simple-framebuffer";
reg = <0 0x80400000 0 (1920 * 1280 * 4)>;
width = <1920>;
height = <1280>;
stride = <(1920 * 4)>;
format = "a8r8g8b8";
};
};
aliases {
hsuart0 = &uart6;
};
/* Reserved memory changes */
reserved-memory {
/* Bootloader display framebuffer region */
cont_splash_mem: memory@80400000 {
reg = <0x0 0x80400000 0x0 0x960000>;
no-map;
};
qseecom_mem: memory@8b500000 {
reg = <0 0x8b500000 0 0xa00000>;
no-map;
};
wlan_msa_mem: memory@8c400000 {
reg = <0 0x8c400000 0 0x100000>;
no-map;
};
slpi_mem: memory@8c500000 {
reg = <0 0x8c500000 0 0x1200000>;
no-map;
};
ipa_fw_mem: memory@8d700000 {
reg = <0 0x8d700000 0 0x100000>;
no-map;
};
gpu_mem: memory@8d800000 {
reg = <0 0x8d800000 0 0x5000>;
no-map;
};
mpss_region: memory@8e000000 {
reg = <0 0x8e000000 0 0x8000000>;
no-map;
};
adsp_mem: memory@96000000 {
reg = <0 0x96000000 0 0x2000000>;
no-map;
};
cdsp_mem: memory@98000000 {
reg = <0 0x98000000 0 0x800000>;
no-map;
};
venus_mem: memory@98800000 {
reg = <0 0x98800000 0 0x500000>;
no-map;
};
mba_region: memory@98d00000 {
reg = <0 0x98d00000 0 0x200000>;
no-map;
};
spss_mem: memory@98f00000 {
reg = <0 0x98f00000 0 0x100000>;
no-map;
};
};
};
&adsp_pas {
firmware-name = "qcom/samsung/w737/qcadsp850.mbn";
status = "okay";
};
&apps_rsc {
pm8998-rpmh-regulators {
compatible = "qcom,pm8998-rpmh-regulators";
qcom,pmic-id = "a";
vdd-l2-l8-l17-supply = <&vreg_s3a_1p35>;
vdd-l7-l12-l14-l15-supply = <&vreg_s5a_2p04>;
vreg_s2a_1p125: smps2 {
};
vreg_s3a_1p35: smps3 {
regulator-min-microvolt = <1352000>;
regulator-max-microvolt = <1352000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_s4a_1p8: smps4 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_s5a_2p04: smps5 {
regulator-min-microvolt = <2040000>;
regulator-max-microvolt = <2040000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_s7a_1p025: smps7 {
};
vdd_qusb_hs0:
vdda_hp_pcie_core:
vdda_mipi_csi0_0p9:
vdda_mipi_csi1_0p9:
vdda_mipi_csi2_0p9:
vdda_mipi_dsi0_pll:
vdda_mipi_dsi1_pll:
vdda_qlink_lv:
vdda_qlink_lv_ck:
vdda_qrefs_0p875:
vdda_pcie_core:
vdda_pll_cc_ebi01:
vdda_pll_cc_ebi23:
vdda_sp_sensor:
vdda_ufs1_core:
vdda_ufs2_core:
vdda_usb1_ss_core:
vdda_usb2_ss_core:
vreg_l1a_0p875: ldo1 {
regulator-min-microvolt = <880000>;
regulator-max-microvolt = <880000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vddpx_10:
vreg_l2a_1p2: ldo2 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-always-on;
};
vreg_l3a_1p0: ldo3 {
};
vdd_wcss_cx:
vdd_wcss_mx:
vdda_wcss_pll:
vreg_l5a_0p8: ldo5 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <800000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vddpx_13:
vreg_l6a_1p8: ldo6 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l7a_1p8: ldo7 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l8a_1p2: ldo8 {
};
vreg_l9a_1p8: ldo9 {
};
vreg_l10a_1p8: ldo10 {
};
vreg_l11a_1p0: ldo11 {
};
vdd_qfprom:
vdd_qfprom_sp:
vdda_apc1_cs_1p8:
vdda_gfx_cs_1p8:
vdda_qrefs_1p8:
vdda_qusb_hs0_1p8:
vddpx_11:
vreg_l12a_1p8: ldo12 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vddpx_2:
vreg_l13a_2p95: ldo13 {
};
vreg_l14a_1p88: ldo14 {
regulator-min-microvolt = <1880000>;
regulator-max-microvolt = <1880000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-always-on;
};
vreg_l15a_1p8: ldo15 {
};
vreg_l16a_2p7: ldo16 {
};
vreg_l17a_1p3: ldo17 {
regulator-min-microvolt = <1304000>;
regulator-max-microvolt = <1304000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l18a_1p8: ldo18 {
};
vreg_l19a_3p0: ldo19 {
regulator-min-microvolt = <3100000>;
regulator-max-microvolt = <3108000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l20a_2p95: ldo20 {
regulator-min-microvolt = <2960000>;
regulator-max-microvolt = <2960000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l21a_2p95: ldo21 {
};
vreg_l22a_2p85: ldo22 {
};
vreg_l23a_3p3: ldo23 {
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3312000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vdda_qusb_hs0_3p1:
vreg_l24a_3p075: ldo24 {
regulator-min-microvolt = <3075000>;
regulator-max-microvolt = <3083000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l25a_3p3: ldo25 {
regulator-min-microvolt = <3104000>;
regulator-max-microvolt = <3112000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vdda_hp_pcie_1p2:
vdda_hv_ebi0:
vdda_hv_ebi1:
vdda_hv_ebi2:
vdda_hv_ebi3:
vdda_mipi_csi_1p25:
vdda_mipi_dsi0_1p2:
vdda_mipi_dsi1_1p2:
vdda_pcie_1p2:
vdda_ufs1_1p2:
vdda_ufs2_1p2:
vdda_usb1_ss_1p2:
vdda_usb2_ss_1p2:
vreg_l26a_1p2: ldo26 {
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1208000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l28a_3p0: ldo28 {
};
vreg_lvs1a_1p8: lvs1 {
};
vreg_lvs2a_1p8: lvs2 {
};
};
};
&cdsp_pas {
firmware-name = "qcom/samsung/w737/qccdsp850.mbn";
status = "okay";
};
&gcc {
protected-clocks = <GCC_QSPI_CORE_CLK>,
<GCC_QSPI_CORE_CLK_SRC>,
<GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
<GCC_LPASS_Q6_AXI_CLK>,
<GCC_LPASS_SWAY_CLK>;
};
&i2c10 {
status = "okay";
clock-frequency = <400000>;
/* SN65DSI86 @ 0x2c */
/* The panel requires dual DSI, which is not supported by the bridge driver */
};
&i2c11 {
status = "okay";
clock-frequency = <400000>;
/* HID-I2C Touchscreen @ 0x20 */
};
&i2c15 {
status = "okay";
clock-frequency = <400000>;
digitizer@9 {
compatible = "wacom,w9013", "hid-over-i2c";
reg = <0x9>;
pinctrl-names = "default";
pinctrl-0 = <&pen_irq_l>, <&pen_pdct_l>, <&pen_rst_l>;
post-power-on-delay-ms = <120>;
interrupt-parent = <&tlmm>;
interrupts = <119 IRQ_TYPE_LEVEL_LOW>;
hid-descr-addr = <0x1>;
};
};
&ipa {
status = "okay";
memory-region = <&ipa_fw_mem>;
firmware-name = "qcom/samsung/w737/ipa_fws.elf";
};
/* No idea why it causes an SError when enabled */
&llcc {
status = "disabled";
};
&mss_pil {
status = "okay";
firmware-name = "qcom/samsung/w737/qcdsp1v2850.mbn", "qcom/samsung/w737/qcdsp2850.mbn";
};
&qup_i2c10_default {
pinconf {
pins = "gpio55", "gpio56";
drive-strength = <2>;
bias-disable;
};
};
&qup_i2c11_default {
pinconf {
pins = "gpio31", "gpio32";
drive-strength = <2>;
bias-disable;
};
};
&qup_i2c12_default {
drive-strength = <2>;
bias-disable;
};
&qup_uart6_default {
pinmux {
pins = "gpio45", "gpio46", "gpio47", "gpio48";
function = "qup6";
};
cts {
pins = "gpio45";
bias-pull-down;
};
rts-tx {
pins = "gpio46", "gpio47";
drive-strength = <2>;
bias-disable;
};
rx {
pins = "gpio48";
bias-pull-up;
};
};
&qupv3_id_0 {
status = "okay";
};
&qupv3_id_1 {
status = "okay";
};
&q6asmdai {
dai@0 {
reg = <0>;
};
dai@1 {
reg = <1>;
};
dai@2 {
reg = <2>;
};
};
&sound {
compatible = "qcom,sdm845-sndcard";
model = "Samsung-W737";
audio-routing =
"RX_BIAS", "MCLK",
"AMIC2", "MIC BIAS2",
"SpkrLeft IN", "SPK1 OUT",
"SpkrRight IN", "SPK2 OUT",
"MM_DL1", "MultiMedia1 Playback",
"MM_DL3", "MultiMedia3 Playback",
"MultiMedia2 Capture", "MM_UL2";
mm1-dai-link {
link-name = "MultiMedia1";
cpu {
sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA1>;
};
};
mm2-dai-link {
link-name = "MultiMedia2";
cpu {
sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA2>;
};
};
mm3-dai-link {
link-name = "MultiMedia3";
cpu {
sound-dai = <&q6asmdai MSM_FRONTEND_DAI_MULTIMEDIA3>;
};
};
slim-dai-link {
link-name = "SLIM Playback";
cpu {
sound-dai = <&q6afedai SLIMBUS_0_RX>;
};
platform {
sound-dai = <&q6routing>;
};
codec {
sound-dai = <&left_spkr>, <&right_spkr>, <&swm 0>, <&wcd9340 0>;
};
};
slimcap-dai-link {
link-name = "SLIM Capture";
cpu {
sound-dai = <&q6afedai SLIMBUS_0_TX>;
};
platform {
sound-dai = <&q6routing>;
};
codec {
sound-dai = <&wcd9340 1>;
};
};
slim-wcd-dai-link {
link-name = "SLIM WCD Playback";
cpu {
sound-dai = <&q6afedai SLIMBUS_1_RX>;
};
platform {
sound-dai = <&q6routing>;
};
codec {
sound-dai = <&wcd9340 2>;
};
};
};
&tlmm {
gpio-reserved-ranges = <0 6>, <85 4>;
pen_irq_l: pen-irq-l {
pinmux {
pins = "gpio119";
function = "gpio";
};
pinconf {
pins = "gpio119";
bias-disable;
};
};
pen_pdct_l: pen-pdct-l {
pinmux {
pins = "gpio124";
function = "gpio";
};
pinconf {
pins = "gpio124";
bias-disable;
drive-strength = <2>;
output-high;
};
};
pen_rst_l: pen-rst-l {
pinmux {
pins = "gpio21";
function = "gpio";
};
pinconf {
pins = "gpio21";
bias-disable;
drive-strength = <2>;
/*
* The pen driver doesn't currently support
* driving this reset line. By specifying
* output-high here we're relying on the fact
* that this pin has a default pulldown at boot
* (which makes sure the pen was in reset if it
* was powered) and then we set it high here to
* take it out of reset. Better would be if the
* pen driver could control this and we could
* remove "output-high" here.
*/
output-high;
};
};
wcd_intr_default: wcd_intr_default {
pins = "gpio54";
function = "gpio";
input-enable;
bias-pull-down;
drive-strength = <2>;
};
};
&uart6 {
status = "okay";
bluetooth {
compatible = "qcom,wcn3990-bt";
vddio-supply = <&vreg_s4a_1p8>;
vddxo-supply = <&vreg_l7a_1p8>;
vddrf-supply = <&vreg_l17a_1p3>;
vddch0-supply = <&vreg_l25a_3p3>;
vddch1-supply = <&vreg_l23a_3p3>;
max-speed = <3200000>;
};
};
&ufs_mem_hc {
status = "okay";
reset-gpios = <&tlmm 150 GPIO_ACTIVE_LOW>;
vcc-supply = <&vreg_l20a_2p95>;
vcc-max-microamp = <600000>;
};
&ufs_mem_phy {
status = "okay";
vdda-phy-supply = <&vdda_ufs1_core>;
vdda-pll-supply = <&vdda_ufs1_1p2>;
};
&usb_1 {
status = "okay";
};
&usb_1_dwc3 {
dr_mode = "host";
};
&usb_1_hsphy {
status = "okay";
vdd-supply = <&vdda_usb1_ss_core>;
vdda-pll-supply = <&vdda_qusb_hs0_1p8>;
vdda-phy-dpdm-supply = <&vdda_qusb_hs0_3p1>;
qcom,imp-res-offset-value = <8>;
qcom,hstx-trim-value = <QUSB2_V2_HSTX_TRIM_21_6_MA>;
qcom,preemphasis-level = <QUSB2_V2_PREEMPHASIS_5_PERCENT>;
qcom,preemphasis-width = <QUSB2_V2_PREEMPHASIS_WIDTH_HALF_BIT>;
};
&usb_1_qmpphy {
status = "okay";
vdda-phy-supply = <&vdda_usb1_ss_1p2>;
vdda-pll-supply = <&vdda_usb1_ss_core>;
};
&usb_2 {
status = "okay";
};
&usb_2_dwc3 {
dr_mode = "host";
};
&usb_2_hsphy {
status = "okay";
vdd-supply = <&vdda_usb2_ss_core>;
vdda-pll-supply = <&vdda_qusb_hs0_1p8>;
vdda-phy-dpdm-supply = <&vdda_qusb_hs0_3p1>;
qcom,imp-res-offset-value = <8>;
qcom,hstx-trim-value = <QUSB2_V2_HSTX_TRIM_22_8_MA>;
};
&usb_2_qmpphy {
status = "okay";
vdda-phy-supply = <&vdda_usb2_ss_1p2>;
vdda-pll-supply = <&vdda_usb2_ss_core>;
};
&venus {
status = "okay";
firmware-name = "qcom/samsung/w737/qcvss850.mbn";
};
&wcd9340{
pinctrl-0 = <&wcd_intr_default>;
pinctrl-names = "default";
clock-names = "extclk";
clocks = <&rpmhcc RPMH_LN_BB_CLK2>;
reset-gpios = <&tlmm 64 0>;
vdd-buck-supply = <&vreg_s4a_1p8>;
vdd-buck-sido-supply = <&vreg_s4a_1p8>;
vdd-tx-supply = <&vreg_s4a_1p8>;
vdd-rx-supply = <&vreg_s4a_1p8>;
vdd-io-supply = <&vreg_s4a_1p8>;
qcom,mbhc-buttons-vthreshold-microvolt = <75000 150000 237000 500000 500000 500000 500000 500000>;
qcom,mbhc-headset-vthreshold-microvolt = <1700000>;
qcom,mbhc-headphone-vthreshold-microvolt = <50000>;
swm: swm@c85 {
left_spkr: wsa8810-left{
compatible = "sdw10217211000";
reg = <0 3>;
powerdown-gpios = <&wcdgpio 1 GPIO_ACTIVE_HIGH>;
#thermal-sensor-cells = <0>;
sound-name-prefix = "SpkrLeft";
#sound-dai-cells = <0>;
};
right_spkr: wsa8810-right{
compatible = "sdw10217211000";
powerdown-gpios = <&wcdgpio 2 GPIO_ACTIVE_HIGH>;
reg = <0 4>;
#thermal-sensor-cells = <0>;
sound-name-prefix = "SpkrRight";
#sound-dai-cells = <0>;
};
};
};
&wifi {
status = "okay";
vdd-0.8-cx-mx-supply = <&vreg_l5a_0p8>;
vdd-1.8-xo-supply = <&vreg_l7a_1p8>;
vdd-1.3-rfa-supply = <&vreg_l17a_1p3>;
vdd-3.3-ch0-supply = <&vreg_l25a_3p3>;
vdd-3.3-ch1-supply = <&vreg_l23a_3p3>;
qcom,snoc-host-cap-8bit-quirk;
};

4
arch/arm64/boot/dts/qcom/sm6125.dtsi
View File

@@ -449,7 +449,7 @@ sdhc_1: sdhci@4744000 {
<&xo_board>;
clock-names = "iface", "core", "xo";
power-domains = <&rpmpd 0>;
power-domains = <&rpmpd SM6125_VDDCX>;
bus-width = <8>;
non-removable;
@@ -474,7 +474,7 @@ sdhc_2: sdhci@4784000 {
pinctrl-1 = <&sdc2_state_off>;
pinctrl-names = "default", "sleep";
power-domains = <&rpmpd 0>;
power-domains = <&rpmpd SM6125_VDDCX>;
bus-width = <4>;
status = "disabled";

9
arch/arm64/boot/dts/qcom/sm7225-fairphone-fp4.dts
View File

@@ -10,6 +10,7 @@
#include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
#include "sm7225.dtsi"
#include "pm6150l.dtsi"
#include "pm6350.dtsi"
/ {
@@ -300,6 +301,14 @@ &mpss {
firmware-name = "qcom/sm7225/fairphone4/modem.mdt";
};
&pm6150l_wled {
status = "okay";
qcom,switching-freq = <800>;
qcom,current-limit-microamp = <20000>;
qcom,num-strings = <2>;
};
&pm6350_gpios {
gpio_keys_pin: gpio-keys-pin {
pins = "gpio2";

20
arch/arm64/boot/dts/qcom/sm8150-microsoft-surface-duo.dts
View File

@@ -430,18 +430,8 @@ &i2c19 {
/* MAX34417 @ 0x1e */
};
&pon {
pwrkey {
status = "okay";
};
resin {
compatible = "qcom,pm8941-resin";
interrupts = <0x0 0x8 0x1 IRQ_TYPE_EDGE_BOTH>;
debounce = <15625>;
bias-pull-up;
linux,code = <KEY_VOLUMEDOWN>;
};
&pon_pwrkey {
status = "okay";
};
&qupv3_id_0 {
@@ -476,6 +466,12 @@ &remoteproc_slpi {
firmware-name = "qcom/sm8150/microsoft/slpi.mdt";
};
&pon_resin {
status = "okay";
linux,code = <KEY_VOLUMEDOWN>;
};
&tlmm {
gpio-reserved-ranges = <126 4>;

154
arch/arm64/boot/dts/qcom/sm8150.dtsi
View File

@@ -932,6 +932,9 @@ i2c0: i2c@880000 {
reg = <0 0x00880000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
<&gpi_dma0 1 0 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&qup_i2c0_default>;
interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
@@ -946,6 +949,9 @@ spi0: spi@880000 {
reg-names = "se";
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
<&gpi_dma0 1 0 QCOM_GPI_SPI>;
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&qup_spi0_default>;
interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
@@ -960,6 +966,9 @@ i2c1: i2c@884000 {
reg = <0 0x00884000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
<&gpi_dma0 1 1 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&qup_i2c1_default>;
interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
@@ -974,6 +983,9 @@ spi1: spi@884000 {
reg-names = "se";
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
<&gpi_dma0 1 1 QCOM_GPI_SPI>;
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&qup_spi1_default>;
interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
@@ -988,6 +1000,9 @@ i2c2: i2c@888000 {
reg = <0 0x00888000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
<&gpi_dma0 1 2 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&qup_i2c2_default>;
interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
@@ -1002,6 +1017,9 @@ spi2: spi@888000 {
reg-names = "se";
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
<&gpi_dma0 1 2 QCOM_GPI_SPI>;
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&qup_spi2_default>;
interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
@@ -1016,6 +1034,9 @@ i2c3: i2c@88c000 {
reg = <0 0x0088c000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
<&gpi_dma0 1 3 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&qup_i2c3_default>;
interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
@@ -1030,6 +1051,9 @@ spi3: spi@88c000 {
reg-names = "se";
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
<&gpi_dma0 1 3 QCOM_GPI_SPI>;
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&qup_spi3_default>;
interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
@@ -1044,6 +1068,9 @@ i2c4: i2c@890000 {
reg = <0 0x00890000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
<&gpi_dma0 1 4 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&qup_i2c4_default>;
interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
@@ -1058,6 +1085,9 @@ spi4: spi@890000 {
reg-names = "se";
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
<&gpi_dma0 1 4 QCOM_GPI_SPI>;
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&qup_spi4_default>;
interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
@@ -1072,6 +1102,9 @@ i2c5: i2c@894000 {
reg = <0 0x00894000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
<&gpi_dma0 1 5 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&qup_i2c5_default>;
interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
@@ -1086,6 +1119,9 @@ spi5: spi@894000 {
reg-names = "se";
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
<&gpi_dma0 1 5 QCOM_GPI_SPI>;
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&qup_spi5_default>;
interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
@@ -1100,6 +1136,9 @@ i2c6: i2c@898000 {
reg = <0 0x00898000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
<&gpi_dma0 1 6 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&qup_i2c6_default>;
interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
@@ -1114,6 +1153,9 @@ spi6: spi@898000 {
reg-names = "se";
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
<&gpi_dma0 1 6 QCOM_GPI_SPI>;
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&qup_spi6_default>;
interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
@@ -1128,6 +1170,9 @@ i2c7: i2c@89c000 {
reg = <0 0x0089c000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>,
<&gpi_dma0 1 7 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&qup_i2c7_default>;
interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
@@ -1142,6 +1187,9 @@ spi7: spi@89c000 {
reg-names = "se";
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>,
<&gpi_dma0 1 7 QCOM_GPI_SPI>;
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&qup_spi7_default>;
interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
@@ -1192,6 +1240,9 @@ i2c8: i2c@a80000 {
reg = <0 0x00a80000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
<&gpi_dma1 1 0 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&qup_i2c8_default>;
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
@@ -1206,6 +1257,9 @@ spi8: spi@a80000 {
reg-names = "se";
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
<&gpi_dma1 1 0 QCOM_GPI_SPI>;
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&qup_spi8_default>;
interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
@@ -1220,6 +1274,9 @@ i2c9: i2c@a84000 {
reg = <0 0x00a84000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
<&gpi_dma1 1 1 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&qup_i2c9_default>;
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
@@ -1234,6 +1291,9 @@ spi9: spi@a84000 {
reg-names = "se";
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
<&gpi_dma1 1 1 QCOM_GPI_SPI>;
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&qup_spi9_default>;
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
@@ -1248,6 +1308,9 @@ i2c10: i2c@a88000 {
reg = <0 0x00a88000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
<&gpi_dma1 1 2 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&qup_i2c10_default>;
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
@@ -1262,6 +1325,9 @@ spi10: spi@a88000 {
reg-names = "se";
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
<&gpi_dma1 1 2 QCOM_GPI_SPI>;
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&qup_spi10_default>;
interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
@@ -1276,6 +1342,9 @@ i2c11: i2c@a8c000 {
reg = <0 0x00a8c000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
<&gpi_dma1 1 3 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&qup_i2c11_default>;
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
@@ -1290,6 +1359,9 @@ spi11: spi@a8c000 {
reg-names = "se";
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
<&gpi_dma1 1 3 QCOM_GPI_SPI>;
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&qup_spi11_default>;
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
@@ -1313,6 +1385,9 @@ i2c12: i2c@a90000 {
reg = <0 0x00a90000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
<&gpi_dma1 1 4 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&qup_i2c12_default>;
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
@@ -1327,6 +1402,9 @@ spi12: spi@a90000 {
reg-names = "se";
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
<&gpi_dma1 1 4 QCOM_GPI_SPI>;
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&qup_spi12_default>;
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
@@ -1341,6 +1419,9 @@ i2c16: i2c@94000 {
reg = <0 0x0094000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
<&gpi_dma2 1 5 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&qup_i2c16_default>;
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
@@ -1355,6 +1436,9 @@ spi16: spi@a94000 {
reg-names = "se";
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
<&gpi_dma2 1 5 QCOM_GPI_SPI>;
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&qup_spi16_default>;
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
@@ -1406,6 +1490,9 @@ i2c17: i2c@c80000 {
reg = <0 0x00c80000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
<&gpi_dma2 1 0 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&qup_i2c17_default>;
interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
@@ -1420,6 +1507,9 @@ spi17: spi@c80000 {
reg-names = "se";
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
<&gpi_dma2 1 0 QCOM_GPI_SPI>;
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&qup_spi17_default>;
interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
@@ -1434,6 +1524,9 @@ i2c18: i2c@c84000 {
reg = <0 0x00c84000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
<&gpi_dma2 1 1 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&qup_i2c18_default>;
interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
@@ -1448,6 +1541,9 @@ spi18: spi@c84000 {
reg-names = "se";
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
<&gpi_dma2 1 1 QCOM_GPI_SPI>;
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&qup_spi18_default>;
interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
@@ -1462,6 +1558,9 @@ i2c19: i2c@c88000 {
reg = <0 0x00c88000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
<&gpi_dma2 1 2 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&qup_i2c19_default>;
interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
@@ -1476,6 +1575,9 @@ spi19: spi@c88000 {
reg-names = "se";
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
<&gpi_dma2 1 2 QCOM_GPI_SPI>;
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&qup_spi19_default>;
interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
@@ -1490,6 +1592,9 @@ i2c13: i2c@c8c000 {
reg = <0 0x00c8c000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
<&gpi_dma2 1 3 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&qup_i2c13_default>;
interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
@@ -1504,6 +1609,9 @@ spi13: spi@c8c000 {
reg-names = "se";
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>,
<&gpi_dma2 1 3 QCOM_GPI_SPI>;
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&qup_spi13_default>;
interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
@@ -1518,6 +1626,9 @@ i2c14: i2c@c90000 {
reg = <0 0x00c90000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
<&gpi_dma2 1 4 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&qup_i2c14_default>;
interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
@@ -1532,6 +1643,9 @@ spi14: spi@c90000 {
reg-names = "se";
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>,
<&gpi_dma2 1 4 QCOM_GPI_SPI>;
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&qup_spi14_default>;
interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
@@ -1546,6 +1660,9 @@ i2c15: i2c@c94000 {
reg = <0 0x00c94000 0 0x4000>;
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
<&gpi_dma2 1 5 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&qup_i2c15_default>;
interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
@@ -1560,6 +1677,9 @@ spi15: spi@c94000 {
reg-names = "se";
clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
<&gpi_dma2 1 5 QCOM_GPI_SPI>;
dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&qup_spi15_default>;
interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
@@ -3556,9 +3676,9 @@ apps_rsc: rsc@18200000 {
qcom,tcs-offset = <0xd00>;
qcom,drv-id = <2>;
qcom,tcs-config = <ACTIVE_TCS 2>,
<SLEEP_TCS 1>,
<WAKE_TCS 1>,
<CONTROL_TCS 0>;
<SLEEP_TCS 3>,
<WAKE_TCS 3>,
<CONTROL_TCS 1>;
rpmhcc: clock-controller {
compatible = "qcom,sm8150-rpmh-clk";
@@ -3649,6 +3769,30 @@ cpufreq_hw: cpufreq@18323000 {
#freq-domain-cells = <1>;
};
lmh_cluster1: lmh@18350800 {
compatible = "qcom,sm8150-lmh";
reg = <0 0x18350800 0 0x400>;
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
cpus = <&CPU4>;
qcom,lmh-temp-arm-millicelsius = <60000>;
qcom,lmh-temp-low-millicelsius = <84500>;
qcom,lmh-temp-high-millicelsius = <85000>;
interrupt-controller;
#interrupt-cells = <1>;
};
lmh_cluster0: lmh@18358800 {
compatible = "qcom,sm8150-lmh";
reg = <0 0x18358800 0 0x400>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
cpus = <&CPU0>;
qcom,lmh-temp-arm-millicelsius = <60000>;
qcom,lmh-temp-low-millicelsius = <84500>;
qcom,lmh-temp-high-millicelsius = <85000>;
interrupt-controller;
#interrupt-cells = <1>;
};
wifi: wifi@18800000 {
compatible = "qcom,wcn3990-wifi";
reg = <0 0x18800000 0 0x800000>;
@@ -4265,7 +4409,7 @@ cluster1_crit: cluster1_crit {
};
};
gpu-thermal-top {
gpu-top-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
@@ -4445,7 +4589,7 @@ modem_scl_alert0: trip-point0 {
};
};
gpu-thermal-bottom {
gpu-bottom-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;

132
arch/arm64/boot/dts/qcom/sm8250.dtsi
View File

@@ -98,6 +98,8 @@ CPU0: cpu@0 {
capacity-dmips-mhz = <448>;
dynamic-power-coefficient = <205>;
next-level-cache = <&L2_0>;
power-domains = <&CPU_PD0>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 0>;
operating-points-v2 = <&cpu0_opp_table>;
interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
@@ -120,6 +122,8 @@ CPU1: cpu@100 {
capacity-dmips-mhz = <448>;
dynamic-power-coefficient = <205>;
next-level-cache = <&L2_100>;
power-domains = <&CPU_PD1>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 0>;
operating-points-v2 = <&cpu0_opp_table>;
interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
@@ -139,6 +143,8 @@ CPU2: cpu@200 {
capacity-dmips-mhz = <448>;
dynamic-power-coefficient = <205>;
next-level-cache = <&L2_200>;
power-domains = <&CPU_PD2>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 0>;
operating-points-v2 = <&cpu0_opp_table>;
interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
@@ -158,6 +164,8 @@ CPU3: cpu@300 {
capacity-dmips-mhz = <448>;
dynamic-power-coefficient = <205>;
next-level-cache = <&L2_300>;
power-domains = <&CPU_PD3>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 0>;
operating-points-v2 = <&cpu0_opp_table>;
interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
@@ -177,6 +185,8 @@ CPU4: cpu@400 {
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <379>;
next-level-cache = <&L2_400>;
power-domains = <&CPU_PD4>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 1>;
operating-points-v2 = <&cpu4_opp_table>;
interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
@@ -196,6 +206,8 @@ CPU5: cpu@500 {
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <379>;
next-level-cache = <&L2_500>;
power-domains = <&CPU_PD5>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 1>;
operating-points-v2 = <&cpu4_opp_table>;
interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
@@ -216,6 +228,8 @@ CPU6: cpu@600 {
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <379>;
next-level-cache = <&L2_600>;
power-domains = <&CPU_PD6>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 1>;
operating-points-v2 = <&cpu4_opp_table>;
interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
@@ -235,6 +249,8 @@ CPU7: cpu@700 {
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <444>;
next-level-cache = <&L2_700>;
power-domains = <&CPU_PD7>;
power-domain-names = "psci";
qcom,freq-domain = <&cpufreq_hw 2>;
operating-points-v2 = <&cpu7_opp_table>;
interconnects = <&gem_noc MASTER_AMPSS_M0 &mc_virt SLAVE_EBI_CH0>,
@@ -281,6 +297,42 @@ core7 {
};
};
};
idle-states {
entry-method = "psci";
LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
compatible = "arm,idle-state";
idle-state-name = "silver-rail-power-collapse";
arm,psci-suspend-param = <0x40000004>;
entry-latency-us = <360>;
exit-latency-us = <531>;
min-residency-us = <3934>;
local-timer-stop;
};
BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
compatible = "arm,idle-state";
idle-state-name = "gold-rail-power-collapse";
arm,psci-suspend-param = <0x40000004>;
entry-latency-us = <702>;
exit-latency-us = <1061>;
min-residency-us = <4488>;
local-timer-stop;
};
};
domain-idle-states {
CLUSTER_SLEEP_0: cluster-sleep-0 {
compatible = "domain-idle-state";
idle-state-name = "cluster-llcc-off";
arm,psci-suspend-param = <0x4100c244>;
entry-latency-us = <3264>;
exit-latency-us = <6562>;
min-residency-us = <9987>;
local-timer-stop;
};
};
};
cpu0_opp_table: cpu0_opp_table {
@@ -594,6 +646,59 @@ pmu {
psci {
compatible = "arm,psci-1.0";
method = "smc";
CPU_PD0: cpu0 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
};
CPU_PD1: cpu1 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
};
CPU_PD2: cpu2 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
};
CPU_PD3: cpu3 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&LITTLE_CPU_SLEEP_0>;
};
CPU_PD4: cpu4 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&BIG_CPU_SLEEP_0>;
};
CPU_PD5: cpu5 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&BIG_CPU_SLEEP_0>;
};
CPU_PD6: cpu6 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&BIG_CPU_SLEEP_0>;
};
CPU_PD7: cpu7 {
#power-domain-cells = <0>;
power-domains = <&CLUSTER_PD>;
domain-idle-states = <&BIG_CPU_SLEEP_0>;
};
CLUSTER_PD: cpu-cluster0 {
#power-domain-cells = <0>;
domain-idle-states = <&CLUSTER_SLEEP_0>;
};
};
reserved-memory {
@@ -1740,8 +1845,8 @@ pcie0: pci@1c00000 {
phys = <&pcie0_lane>;
phy-names = "pciephy";
perst-gpio = <&tlmm 79 GPIO_ACTIVE_LOW>;
enable-gpio = <&tlmm 81 GPIO_ACTIVE_HIGH>;
perst-gpios = <&tlmm 79 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 81 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pcie0_default_state>;
@@ -1801,7 +1906,7 @@ pcie1: pci@1c08000 {
ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>,
<0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
interrupts = <GIC_SPI 306 IRQ_TYPE_EDGE_RISING>;
interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
@@ -1844,8 +1949,8 @@ pcie1: pci@1c08000 {
phys = <&pcie1_lane>;
phy-names = "pciephy";
perst-gpio = <&tlmm 82 GPIO_ACTIVE_LOW>;
enable-gpio = <&tlmm 84 GPIO_ACTIVE_HIGH>;
perst-gpios = <&tlmm 82 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 84 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pcie1_default_state>;
@@ -1907,7 +2012,7 @@ pcie2: pci@1c10000 {
ranges = <0x01000000 0x0 0x64200000 0x0 0x64200000 0x0 0x100000>,
<0x02000000 0x0 0x64300000 0x0 0x64300000 0x0 0x3d00000>;
interrupts = <GIC_SPI 236 IRQ_TYPE_EDGE_RISING>;
interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
@@ -1950,8 +2055,8 @@ pcie2: pci@1c10000 {
phys = <&pcie2_lane>;
phy-names = "pciephy";
perst-gpio = <&tlmm 85 GPIO_ACTIVE_LOW>;
enable-gpio = <&tlmm 87 GPIO_ACTIVE_HIGH>;
perst-gpios = <&tlmm 85 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 87 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pcie2_default_state>;
@@ -4320,7 +4425,7 @@ IPCC_MPROC_SIGNAL_GLINK_QMP
apr {
compatible = "qcom,apr-v2";
qcom,glink-channels = "apr_audio_svc";
qcom,apr-domain = <APR_DOMAIN_ADSP>;
qcom,domain = <APR_DOMAIN_ADSP>;
#address-cells = <1>;
#size-cells = <0>;
@@ -4571,7 +4676,10 @@ cpufreq_hw: cpufreq@18591000 {
clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
clock-names = "xo", "alternate";
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2";
#freq-domain-cells = <1>;
};
};
@@ -5172,7 +5280,7 @@ cluster1_crit: cluster1_crit {
};
};
gpu-thermal-top {
gpu-top-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
@@ -5307,7 +5415,7 @@ npu_alert0: trip-point0 {
};
};
gpu-thermal-bottom {
gpu-bottom-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;

20
arch/arm64/boot/dts/qcom/sm8350.dtsi
View File

@@ -1425,6 +1425,8 @@ ipa: ipa@1e40000 {
interconnect-names = "memory",
"config";
qcom,qmp = <&aoss_qmp>;
qcom,smem-states = <&ipa_smp2p_out 0>,
<&ipa_smp2p_out 1>;
qcom,smem-state-names = "ipa-clock-enabled-valid",
@@ -1802,7 +1804,7 @@ apps_rsc: rsc@18200000 {
qcom,tcs-offset = <0xd00>;
qcom,drv-id = <2>;
qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>,
<WAKE_TCS 3>, <CONTROL_TCS 1>;
<WAKE_TCS 3>, <CONTROL_TCS 0>;
rpmhcc: clock-controller {
compatible = "qcom,sm8350-rpmh-clk";
@@ -2991,7 +2993,7 @@ aoss1_alert0: trip-point0 {
};
};
gpu-thermal-top {
gpu-top-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
@@ -3006,7 +3008,7 @@ gpu1_alert0: trip-point0 {
};
};
gpu-thermal-bottom {
gpu-bottom-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
@@ -3096,7 +3098,7 @@ mem_alert0: trip-point0 {
};
};
modem1-thermal-top {
modem1-top-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
@@ -3111,7 +3113,7 @@ modem1_alert0: trip-point0 {
};
};
modem2-thermal-top {
modem2-top-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
@@ -3126,7 +3128,7 @@ modem2_alert0: trip-point0 {
};
};
modem3-thermal-top {
modem3-top-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
@@ -3141,7 +3143,7 @@ modem3_alert0: trip-point0 {
};
};
modem4-thermal-top {
modem4-top-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
@@ -3156,7 +3158,7 @@ modem4_alert0: trip-point0 {
};
};
camera-thermal-top {
camera-top-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
@@ -3171,7 +3173,7 @@ camera1_alert0: trip-point0 {
};
};
cam-thermal-bottom {
cam-bottom-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;

405
arch/arm64/boot/dts/qcom/sm8450-hdk.dts Normal file
View File

@@ -0,0 +1,405 @@
// SPDX-License-Identifier: BSD-3-Clause
/*
* Copyright (c) 2022, Linaro Limited
*/
/dts-v1/;
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
#include "sm8450.dtsi"
/ {
model = "Qualcomm Technologies, Inc. SM8450 HDK";
compatible = "qcom,sm8450-hdk", "qcom,sm8450";
aliases {
serial0 = &uart7;
};
chosen {
stdout-path = "serial0:115200n8";
};
vph_pwr: vph-pwr-regulator {
compatible = "regulator-fixed";
regulator-name = "vph_pwr";
regulator-min-microvolt = <3700000>;
regulator-max-microvolt = <3700000>;
regulator-always-on;
regulator-boot-on;
};
};
&apps_rsc {
pm8350-rpmh-regulators {
compatible = "qcom,pm8350-rpmh-regulators";
qcom,pmic-id = "b";
vdd-s1-supply = <&vph_pwr>;
vdd-s2-supply = <&vph_pwr>;
vdd-s3-supply = <&vph_pwr>;
vdd-s4-supply = <&vph_pwr>;
vdd-s5-supply = <&vph_pwr>;
vdd-s6-supply = <&vph_pwr>;
vdd-s7-supply = <&vph_pwr>;
vdd-s8-supply = <&vph_pwr>;
vdd-s9-supply = <&vph_pwr>;
vdd-s10-supply = <&vph_pwr>;
vdd-s11-supply = <&vph_pwr>;
vdd-s12-supply = <&vph_pwr>;
vdd-l1-l4-supply = <&vreg_s11b_0p95>;
vdd-l2-l7-supply = <&vreg_bob>;
vdd-l3-l5-supply = <&vreg_bob>;
vdd-l6-l9-l10-supply = <&vreg_s12b_1p25>;
vdd-l8-supply = <&vreg_s2h_0p95>;
vreg_s10b_1p8: smps10 {
regulator-name = "vreg_s10b_1p8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
vreg_s11b_0p95: smps11 {
regulator-name = "vreg_s11b_0p95";
regulator-min-microvolt = <966000>;
regulator-max-microvolt = <1104000>;
};
vreg_s12b_1p25: smps12 {
regulator-name = "vreg_s12b_1p25";
regulator-min-microvolt = <1350000>;
regulator-max-microvolt = <1400000>;
};
vreg_l1b_0p91: ldo1 {
regulator-name = "vreg_l1b_0p91";
regulator-min-microvolt = <912000>;
regulator-max-microvolt = <920000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l2b_3p07: ldo2 {
regulator-name = "vreg_l2b_3p07";
regulator-min-microvolt = <3072000>;
regulator-max-microvolt = <3072000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l3b_0p9: ldo3 {
regulator-name = "vreg_l3b_0p9";
regulator-min-microvolt = <904000>;
regulator-max-microvolt = <904000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l5b_0p88: ldo5 {
regulator-name = "vreg_l5b_0p88";
regulator-min-microvolt = <880000>;
regulator-max-microvolt = <888000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l6b_1p2: ldo6 {
regulator-name = "vreg_l6b_1p2";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l7b_2p5: ldo7 {
regulator-name = "vreg_l7b_2p5";
regulator-min-microvolt = <2504000>;
regulator-max-microvolt = <2504000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l9b_1p2: ldo9 {
regulator-name = "vreg_l9b_1p2";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
pm8350c-rpmh-regulators {
compatible = "qcom,pm8350c-rpmh-regulators";
qcom,pmic-id = "c";
vdd-s1-supply = <&vph_pwr>;
vdd-s2-supply = <&vph_pwr>;
vdd-s3-supply = <&vph_pwr>;
vdd-s4-supply = <&vph_pwr>;
vdd-s5-supply = <&vph_pwr>;
vdd-s6-supply = <&vph_pwr>;
vdd-s7-supply = <&vph_pwr>;
vdd-s8-supply = <&vph_pwr>;
vdd-s9-supply = <&vph_pwr>;
vdd-s10-supply = <&vph_pwr>;
vdd-l1-l12-supply = <&vreg_bob>;
vdd-l2-l8-supply = <&vreg_bob>;
vdd-l3-l4-l5-l7-l13-supply = <&vreg_bob>;
vdd-l6-l9-l11-supply = <&vreg_bob>;
vdd-l10-supply = <&vreg_s12b_1p25>;
vdd-bob-supply = <&vph_pwr>;
vreg_s1c_1p86: smps1 {
regulator-name = "vreg_s1c_1p86";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <2024000>;
};
vreg_s10c_1p05: smps10 {
regulator-name = "vreg_s10c_1p05";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1100000>;
};
vreg_bob: bob {
regulator-name = "vreg_bob";
regulator-min-microvolt = <3008000>;
regulator-max-microvolt = <3960000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
};
vreg_l1c_1p8: ldo1 {
regulator-name = "vreg_l1c_1p8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l3c_3p0: ldo3 {
regulator-name = "vreg_l3c_3p0";
regulator-min-microvolt = <3296000>;
regulator-max-microvolt = <3304000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l4c_1p8: ldo4 {
regulator-name = "vreg_l4c_1p8";
regulator-min-microvolt = <1704000>;
regulator-max-microvolt = <3000000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l5c_1p8: ldo5 {
regulator-name = "vreg_l5c_1p8";
regulator-min-microvolt = <1704000>;
regulator-max-microvolt = <3000000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l6c_1p8: ldo6 {
regulator-name = "vreg_l6c_1p8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3008000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l7c_3p0: ldo7 {
regulator-name = "vreg_l7c_3p0";
regulator-min-microvolt = <3008000>;
regulator-max-microvolt = <3008000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l8c_1p8: ldo8 {
regulator-name = "vreg_l8c_1p8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l9c_2p96: ldo9 {
regulator-name = "vreg_l9c_2p96";
regulator-min-microvolt = <2960000>;
regulator-max-microvolt = <3008000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l12c_1p8: ldo12 {
regulator-name = "vreg_l12c_1p8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1968000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l13c_3p0: ldo13 {
regulator-name = "vreg_l13c_3p0";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
pm8450-rpmh-regulators {
compatible = "qcom,pm8450-rpmh-regulators";
qcom,pmic-id = "h";
vdd-s1-supply = <&vph_pwr>;
vdd-s2-supply = <&vph_pwr>;
vdd-s3-supply = <&vph_pwr>;
vdd-s4-supply = <&vph_pwr>;
vdd-s5-supply = <&vph_pwr>;
vdd-s6-supply = <&vph_pwr>;
vdd-l2-supply = <&vreg_bob>;
vdd-l3-supply = <&vreg_bob>;
vdd-l4-supply = <&vreg_bob>;
vreg_s2h_0p95: smps2 {
regulator-name = "vreg_s2h_0p95";
regulator-min-microvolt = <848000>;
regulator-max-microvolt = <1104000>;
};
vreg_s3h_0p5: smps3 {
regulator-name = "vreg_s3h_0p5";
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <500000>;
};
vreg_l2h_0p91: ldo2 {
regulator-name = "vreg_l2h_0p91";
regulator-min-microvolt = <880000>;
regulator-max-microvolt = <912000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
vreg_l3h_0p91: ldo3 {
regulator-name = "vreg_l3h_0p91";
regulator-min-microvolt = <912000>;
regulator-max-microvolt = <912000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
};
pmr735a-rpmh-regulators {
compatible = "qcom,pmr735a-rpmh-regulators";
qcom,pmic-id = "e";
vdd-s1-supply = <&vph_pwr>;
vdd-s2-supply = <&vph_pwr>;
vdd-s3-supply = <&vph_pwr>;
vdd-l1-l2-supply = <&vreg_s2e_0p85>;
vdd-l3-supply = <&vreg_s1e_1p25>;
vdd-l4-supply = <&vreg_s1c_1p86>;
vdd-l5-l6-supply = <&vreg_s1c_1p86>;
vdd-l7-bob-supply = <&vreg_bob>;
vreg_s1e_1p25: smps1 {
regulator-name = "vreg_s1e_1p25";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1296000>;
};
vreg_s2e_0p85: smps2 {
regulator-name = "vreg_s2e_0p85";
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1040000>;
};
vreg_l1e_0p8: ldo1 {
regulator-name = "vreg_l1e_0p8";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <800000>;
};
vreg_l2e_0p8: ldo2 {
regulator-name = "vreg_l2e_0p8";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <800000>;
};
vreg_l3e_1p2: ldo3 {
regulator-name = "vreg_l3e_1p2";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
};
vreg_l4e_1p7: ldo4 {
regulator-name = "vreg_l4e_1p7";
regulator-min-microvolt = <1776000>;
regulator-max-microvolt = <1776000>;
};
vreg_l5e_0p88: ldo5 {
regulator-name = "vreg_l5e_0p88";
regulator-min-microvolt = <880000>;
regulator-max-microvolt = <880000>;
};
vreg_l6e_1p2: ldo6 {
regulator-name = "vreg_l6e_1p2";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
};
vreg_l7e_2p8: ldo7 {
regulator-name = "vreg_l7e_2p8";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
};
};
};
&qupv3_id_0 {
status = "okay";
};
&tlmm {
gpio-reserved-ranges = <28 4>, <36 4>;
};
&uart7 {
status = "okay";
};
&ufs_mem_hc {
status = "okay";
reset-gpios = <&tlmm 210 GPIO_ACTIVE_LOW>;
vcc-supply = <&vreg_l7b_2p5>;
vcc-max-microamp = <1100000>;
vccq-supply = <&vreg_l9b_1p2>;
vccq-max-microamp = <1200000>;
};
&ufs_mem_phy {
status = "okay";
vdda-phy-supply = <&vreg_l5b_0p88>;
vdda-pll-supply = <&vreg_l6b_1p2>;
vdda-max-microamp = <173000>;
vdda-pll-max-microamp = <24900>;
};
&usb_1 {
status = "okay";
};
&usb_1_dwc3 {
dr_mode = "peripheral";
};
&usb_1_hsphy {
status = "okay";
vdda-pll-supply = <&vreg_l5b_0p88>;
vdda18-supply = <&vreg_l1c_1p8>;
vdda33-supply = <&vreg_l2b_3p07>;
};
&usb_1_qmpphy {
status = "okay";
vdda-phy-supply = <&vreg_l6b_1p2>;
vdda-pll-supply = <&vreg_l1b_0p91>;
};

20
arch/arm64/boot/dts/qcom/sm8450-qrd.dts
View File

@@ -346,6 +346,26 @@ &qupv3_id_0 {
status = "okay";
};
&remoteproc_adsp {
status = "okay";
firmware-name = "qcom/sm8450/adsp.mbn";
};
&remoteproc_cdsp {
status = "okay";
firmware-name = "qcom/sm8450/cdsp.mbn";
};
&remoteproc_mpss {
status = "okay";
firmware-name = "qcom/sm8450/modem.mbn";
};
&remoteproc_slpi {
status = "okay";
firmware-name = "qcom/sm8450/slpi.mbn";
};
&tlmm {
gpio-reserved-ranges = <28 4>, <36 4>;
};

417
arch/arm64/boot/dts/qcom/sm8450.dtsi
View File

@@ -7,7 +7,9 @@
#include <dt-bindings/clock/qcom,gcc-sm8450.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/mailbox/qcom-ipcc.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/interconnect/qcom,sm8450.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
/ {
@@ -203,9 +205,9 @@ LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
compatible = "arm,idle-state";
idle-state-name = "silver-rail-power-collapse";
arm,psci-suspend-param = <0x40000004>;
entry-latency-us = <274>;
exit-latency-us = <480>;
min-residency-us = <3934>;
entry-latency-us = <800>;
exit-latency-us = <750>;
min-residency-us = <4090>;
local-timer-stop;
};
@@ -213,9 +215,9 @@ BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
compatible = "arm,idle-state";
idle-state-name = "gold-rail-power-collapse";
arm,psci-suspend-param = <0x40000004>;
entry-latency-us = <327>;
exit-latency-us = <1502>;
min-residency-us = <4488>;
entry-latency-us = <600>;
exit-latency-us = <1550>;
min-residency-us = <4791>;
local-timer-stop;
};
};
@@ -224,10 +226,10 @@ domain-idle-states {
CLUSTER_SLEEP_0: cluster-sleep-0 {
compatible = "domain-idle-state";
idle-state-name = "cluster-l3-off";
arm,psci-suspend-param = <0x4100c344>;
entry-latency-us = <584>;
exit-latency-us = <2332>;
min-residency-us = <6118>;
arm,psci-suspend-param = <0x41000044>;
entry-latency-us = <1050>;
exit-latency-us = <2500>;
min-residency-us = <5309>;
local-timer-stop;
};
@@ -235,9 +237,9 @@ CLUSTER_SLEEP_1: cluster-sleep-1 {
compatible = "domain-idle-state";
idle-state-name = "cluster-power-collapse";
arm,psci-suspend-param = <0x4100c344>;
entry-latency-us = <2893>;
exit-latency-us = <4023>;
min-residency-us = <9987>;
entry-latency-us = <2700>;
exit-latency-us = <3500>;
min-residency-us = <13959>;
local-timer-stop;
};
};
@@ -250,6 +252,18 @@ scm: scm {
};
};
clk_virt: interconnect@0 {
compatible = "qcom,sm8450-clk-virt";
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
mc_virt: interconnect@1 {
compatible = "qcom,sm8450-mc-virt";
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
memory@a0000000 {
device_type = "memory";
/* We expect the bootloader to fill in the size */
@@ -315,7 +329,7 @@ CPU_PD7: cpu7 {
CLUSTER_PD: cpu-cluster0 {
#power-domain-cells = <0>;
domain-idle-states = <&CLUSTER_SLEEP_0>;
domain-idle-states = <&CLUSTER_SLEEP_0>, <&CLUSTER_SLEEP_1>;
};
};
@@ -460,6 +474,15 @@ cvp_mem: memory@9ee00000 {
no-map;
};
rmtfs_mem: memory@9fd00000 {
compatible = "qcom,rmtfs-mem";
reg = <0x0 0x9fd00000 0x0 0x280000>;
no-map;
qcom,client-id = <1>;
qcom,vmid = <15>;
};
global_sync_mem: memory@a6f00000 {
reg = <0x0 0xa6f00000 0x0 0x100000>;
no-map;
@@ -540,6 +563,113 @@ trusted_apps_ext_mem: memory@ed900000 {
};
};
smp2p-adsp {
compatible = "qcom,smp2p";
qcom,smem = <443>, <429>;
interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
IPCC_MPROC_SIGNAL_SMP2P
IRQ_TYPE_EDGE_RISING>;
mboxes = <&ipcc IPCC_CLIENT_LPASS
IPCC_MPROC_SIGNAL_SMP2P>;
qcom,local-pid = <0>;
qcom,remote-pid = <2>;
smp2p_adsp_out: master-kernel {
qcom,entry-name = "master-kernel";
#qcom,smem-state-cells = <1>;
};
smp2p_adsp_in: slave-kernel {
qcom,entry-name = "slave-kernel";
interrupt-controller;
#interrupt-cells = <2>;
};
};
smp2p-cdsp {
compatible = "qcom,smp2p";
qcom,smem = <94>, <432>;
interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
IPCC_MPROC_SIGNAL_SMP2P
IRQ_TYPE_EDGE_RISING>;
mboxes = <&ipcc IPCC_CLIENT_CDSP
IPCC_MPROC_SIGNAL_SMP2P>;
qcom,local-pid = <0>;
qcom,remote-pid = <5>;
smp2p_cdsp_out: master-kernel {
qcom,entry-name = "master-kernel";
#qcom,smem-state-cells = <1>;
};
smp2p_cdsp_in: slave-kernel {
qcom,entry-name = "slave-kernel";
interrupt-controller;
#interrupt-cells = <2>;
};
};
smp2p-modem {
compatible = "qcom,smp2p";
qcom,smem = <435>, <428>;
interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
IPCC_MPROC_SIGNAL_SMP2P
IRQ_TYPE_EDGE_RISING>;
mboxes = <&ipcc IPCC_CLIENT_MPSS
IPCC_MPROC_SIGNAL_SMP2P>;
qcom,local-pid = <0>;
qcom,remote-pid = <1>;
smp2p_modem_out: master-kernel {
qcom,entry-name = "master-kernel";
#qcom,smem-state-cells = <1>;
};
smp2p_modem_in: slave-kernel {
qcom,entry-name = "slave-kernel";
interrupt-controller;
#interrupt-cells = <2>;
};
ipa_smp2p_out: ipa-ap-to-modem {
qcom,entry-name = "ipa";
#qcom,smem-state-cells = <1>;
};
ipa_smp2p_in: ipa-modem-to-ap {
qcom,entry-name = "ipa";
interrupt-controller;
#interrupt-cells = <2>;
};
};
smp2p-slpi {
compatible = "qcom,smp2p";
qcom,smem = <481>, <430>;
interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
IPCC_MPROC_SIGNAL_SMP2P
IRQ_TYPE_EDGE_RISING>;
mboxes = <&ipcc IPCC_CLIENT_SLPI
IPCC_MPROC_SIGNAL_SMP2P>;
qcom,local-pid = <0>;
qcom,remote-pid = <3>;
smp2p_slpi_out: master-kernel {
qcom,entry-name = "master-kernel";
#qcom,smem-state-cells = <1>;
};
smp2p_slpi_in: slave-kernel {
qcom,entry-name = "slave-kernel";
interrupt-controller;
#interrupt-cells = <2>;
};
};
soc: soc@0 {
#address-cells = <2>;
#size-cells = <2>;
@@ -620,6 +750,54 @@ i2c14: i2c@a98000 {
};
};
config_noc: interconnect@1500000 {
compatible = "qcom,sm8450-config-noc";
reg = <0 0x01500000 0 0x1c000>;
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
system_noc: interconnect@1680000 {
compatible = "qcom,sm8450-system-noc";
reg = <0 0x01680000 0 0x1e200>;
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
pcie_noc: interconnect@16c0000 {
compatible = "qcom,sm8450-pcie-anoc";
reg = <0 0x016c0000 0 0xe280>;
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
aggre1_noc: interconnect@16e0000 {
compatible = "qcom,sm8450-aggre1-noc";
reg = <0 0x016e0000 0 0x1c080>;
#interconnect-cells = <2>;
clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
<&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
aggre2_noc: interconnect@1700000 {
compatible = "qcom,sm8450-aggre2-noc";
reg = <0 0x01700000 0 0x31080>;
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
clocks = <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>,
<&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>,
<&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
<&rpmhcc RPMH_IPA_CLK>;
};
mmss_noc: interconnect@1740000 {
compatible = "qcom,sm8450-mmss-noc";
reg = <0 0x01740000 0 0x1f080>;
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
tcsr_mutex: hwlock@1f40000 {
compatible = "qcom,tcsr-mutex";
reg = <0x0 0x01f40000 0x0 0x40000>;
@@ -672,6 +850,167 @@ usb_1_ssphy: phy@88e9200 {
};
};
remoteproc_slpi: remoteproc@2400000 {
compatible = "qcom,sm8450-slpi-pas";
reg = <0 0x02400000 0 0x4000>;
interrupts-extended = <&pdc 9 IRQ_TYPE_LEVEL_HIGH>,
<&smp2p_slpi_in 0 IRQ_TYPE_EDGE_RISING>,
<&smp2p_slpi_in 1 IRQ_TYPE_EDGE_RISING>,
<&smp2p_slpi_in 2 IRQ_TYPE_EDGE_RISING>,
<&smp2p_slpi_in 3 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "wdog", "fatal", "ready",
"handover", "stop-ack";
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
power-domains = <&rpmhpd SM8450_LCX>,
<&rpmhpd SM8450_LMX>;
power-domain-names = "lcx", "lmx";
memory-region = <&slpi_mem>;
qcom,qmp = <&aoss_qmp>;
qcom,smem-states = <&smp2p_slpi_out 0>;
qcom,smem-state-names = "stop";
status = "disabled";
glink-edge {
interrupts-extended = <&ipcc IPCC_CLIENT_SLPI
IPCC_MPROC_SIGNAL_GLINK_QMP
IRQ_TYPE_EDGE_RISING>;
mboxes = <&ipcc IPCC_CLIENT_SLPI
IPCC_MPROC_SIGNAL_GLINK_QMP>;
label = "slpi";
qcom,remote-pid = <3>;
};
};
remoteproc_adsp: remoteproc@30000000 {
compatible = "qcom,sm8450-adsp-pas";
reg = <0 0x030000000 0 0x100>;
interrupts-extended = <&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
<&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
<&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
<&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
<&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "wdog", "fatal", "ready",
"handover", "stop-ack";
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
power-domains = <&rpmhpd SM8450_LCX>,
<&rpmhpd SM8450_LMX>;
power-domain-names = "lcx", "lmx";
memory-region = <&adsp_mem>;
qcom,qmp = <&aoss_qmp>;
qcom,smem-states = <&smp2p_adsp_out 0>;
qcom,smem-state-names = "stop";
status = "disabled";
remoteproc_adsp_glink: glink-edge {
interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
IPCC_MPROC_SIGNAL_GLINK_QMP
IRQ_TYPE_EDGE_RISING>;
mboxes = <&ipcc IPCC_CLIENT_LPASS
IPCC_MPROC_SIGNAL_GLINK_QMP>;
label = "lpass";
qcom,remote-pid = <2>;
};
};
remoteproc_cdsp: remoteproc@32300000 {
compatible = "qcom,sm8450-cdsp-pas";
reg = <0 0x032300000 0 0x1400000>;
interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_LEVEL_HIGH>,
<&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
<&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
<&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>,
<&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "wdog", "fatal", "ready",
"handover", "stop-ack";
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
power-domains = <&rpmhpd SM8450_CX>,
<&rpmhpd SM8450_MXC>;
power-domain-names = "cx", "mxc";
memory-region = <&cdsp_mem>;
qcom,qmp = <&aoss_qmp>;
qcom,smem-states = <&smp2p_cdsp_out 0>;
qcom,smem-state-names = "stop";
status = "disabled";
glink-edge {
interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
IPCC_MPROC_SIGNAL_GLINK_QMP
IRQ_TYPE_EDGE_RISING>;
mboxes = <&ipcc IPCC_CLIENT_CDSP
IPCC_MPROC_SIGNAL_GLINK_QMP>;
label = "cdsp";
qcom,remote-pid = <5>;
};
};
remoteproc_mpss: remoteproc@4080000 {
compatible = "qcom,sm8450-mpss-pas";
reg = <0x0 0x04080000 0x0 0x4040>;
interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>,
<&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>,
<&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>,
<&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>,
<&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>,
<&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "wdog", "fatal", "ready", "handover",
"stop-ack", "shutdown-ack";
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo";
power-domains = <&rpmhpd 0>,
<&rpmhpd 12>;
power-domain-names = "cx", "mss";
memory-region = <&mpss_mem>;
qcom,qmp = <&aoss_qmp>;
qcom,smem-states = <&smp2p_modem_out 0>;
qcom,smem-state-names = "stop";
status = "disabled";
glink-edge {
interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
IPCC_MPROC_SIGNAL_GLINK_QMP
IRQ_TYPE_EDGE_RISING>;
mboxes = <&ipcc IPCC_CLIENT_MPSS
IPCC_MPROC_SIGNAL_GLINK_QMP>;
interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
label = "modem";
qcom,remote-pid = <1>;
};
};
pdc: interrupt-controller@b220000 {
compatible = "qcom,sm8450-pdc", "qcom,pdc";
reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>;
@@ -682,6 +1021,25 @@ pdc: interrupt-controller@b220000 {
interrupt-controller;
};
aoss_qmp: power-controller@c300000 {
compatible = "qcom,sm8450-aoss-qmp", "qcom,aoss-qmp";
reg = <0 0x0c300000 0 0x400>;
interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
IRQ_TYPE_EDGE_RISING>;
mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
#clock-cells = <0>;
};
ipcc: mailbox@ed18000 {
compatible = "qcom,sm8450-ipcc", "qcom,ipcc";
reg = <0 0x0ed18000 0 0x1000>;
interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <3>;
#mbox-cells = <2>;
};
tlmm: pinctrl@f100000 {
compatible = "qcom,sm8450-tlmm";
reg = <0 0x0f100000 0 0x300000>;
@@ -988,6 +1346,20 @@ cpufreq_hw: cpufreq@17d91000 {
#freq-domain-cells = <1>;
};
gem_noc: interconnect@19100000 {
compatible = "qcom,sm8450-gem-noc";
reg = <0 0x19100000 0 0xbb800>;
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
system-cache-controller@19200000 {
compatible = "qcom,sm8450-llcc";
reg = <0 0x19200000 0 0x580000>, <0 0x19a00000 0 0x80000>;
reg-names = "llcc_base", "llcc_broadcast_base";
interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
};
ufs_mem_hc: ufshc@1d84000 {
compatible = "qcom,sm8450-ufshc", "qcom,ufshc",
"jedec,ufs-2.0";
@@ -1004,6 +1376,9 @@ ufs_mem_hc: ufshc@1d84000 {
iommus = <&apps_smmu 0xe0 0x0>;
interconnects = <&aggre1_noc MASTER_UFS_MEM &mc_virt SLAVE_EBI1>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_UFS_MEM_CFG>;
interconnect-names = "ufs-ddr", "cpu-ufs";
clock-names =
"core_clk",
"bus_aggr_clk",
@@ -1102,6 +1477,20 @@ usb_1_dwc3: usb@a600000 {
phy-names = "usb2-phy", "usb3-phy";
};
};
nsp_noc: interconnect@320c0000 {
compatible = "qcom,sm8450-nsp-noc";
reg = <0 0x320c0000 0 0x10000>;
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
lpass_ag_noc: interconnect@3c40000 {
compatible = "qcom,sm8450-lpass-ag-noc";
reg = <0 0x3c40000 0 0x17200>;
#interconnect-cells = <2>;
qcom,bcm-voters = <&apps_bcm_voter>;
};
};
timer {