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Merge tag 'devicetree-for-7.3' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux

Browse Source 
Pull devicetree updates from Rob Herring:

 - Add a DT maintainer profile document

 - Various dt-check-style improvements

 - Add a devres managed reserved memory region init function

 - Print node name on any skipped reserved memory regions

 - Correctly handle optional argument in
   of_parse_phandle_with_args_map()

 - Convert ti,keystone-reset, ti,da850-vpif, TI L4 interconnect, TI
   SmartReflex, microchip,pic32mzda-dmt, microchip,pic32mzda-wdt, TI
   DA8XX MSTPRI bus, and Xen VM bindings to DT schema format

 - Add bindings for StarFive JHB100 plic, Allwinner A733 NMI controller,
   MediaTek MT8173 GPU, QCom Shikra, Eliza, and Maili cpu-bwmon, and
   QCom Shikra SCM firmware

 - A couple of syntax fixes found using PoC Rust implementation of
   dtschema tools

 - Clean-ups for typos, brackets, incorrect "::" usages, and
   white-space style

* tag 'devicetree-for-7.3' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (40 commits)
  dt-bindings: interconnect: qcom-bwmon: Add Maili cpu-bwmon compatible
  dtc: dt-check-style: Simplify setting depth of DtsLine
  dtc: dt-check-style: Add missing /dts-v1/ to few test cases
  dt-bindings: power: reset: ti,keystone-reset: Convert to DT schema
  media: dt-bindings: ti,da850-vpif: Convert to dt-schema
  dt-bindings: devfreq: samsung,exynos-ppmu: Use standard regex syntax
  dt-bindings: interrupt-controller: mediatek,mt6577-sysirq: Drop invalid JSON pointer
  dt-bindings: arm: omap: Convert L4 interconnect to DT schema
  dt-bindings: power: Convert TI SmartReflex to DT schema
  of: reserved_mem: Introduce devres-managed initialization function
  dt-bindings: interrupt-controller: Add StarFive JHB100 plic
  dt-bindings: irq: sun7i-nmi: Document the Allwinner A733 NMI controller
  dt-bindings: Correct white-space style
  dt-bindings: fix typos and brackets
  docs: dt: submitting-patches: Mention expectation about dt-check-style
  docs: dt: maintainer: Add Devicetree and OF maintainer profile document
  docs: dt: writing-schema: Extend expectations about example part of binding
  dt-bindings: gpu: powervr-rogue: Add MediaTek MT8173 GPU
  of: base: Handle optional argument in of_parse_phandle_with_args_map()
  dt-bindings: update Sudeep Holla's email address
  ...
This commit is contained in:
Linus Torvalds
2026-08-19 10:32:34 -07:00
parent f4cdf7ca9a e1c13aed4a
commit c6cf4441a3
152 changed files with 1696 additions and 735 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
Documentation/devicetree/bindings/arm/arm,juno-fpga-apb-regs.yaml
View File

@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: ARM Juno FPGA APB Registers
maintainers:
- Sudeep Holla <sudeep.holla@arm.com>
- Sudeep Holla <sudeep.holla@kernel.org>
properties:
compatible:

2
Documentation/devicetree/bindings/arm/arm,vexpress-juno.yaml
View File

@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: ARM Versatile Express and Juno Boards
maintainers:
- Sudeep Holla <sudeep.holla@arm.com>
- Sudeep Holla <sudeep.holla@kernel.org>
- Linus Walleij <linusw@kernel.org>
description: |+

2
Documentation/devicetree/bindings/arm/arm,vexpress-scc.yaml
View File

@@ -8,7 +8,7 @@ title: ARM Versatile Express Serial Configuration Controller
maintainers:
- Liviu Dudau <liviu.dudau@arm.com>
- Sudeep Holla <sudeep.holla@arm.com>
- Sudeep Holla <sudeep.holla@kernel.org>
description: |
Test chips for ARM Versatile Express platform implement SCC (Serial

8
Documentation/devicetree/bindings/arm/firmware/linaro,optee-tz.yaml
View File

@@ -50,8 +50,8 @@ additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
firmware {
optee {
firmware {
optee {
compatible = "linaro,optee-tz";
method = "smc";
interrupts = <GIC_SPI 187 IRQ_TYPE_EDGE_RISING>;
@@ -59,8 +59,8 @@ examples:
};
- |
firmware {
optee {
firmware {
optee {
compatible = "linaro,optee-tz";
method = "hvc";
};

2
Documentation/devicetree/bindings/arm/mediatek.yaml
View File

@@ -314,7 +314,7 @@ properties:
- const: google,steelix-sku196608
- const: google,steelix
- const: mediatek,mt8186
- description: Google Squirtle (Acer Chromebook Spin 311 (R724T)
- description: Google Squirtle (Acer Chromebook Spin 311 (R724T))
items:
- const: google,squirtle
- const: mediatek,mt8186

37
Documentation/devicetree/bindings/arm/omap/l4.txt
View File

@@ -1,37 +0,0 @@
L4 interconnect bindings
These bindings describe the OMAP SoCs L4 interconnect bus.
Required properties:
- compatible : Should be "ti,omap2-l4" for OMAP2 family l4 core bus
Should be "ti,omap2-l4-wkup" for OMAP2 family l4 wkup bus
Should be "ti,omap3-l4-core" for OMAP3 family l4 core bus
Should be "ti,omap4-l4-cfg" for OMAP4 family l4 cfg bus
Should be "ti,omap4-l4-per" for OMAP4 family l4 per bus
Should be "ti,omap4-l4-wkup" for OMAP4 family l4 wkup bus
Should be "ti,omap5-l4-cfg" for OMAP5 family l4 cfg bus
Should be "ti,omap5-l4-wkup" for OMAP5 family l4 wkup bus
Should be "ti,dra7-l4-cfg" for DRA7 family l4 cfg bus
Should be "ti,dra7-l4-wkup" for DRA7 family l4 wkup bus
Should be "ti,am3-l4-wkup" for AM33xx family l4 wkup bus
Should be "ti,am4-l4-wkup" for AM43xx family l4 wkup bus
- ranges : contains the IO map range for the bus
- reg : registers link agent and interconnect agent and access protection
- reg-names : "la" for link agent, "ia0" to "ia3" for one to three
interconnect agent instances, "ap" for access if it exists
Examples:
l4: interconnect@48000000 {
compatible "ti,omap4-l4-per", "simple-bus";
reg = <0x48000000 0x800>,
<0x48000800 0x800>,
<0x48001000 0x400>,
<0x48001400 0x400>,
<0x48001800 0x400>,
<0x48001c00 0x400>;
reg-names = "ap", "la", "ia0", "ia1", "ia2", "ia3";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x48000000 0x100000>;
};

18
Documentation/devicetree/bindings/arm/psci.yaml
View File

@@ -146,12 +146,12 @@ examples:
// Case 1: PSCI v0.1 only.
psci {
compatible = "arm,psci";
method = "smc";
cpu_suspend = <0x95c10000>;
cpu_off = <0x95c10001>;
cpu_on = <0x95c10002>;
migrate = <0x95c10003>;
compatible = "arm,psci";
method = "smc";
cpu_suspend = <0x95c10000>;
cpu_off = <0x95c10001>;
cpu_on = <0x95c10002>;
migrate = <0x95c10003>;
};
- |+
@@ -159,8 +159,8 @@ examples:
// Case 2: PSCI v0.2 only
psci {
compatible = "arm,psci-0.2";
method = "smc";
compatible = "arm,psci-0.2";
method = "smc";
};
- |+
@@ -251,7 +251,7 @@ examples:
cpu_pd1: power-domain-cpu1 {
#power-domain-cells = <0>;
domain-idle-states = <&cpu_pwrdn>;
domain-idle-states = <&cpu_pwrdn>;
power-domains = <&cluster_pd>;
};

2
Documentation/devicetree/bindings/arm/qcom,coresight-tnoc.yaml
View File

@@ -82,7 +82,7 @@ additionalProperties: false
examples:
- |
tn@109ab000 {
tn@109ab000 {
compatible = "qcom,coresight-tnoc", "arm,primecell";
reg = <0x109ab000 0x4200>;

2
Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml
View File

@@ -9,7 +9,7 @@ title: Trace, Profiling and Diagnostics Monitor - TPDM
description: |
The TPDM or Monitor serves as data collection component for various dataset
types specified in the QPMDA spec. It covers Implementation defined ((ImplDef),
types specified in the QPMDA spec. It covers Implementation defined (ImplDef),
Basic Counts (BC), Tenure Counts (TC), Continuous Multi-Bit (CMB), and Discrete
Single Bit (DSB). It performs data collection in the data producing clock
domain and transfers it to the data collection time domain, generally ATB

4
Documentation/devicetree/bindings/arm/qcom-soc.yaml
View File

@@ -11,10 +11,10 @@ maintainers:
description: |
Guidelines for new compatibles for SoC blocks/components.
When adding new compatibles in new bindings, use the format::
When adding new compatibles in new bindings, use the format:
qcom,SoC-IP
For example::
For example:
qcom,sdm845-llcc-bwmon
When adding new compatibles to existing bindings, use the format in the

4
Documentation/devicetree/bindings/arm/qcom.yaml
View File

@@ -1262,7 +1262,7 @@ properties:
items:
items:
- description: |
MSM chipset ID - an exact match value consisting of two bitfields::
MSM chipset ID - an exact match value consisting of two bitfields:
- bits 0-15 - The unique MSM chipset ID
- bits 16-31 - Reserved; should be 0
- description: |
@@ -1288,7 +1288,7 @@ properties:
- items:
- items:
- description: |
Board ID consisting of three bitfields::
Board ID consisting of three bitfields:
- bits 31-24 - Unused
- bits 23-16 - Platform Version Major
- bits 15-8 - Platform Version Minor

4
Documentation/devicetree/bindings/arm/samsung/samsung-soc.yaml
View File

@@ -11,10 +11,10 @@ maintainers:
description: |
Guidelines for new compatibles for SoC blocks/components.
When adding new compatibles in new bindings, use the format::
When adding new compatibles in new bindings, use the format:
samsung,SoC-IP
For example::
For example:
samsung,exynos5433-cmu-isp
select:

62
Documentation/devicetree/bindings/arm/xen.txt
View File

@@ -1,62 +0,0 @@
* Xen hypervisor device tree bindings
Xen ARM virtual platforms shall have a top-level "hypervisor" node with
the following properties:
- compatible:
compatible = "xen,xen-<version>", "xen,xen";
where <version> is the version of the Xen ABI of the platform.
- reg: specifies the base physical address and size of the regions in memory
where the special resources should be mapped to, using an HYPERVISOR_memory_op
hypercall.
Region 0 is reserved for mapping grant table, it must be always present.
The memory region is large enough to map the whole grant table (it is larger
or equal to gnttab_max_grant_frames()).
Regions 1...N are extended regions (unused address space) for mapping foreign
GFNs and grants, they might be absent if there is nothing to expose.
- interrupts: the interrupt used by Xen to inject event notifications.
A GIC node is also required.
To support UEFI on Xen ARM virtual platforms, Xen populates the FDT "uefi" node
under /hypervisor with following parameters:
________________________________________________________________________________
Name | Size | Description
================================================================================
xen,uefi-system-table | 64-bit | Guest physical address of the UEFI System
| | Table.
--------------------------------------------------------------------------------
xen,uefi-mmap-start | 64-bit | Guest physical address of the UEFI memory
| | map.
--------------------------------------------------------------------------------
xen,uefi-mmap-size | 32-bit | Size in bytes of the UEFI memory map
| | pointed to in previous entry.
--------------------------------------------------------------------------------
xen,uefi-mmap-desc-size | 32-bit | Size in bytes of each entry in the UEFI
| | memory map.
--------------------------------------------------------------------------------
xen,uefi-mmap-desc-ver | 32-bit | Version of the mmap descriptor format.
--------------------------------------------------------------------------------
Example (assuming #address-cells = <2> and #size-cells = <2>):
hypervisor {
compatible = "xen,xen-4.3", "xen,xen";
reg = <0 0xb0000000 0 0x20000>;
interrupts = <1 15 0xf08>;
uefi {
xen,uefi-system-table = <0xXXXXXXXX>;
xen,uefi-mmap-start = <0xXXXXXXXX>;
xen,uefi-mmap-size = <0xXXXXXXXX>;
xen,uefi-mmap-desc-size = <0xXXXXXXXX>;
xen,uefi-mmap-desc-ver = <0xXXXXXXXX>;
};
};
The format and meaning of the "xen,uefi-*" parameters are similar to those in
Documentation/arch/arm/uefi.rst, which are provided by the regular UEFI stub. However
they differ because they are provided by the Xen hypervisor, together with a set
of UEFI runtime services implemented via hypercalls, see
http://xenbits.xen.org/docs/unstable/hypercall/x86_64/include,public,platform.h.html.

110
Documentation/devicetree/bindings/arm/xen.yaml Normal file
View File

@@ -0,0 +1,110 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/xen.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xen hypervisor
maintainers:
- Stefano Stabellini <sstabellini@kernel.org>
description:
Xen ARM virtual platforms shall have a top-level "hypervisor" node with
the properties defined below.
properties:
$nodename:
pattern: '^hypervisor(@[0-9a-f]+)?$'
compatible:
description:
Specifies the Xen hypervisor. The version of the Xen ABI is encoded
in the first item as "xen,xen-<version>", followed by the generic
"xen,xen" string.
items:
- pattern: '^xen,xen-[0-9]+\.[0-9]+$'
- const: xen,xen
reg:
description: |
Base physical address and size of the regions in memory where special
resources should be mapped to, using a HYPERVISOR_memory_op hypercall.
Region 0 is reserved for mapping the grant table and must always be
present. The memory region must be large enough to map the whole grant
table (it is larger or equal to gnttab_max_grant_frames()).
Regions 1...N are extended regions (unused address space) for mapping
foreign GFNs and grants. They might be absent if there is nothing to
expose.
minItems: 1
interrupts:
description:
The interrupt used by Xen to inject event notifications.
A GIC node is also required.
maxItems: 1
uefi:
type: object
description:
Node populated by Xen to support UEFI on Xen ARM virtual platforms.
The format and meaning of the "xen,uefi-*" parameters are similar to
those in Documentation/arch/arm/uefi.rst, but are provided by the Xen
hypervisor together with a set of UEFI runtime services implemented via
hypercalls.
properties:
xen,uefi-system-table:
description: Guest physical address of the UEFI System Table.
$ref: /schemas/types.yaml#/definitions/uint64
xen,uefi-mmap-start:
description: Guest physical address of the UEFI memory map.
$ref: /schemas/types.yaml#/definitions/uint64
xen,uefi-mmap-size:
description: Size in bytes of the UEFI memory map pointed to by xen,uefi-mmap-start.
$ref: /schemas/types.yaml#/definitions/uint32
xen,uefi-mmap-desc-size:
description: Size in bytes of each entry in the UEFI memory map.
$ref: /schemas/types.yaml#/definitions/uint32
xen,uefi-mmap-desc-ver:
description: Version of the mmap descriptor format.
$ref: /schemas/types.yaml#/definitions/uint32
required:
- xen,uefi-system-table
- xen,uefi-mmap-start
- xen,uefi-mmap-size
- xen,uefi-mmap-desc-size
- xen,uefi-mmap-desc-ver
additionalProperties: false
required:
- compatible
- reg
- interrupts
additionalProperties: false
examples:
- |
hypervisor@b0000000 {
compatible = "xen,xen-4.3", "xen,xen";
reg = <0xb0000000 0x20000>;
interrupts = <1 15 0xf08>;
uefi {
xen,uefi-system-table = /bits/ 64 <0x1301415>;
xen,uefi-mmap-start = /bits/ 64 <0x7591400>;
xen,uefi-mmap-size = <0x1800>;
xen,uefi-mmap-desc-size = <0x30>;
xen,uefi-mmap-desc-ver = <1>;
};
};
...

22
Documentation/devicetree/bindings/ata/st,ahci.yaml
View File

@@ -57,16 +57,16 @@ examples:
#include <dt-bindings/clock/stih407-clks.h>
sata@9b20000 {
compatible = "st,ahci";
reg = <0x9b20000 0x1000>;
interrupts = <GIC_SPI 159 IRQ_TYPE_NONE>;
compatible = "st,ahci";
reg = <0x9b20000 0x1000>;
interrupts = <GIC_SPI 159 IRQ_TYPE_NONE>;
interrupt-names = "hostc";
phys = <&phy_port0 PHY_TYPE_SATA>;
phy-names = "sata-phy";
resets = <&powerdown STIH407_SATA0_POWERDOWN>,
<&softreset STIH407_SATA0_SOFTRESET>,
<&softreset STIH407_SATA0_PWR_SOFTRESET>;
reset-names = "pwr-dwn", "sw-rst", "pwr-rst";
clocks = <&clk_s_c0_flexgen CLK_ICN_REG>;
clock-names = "ahci_clk";
phys = <&phy_port0 PHY_TYPE_SATA>;
phy-names = "sata-phy";
resets = <&powerdown STIH407_SATA0_POWERDOWN>,
<&softreset STIH407_SATA0_SOFTRESET>,
<&softreset STIH407_SATA0_PWR_SOFTRESET>;
reset-names = "pwr-dwn", "sw-rst", "pwr-rst";
clocks = <&clk_s_c0_flexgen CLK_ICN_REG>;
clock-names = "ahci_clk";
};

20
Documentation/devicetree/bindings/bus/ti,da850-mstpri.txt
View File

@@ -1,20 +0,0 @@
* Device tree bindings for Texas Instruments da8xx master peripheral
priority driver
DA8XX SoCs feature a set of registers allowing to change the priority of all
peripherals classified as masters.
Documentation:
OMAP-L138 (DA850) - http://www.ti.com/lit/ug/spruh82c/spruh82c.pdf
Required properties:
- compatible: "ti,da850-mstpri" - for da850 based boards
- reg: offset and length of the mstpri registers
Example for da850-lcdk is shown below.
mstpri {
compatible = "ti,da850-mstpri";
reg = <0x14110 0x0c>;
};

37
Documentation/devicetree/bindings/bus/ti,da850-mstpri.yaml Normal file
View File

@@ -0,0 +1,37 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/bus/ti,da850-mstpri.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Texas Instruments DA8XX Master Peripheral Priority Registers
maintainers:
- Eduard Bostina <egbostina@gmail.com>
description: |
DA8XX SoCs feature a set of registers allowing to change the priority of all
peripherals classified as masters.
Documentation:
OMAP-L138 (DA850) - http://www.ti.com/lit/ug/spruh82c/spruh82c.pdf
properties:
compatible:
const: ti,da850-mstpri
reg:
maxItems: 1
required:
- compatible
- reg
additionalProperties: false
examples:
- |
mstpri@14110 {
compatible = "ti,da850-mstpri";
reg = <0x14110 0x0c>;
};

140
Documentation/devicetree/bindings/bus/ti,omap-l4.yaml Normal file
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@@ -0,0 +1,140 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/bus/ti,omap-l4.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: TI OMAP SoCs L4 interconnect bus
maintainers:
- Eduard Bostina <egbostina@gmail.com>
description:
These bindings describe the OMAP SoCs L4 interconnect bus.
select:
properties:
compatible:
contains:
enum:
- ti,omap2-l4
- ti,omap2-l4-wkup
- ti,omap3-l4-core
- ti,omap4-l4-abe
- ti,omap4-l4-cfg
- ti,omap4-l4-per
- ti,omap4-l4-wkup
- ti,omap5-l4-abe
- ti,omap5-l4-cfg
- ti,omap5-l4-per
- ti,omap5-l4-wkup
- ti,dra7-l4-cfg
- ti,dra7-l4-per1
- ti,dra7-l4-per2
- ti,dra7-l4-per3
- ti,dra7-l4-wkup
- ti,am33xx-l4-fast
- ti,am33xx-l4-fw
- ti,am33xx-l4-mpuss
- ti,am33xx-l4-per
- ti,am33xx-l4-wkup
- ti,am4-l4-fast
- ti,am4-l4-per
- ti,am4-l4-wkup
- ti,dm814-l4hs
- ti,dm814-l4ls
required:
- compatible
properties:
compatible:
items:
- enum:
- ti,omap2-l4
- ti,omap2-l4-wkup
- ti,omap3-l4-core
- ti,omap4-l4-abe
- ti,omap4-l4-cfg
- ti,omap4-l4-per
- ti,omap4-l4-wkup
- ti,omap5-l4-abe
- ti,omap5-l4-cfg
- ti,omap5-l4-per
- ti,omap5-l4-wkup
- ti,dra7-l4-cfg
- ti,dra7-l4-per1
- ti,dra7-l4-per2
- ti,dra7-l4-per3
- ti,dra7-l4-wkup
- ti,am33xx-l4-fast
- ti,am33xx-l4-fw
- ti,am33xx-l4-mpuss
- ti,am33xx-l4-per
- ti,am33xx-l4-wkup
- ti,am4-l4-fast
- ti,am4-l4-per
- ti,am4-l4-wkup
- ti,dm814-l4hs
- ti,dm814-l4ls
- enum:
- simple-bus
- simple-pm-bus
reg:
minItems: 1
maxItems: 6
reg-names:
minItems: 1
maxItems: 6
items:
enum:
- ap
- la
- ia0
- ia1
- ia2
- ia3
ranges: true
dma-ranges: true
clocks:
maxItems: 1
clock-names:
items:
- const: fck
power-domains:
maxItems: 1
"#address-cells":
const: 1
"#size-cells":
const: 1
required:
- compatible
- ranges
additionalProperties:
type: object
examples:
- |
bus@48000000 {
compatible = "ti,omap4-l4-per", "simple-bus";
reg = <0x48000000 0x800>,
<0x48000800 0x800>,
<0x48001000 0x400>,
<0x48001400 0x400>,
<0x48001800 0x400>,
<0x48001c00 0x400>;
reg-names = "ap", "la", "ia0", "ia1", "ia2", "ia3";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x48000000 0x100000>;
};

2
Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml
View File

@@ -13,7 +13,7 @@ description: |
Qualcomm display clock control module provides the clocks, resets and power
domains on SM8150/SM8250/SM8350.
See also::
See also:
include/dt-bindings/clock/qcom,dispcc-sm8150.h
include/dt-bindings/clock/qcom,dispcc-sm8250.h
include/dt-bindings/clock/qcom,dispcc-sm8350.h

2
Documentation/devicetree/bindings/clock/qcom,gcc-apq8064.yaml
View File

@@ -14,7 +14,7 @@ description: |
Qualcomm global clock control module provides the clocks, resets and power
domains on APQ8064.
See also::
See also:
include/dt-bindings/clock/qcom,gcc-msm8960.h
include/dt-bindings/reset/qcom,gcc-msm8960.h

2
Documentation/devicetree/bindings/clock/qcom,gcc-apq8084.yaml
View File

@@ -14,7 +14,7 @@ description: |
Qualcomm global clock control module provides the clocks, resets and power
domains on APQ8084.
See also::
See also:
include/dt-bindings/clock/qcom,gcc-apq8084.h
include/dt-bindings/reset/qcom,gcc-apq8084.h

2
Documentation/devicetree/bindings/clock/qcom,gcc-ipq6018.yaml
View File

@@ -15,7 +15,7 @@ description: |
Qualcomm global clock control module provides the clocks, resets and power
domains on IPQ6018.
See also::
See also:
include/dt-bindings/clock/qcom,gcc-ipq6018.h
include/dt-bindings/reset/qcom,gcc-ipq6018.h

2
Documentation/devicetree/bindings/clock/qcom,gcc-ipq8064.yaml
View File

@@ -13,7 +13,7 @@ description: |
Qualcomm global clock control module provides the clocks, resets and power
domains on IPQ8064.
See also::
See also:
include/dt-bindings/clock/qcom,gcc-ipq806x.h (qcom,gcc-ipq8064)
include/dt-bindings/reset/qcom,gcc-ipq806x.h (qcom,gcc-ipq8064)

2
Documentation/devicetree/bindings/clock/qcom,gcc-mdm9607.yaml
View File

@@ -14,7 +14,7 @@ description: |
Qualcomm global clock control module provides the clocks, resets and power
domains.
See also::
See also:
include/dt-bindings/clock/qcom,gcc-mdm9607.h
allOf:

2
Documentation/devicetree/bindings/clock/qcom,gcc-mdm9615.yaml
View File

@@ -14,7 +14,7 @@ description: |
Qualcomm global clock control module provides the clocks, resets and power
domains.
See also::
See also:
include/dt-bindings/clock/qcom,gcc-mdm9615.h
allOf:

2
Documentation/devicetree/bindings/clock/qcom,gcc-msm8660.yaml
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@@ -14,7 +14,7 @@ description: |
Qualcomm global clock control module provides the clocks and resets on
MSM8660
See also::
See also:
include/dt-bindings/clock/qcom,gcc-msm8660.h
include/dt-bindings/reset/qcom,gcc-msm8660.h

2
Documentation/devicetree/bindings/clock/qcom,gcc-msm8909.yaml
View File

@@ -13,7 +13,7 @@ description: |
Qualcomm global clock control module provides the clocks, resets and power
domains on MSM8909, MSM8917 or QM215.
See also::
See also:
include/dt-bindings/clock/qcom,gcc-msm8909.h
include/dt-bindings/clock/qcom,gcc-msm8917.h

2
Documentation/devicetree/bindings/clock/qcom,gcc-msm8916.yaml
View File

@@ -14,7 +14,7 @@ description: |
Qualcomm global clock control module provides the clocks, resets and power
domains on MSM8916 or MSM8939.
See also::
See also:
include/dt-bindings/clock/qcom,gcc-msm8916.h
include/dt-bindings/clock/qcom,gcc-msm8939.h
include/dt-bindings/reset/qcom,gcc-msm8916.h

2
Documentation/devicetree/bindings/clock/qcom,gcc-msm8953.yaml
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@@ -13,7 +13,7 @@ description: |
Qualcomm global clock control module provides the clocks, resets and power
domains on MSM8937, MSM8940, MSM8953 or SDM439.
See also::
See also:
include/dt-bindings/clock/qcom,gcc-msm8917.h
include/dt-bindings/clock/qcom,gcc-msm8953.h

2
Documentation/devicetree/bindings/clock/qcom,gcc-msm8974.yaml
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@@ -15,7 +15,7 @@ description: |
Qualcomm global clock control module provides the clocks, resets and power
domains on MSM8974 (all variants) and MSM8226.
See also::
See also:
include/dt-bindings/clock/qcom,gcc-msm8974.h (qcom,gcc-msm8226 and qcom,gcc-msm8974)
include/dt-bindings/reset/qcom,gcc-msm8974.h (qcom,gcc-msm8226 and qcom,gcc-msm8974)

2
Documentation/devicetree/bindings/clock/qcom,gcc-sdm660.yaml
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@@ -14,7 +14,7 @@ description: |
Qualcomm global clock control module provides the clocks, resets and power
domains on SDM630, SDM636 and SDM660
See also::
See also:
include/dt-bindings/clock/qcom,gcc-sdm660.h (qcom,gcc-sdm630 and qcom,gcc-sdm660)
$ref: qcom,gcc.yaml#

2
Documentation/devicetree/bindings/clock/qcom,gpucc.yaml
View File

@@ -14,7 +14,7 @@ description: |
Qualcomm graphics clock control module provides the clocks, resets and power
domains on Qualcomm SoCs.
See also::
See also:
include/dt-bindings/clock/qcom,gpucc-sdm845.h
include/dt-bindings/clock/qcom,gpucc-sa8775p.h
include/dt-bindings/clock/qcom,gpucc-sc7180.h

2
Documentation/devicetree/bindings/clock/qcom,ipq5018-gcc.yaml
View File

@@ -13,7 +13,7 @@ description: |
Qualcomm global clock control module provides the clocks, resets and power
domains on IPQ5018
See also::
See also:
include/dt-bindings/clock/qcom,ipq5018-gcc.h
include/dt-bindings/reset/qcom,ipq5018-gcc.h

2
Documentation/devicetree/bindings/clock/qcom,ipq9574-gcc.yaml
View File

@@ -13,7 +13,7 @@ description: |
Qualcomm global clock control module provides the clocks, resets and power
domains on IPQ9574
See also::
See also:
include/dt-bindings/clock/qcom,ipq9574-gcc.h
include/dt-bindings/reset/qcom,ipq9574-gcc.h

2
Documentation/devicetree/bindings/clock/qcom,qca8k-nsscc.yaml
View File

@@ -14,7 +14,7 @@ description: |
Qualcomm NSS clock control module provides the clocks and resets
on QCA8386(switch mode)/QCA8084(PHY mode)
See also::
See also:
include/dt-bindings/clock/qcom,qca8k-nsscc.h
include/dt-bindings/reset/qcom,qca8k-nsscc.h

2
Documentation/devicetree/bindings/clock/qcom,qcm2290-gpucc.yaml
View File

@@ -13,7 +13,7 @@ description: |
Qualcomm graphics clock control module provides the clocks, resets and power
domains on Qualcomm SoCs.
See also::
See also:
include/dt-bindings/clock/qcom,qcm2290-gpucc.h
properties:

2
Documentation/devicetree/bindings/clock/qcom,rpmcc.yaml
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@@ -12,7 +12,7 @@ maintainers:
description: |
The clock enumerators are defined in <dt-bindings/clock/qcom,rpmcc.h> and
come in pairs:: FOO_CLK followed by FOO_A_CLK. The latter clock is
come in pairs: FOO_CLK followed by FOO_A_CLK. The latter clock is
an "active" clock, which means that the consumer only care that the clock is
available when the apps CPU subsystem is active, i.e. not suspended or in
deep idle. If it is important that the clock keeps running during system

2
Documentation/devicetree/bindings/clock/qcom,sc7280-lpasscorecc.yaml
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@@ -13,7 +13,7 @@ description: |
Qualcomm LPASS core and audio clock control module provides the clocks and
power domains on SC7280.
See also::
See also:
include/dt-bindings/clock/qcom,lpasscorecc-sc7280.h
include/dt-bindings/clock/qcom,lpassaudiocc-sc7280.h

2
Documentation/devicetree/bindings/clock/qcom,sc8280xp-lpasscc.yaml
View File

@@ -13,7 +13,7 @@ description: |
Qualcomm LPASS core and audio clock control module provides the clocks,
and reset on SC8280XP.
See also::
See also:
include/dt-bindings/clock/qcom,lpasscc-sc8280xp.h
properties:

2
Documentation/devicetree/bindings/clock/qcom,sm6115-lpasscc.yaml
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@@ -14,7 +14,7 @@ description: |
Qualcomm LPASS core and audio clock controllers provide audio-related resets
on SM6115 and its derivatives.
See also::
See also:
include/dt-bindings/clock/qcom,sm6115-lpasscc.h
properties:

2
Documentation/devicetree/bindings/clock/qcom,sm8350-videocc.yaml
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@@ -13,7 +13,7 @@ description: |
Qualcomm video clock control module provides the clocks, resets and power
domains on Qualcomm SoCs.
See also::
See also:
include/dt-bindings/clock/qcom,videocc-sm8350.h
include/dt-bindings/reset/qcom,videocc-sm8350.h

2
Documentation/devicetree/bindings/clock/qcom,videocc.yaml
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@@ -13,7 +13,7 @@ description: |
Qualcomm video clock control module provides the clocks, resets and power
domains on Qualcomm SoCs.
See also::
See also:
include/dt-bindings/clock/qcom,sm6350-videocc.h
include/dt-bindings/clock/qcom,videocc-sc7180.h
include/dt-bindings/clock/qcom,videocc-sc7280.h

4
Documentation/devicetree/bindings/clock/renesas,rcar-usb2-clock-sel.yaml
View File

@@ -13,8 +13,8 @@ description: |
If you connect an external clock to the USB_EXTAL pin only, you should set
the clock rate to "usb_extal" node only.
If you connect an oscillator to both the USB_XTAL and USB_EXTAL, this module
is not needed because this is default setting. (Of course, you can set the
clock rates to both "usb_extal" and "usb_xtal" nodes.
is not needed because this is default setting (Of course, you can set the
clock rates to both "usb_extal" and "usb_xtal" nodes).
Case 1: An external clock connects to R-Car SoC
+----------+ +--- R-Car ---------------------+

6
Documentation/devicetree/bindings/clock/samsung,exynos5260-clock.yaml
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@@ -14,17 +14,17 @@ maintainers:
description: |
Expected external clocks, defined in DTS as fixed-rate clocks with a matching
name::
name:
- "fin_pll" - PLL input clock from XXTI
- "xrtcxti" - input clock from XRTCXTI
- "ioclk_pcm_extclk" - pcm external operation clock
- "ioclk_spdif_extclk" - spdif external operation clock
- "ioclk_i2s_cdclk" - i2s0 codec clock
Phy clocks::
Phy clocks:
There are several clocks which are generated by specific PHYs. These clocks
are fed into the clock controller and then routed to the hardware blocks.
These clocks are defined as fixed clocks in the driver with following names::
These clocks are defined as fixed clocks in the driver with following names:
- "phyclk_dptx_phy_ch3_txd_clk" - dp phy clock for channel 3
- "phyclk_dptx_phy_ch2_txd_clk" - dp phy clock for channel 2
- "phyclk_dptx_phy_ch1_txd_clk" - dp phy clock for channel 1

2
Documentation/devicetree/bindings/clock/samsung,exynos5410-clock.yaml
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@@ -14,7 +14,7 @@ maintainers:
description: |
Expected external clocks, defined in DTS as fixed-rate clocks with a matching
name::
name:
- "fin_pll" - PLL input clock from XXTI
All available clocks are defined as preprocessor macros in

2
Documentation/devicetree/bindings/clock/samsung,exynos5433-clock.yaml
View File

@@ -14,7 +14,7 @@ maintainers:
description: |
Expected external clocks, defined in DTS as fixed-rate clocks with a matching
name::
name:
- "oscclk" - PLL input clock from XXTI
All available clocks are defined as preprocessor macros in

2
Documentation/devicetree/bindings/clock/samsung,exynos7-clock.yaml
View File

@@ -14,7 +14,7 @@ maintainers:
description: |
Expected external clocks, defined in DTS as fixed-rate clocks with a matching
name::
name:
- "fin_pll" - PLL input clock from XXTI
All available clocks are defined as preprocessor macros in

2
Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml
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@@ -17,7 +17,7 @@ description: |
Exynos850 clock controller is comprised of several CMU units, generating
clocks for different domains. Those CMU units are modeled as separate device
tree nodes, and might depend on each other. Root clocks in that clock tree are
two external clocks:: OSCCLK (26 MHz) and RTCCLK (32768 Hz). Those external
two external clocks: OSCCLK (26 MHz) and RTCCLK (32768 Hz). Those external
clocks must be defined as fixed-rate clocks in dts.
CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and

2
Documentation/devicetree/bindings/clock/samsung,exynosautov9-clock.yaml
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@@ -17,7 +17,7 @@ description: |
Exynos Auto v9 clock controller is comprised of several CMU units, generating
clocks for different domains. Those CMU units are modeled as separate device
tree nodes, and might depend on each other. Root clocks in that clock tree are
two external clocks:: OSCCLK/XTCXO (26 MHz) and RTCCLK/XrtcXTI (32768 Hz).
two external clocks: OSCCLK/XTCXO (26 MHz) and RTCCLK/XrtcXTI (32768 Hz).
The external OSCCLK must be defined as fixed-rate clock in dts.
CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and

2
Documentation/devicetree/bindings/clock/samsung,exynosautov920-clock.yaml
View File

@@ -17,7 +17,7 @@ description: |
ExynosAuto v920 clock controller is comprised of several CMU units, generating
clocks for different domains. Those CMU units are modeled as separate device
tree nodes, and might depend on each other. Root clocks in that clock tree are
two external clocks:: OSCCLK/XTCXO (38.4 MHz) and RTCCLK/XrtcXTI (32768 Hz).
two external clocks: OSCCLK/XTCXO (38.4 MHz) and RTCCLK/XrtcXTI (32768 Hz).
The external OSCCLK must be defined as fixed-rate clock in dts.
CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and

2
Documentation/devicetree/bindings/clock/samsung,s5pv210-clock.yaml
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@@ -14,7 +14,7 @@ maintainers:
description: |
Expected external clocks, defined in DTS as fixed-rate clocks with a matching
name::
name:
- "xxti" - external crystal oscillator connected to XXTI and XXTO pins of
the SoC,
- "xusbxti" - external crystal oscillator connected to XUSBXTI and XUSBXTO

2
Documentation/devicetree/bindings/devfreq/event/samsung,exynos-ppmu.yaml
View File

@@ -40,7 +40,7 @@ properties:
type: object
patternProperties:
'^ppmu-event[0-9]+(-[a-z0-9]+){,2}$':
'^ppmu-event[0-9]+(-[a-z0-9]+){0,2}$':
type: object
properties:
event-name:

20
Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
View File

@@ -73,16 +73,16 @@ properties:
clocks:
description: |
Several clocks are used, depending on the variant. Typical ones are::
- bus:: Display AHB clock.
- byte:: Display byte clock.
- byte_intf:: Display byte interface clock.
- core:: Display core clock.
- core_mss:: Core MultiMedia SubSystem clock.
- iface:: Display AXI clock.
- mdp_core:: MDP Core clock.
- mnoc:: MNOC clock
- pixel:: Display pixel clock.
Several clocks are used, depending on the variant. Typical ones are:
- bus: Display AHB clock.
- byte: Display byte clock.
- byte_intf: Display byte interface clock.
- core: Display core clock.
- core_mss: Core MultiMedia SubSystem clock.
- iface: Display AXI clock.
- mdp_core: MDP Core clock.
- mnoc: MNOC clock
- pixel: Display pixel clock.
minItems: 3
maxItems: 12

4
Documentation/devicetree/bindings/display/samsung/samsung,fimd.yaml
View File

@@ -41,7 +41,7 @@ properties:
additionalProperties: false
description: |
Timing configuration for lcd i80 interface support.
The parameters are defined as::
The parameters are defined as:
VCLK(internal) __|??????|_____|??????|_____|??????|_____|??????|_____|??
: : : : :
Address Output --:<XXXXXXXXXXX:XXXXXXXXXXXX:XXXXXXXXXXXX:XXXXXXXXXXXX:XX
@@ -132,7 +132,7 @@ patternProperties:
"^port@[0-4]+$":
$ref: /schemas/graph.yaml#/properties/port
description: |
Contains ports with port with index::
Contains ports with port with index:
0 - for CAMIF0 input,
1 - for CAMIF1 input,
2 - for CAMIF2 input,

12
Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml
View File

@@ -261,9 +261,9 @@ examples:
"ovr1", "ovr2", "vp1", "vp2", "common1";
ti,am65x-oldi-io-ctrl = <&dss_oldi_io_ctrl>;
power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 67 1>,
<&k3_clks 216 1>,
<&k3_clks 67 2>;
clocks = <&k3_clks 67 1>,
<&k3_clks 216 1>,
<&k3_clks 67 2>;
clock-names = "fck", "vp1", "vp2";
interrupts = <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>;
ports {
@@ -299,9 +299,9 @@ examples:
reg-names = "common", "vidl1", "vid",
"ovr1", "ovr2", "vp1", "vp2", "common1";
power-domains = <&k3_pds 186 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 186 6>,
<&vp1_clock>,
<&k3_clks 186 2>;
clocks = <&k3_clks 186 6>,
<&vp1_clock>,
<&k3_clks 186 2>;
clock-names = "fck", "vp1", "vp2";
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
oldi-transmitters {

96
Documentation/devicetree/bindings/display/ti/ti,j721e-dss.yaml
View File

@@ -154,54 +154,54 @@ examples:
#include <dt-bindings/soc/ti,sci_pm_domain.h>
dss: dss@4a00000 {
compatible = "ti,j721e-dss";
reg = <0x04a00000 0x10000>, /* common_m */
<0x04a10000 0x10000>, /* common_s0*/
<0x04b00000 0x10000>, /* common_s1*/
<0x04b10000 0x10000>, /* common_s2*/
<0x04a20000 0x10000>, /* vidl1 */
<0x04a30000 0x10000>, /* vidl2 */
<0x04a50000 0x10000>, /* vid1 */
<0x04a60000 0x10000>, /* vid2 */
<0x04a70000 0x10000>, /* ovr1 */
<0x04a90000 0x10000>, /* ovr2 */
<0x04ab0000 0x10000>, /* ovr3 */
<0x04ad0000 0x10000>, /* ovr4 */
<0x04a80000 0x10000>, /* vp1 */
<0x04aa0000 0x10000>, /* vp2 */
<0x04ac0000 0x10000>, /* vp3 */
<0x04ae0000 0x10000>, /* vp4 */
<0x04af0000 0x10000>; /* wb */
reg-names = "common_m", "common_s0",
"common_s1", "common_s2",
"vidl1", "vidl2","vid1","vid2",
"ovr1", "ovr2", "ovr3", "ovr4",
"vp1", "vp2", "vp3", "vp4",
"wb";
clocks = <&k3_clks 152 0>,
<&k3_clks 152 1>,
<&k3_clks 152 4>,
<&k3_clks 152 9>,
<&k3_clks 152 13>;
clock-names = "fck", "vp1", "vp2", "vp3", "vp4";
power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;
interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "common_m",
"common_s0",
"common_s1",
"common_s2";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
compatible = "ti,j721e-dss";
reg = <0x04a00000 0x10000>, /* common_m */
<0x04a10000 0x10000>, /* common_s0*/
<0x04b00000 0x10000>, /* common_s1*/
<0x04b10000 0x10000>, /* common_s2*/
<0x04a20000 0x10000>, /* vidl1 */
<0x04a30000 0x10000>, /* vidl2 */
<0x04a50000 0x10000>, /* vid1 */
<0x04a60000 0x10000>, /* vid2 */
<0x04a70000 0x10000>, /* ovr1 */
<0x04a90000 0x10000>, /* ovr2 */
<0x04ab0000 0x10000>, /* ovr3 */
<0x04ad0000 0x10000>, /* ovr4 */
<0x04a80000 0x10000>, /* vp1 */
<0x04aa0000 0x10000>, /* vp2 */
<0x04ac0000 0x10000>, /* vp3 */
<0x04ae0000 0x10000>, /* vp4 */
<0x04af0000 0x10000>; /* wb */
reg-names = "common_m", "common_s0",
"common_s1", "common_s2",
"vidl1", "vidl2","vid1","vid2",
"ovr1", "ovr2", "ovr3", "ovr4",
"vp1", "vp2", "vp3", "vp4",
"wb";
clocks = <&k3_clks 152 0>,
<&k3_clks 152 1>,
<&k3_clks 152 4>,
<&k3_clks 152 9>,
<&k3_clks 152 13>;
clock-names = "fck", "vp1", "vp2", "vp3", "vp4";
power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;
interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "common_m",
"common_s0",
"common_s1",
"common_s2";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dpi_out_0: endpoint {
remote-endpoint = <&dp_bridge_input>;
};
};
dpi_out_0: endpoint {
remote-endpoint = <&dp_bridge_input>;
};
};
};
};

36
Documentation/devicetree/bindings/display/ti/ti,k2g-dss.yaml
View File

@@ -80,26 +80,26 @@ examples:
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
dss: dss@2540000 {
compatible = "ti,k2g-dss";
reg = <0x02540000 0x400>,
<0x02550000 0x1000>,
<0x02557000 0x1000>,
<0x0255a800 0x100>,
<0x0255ac00 0x100>;
reg-names = "cfg", "common", "vid1", "ovr1", "vp1";
clocks = <&k2g_clks 0x2 0>,
<&k2g_clks 0x2 1>;
clock-names = "fck", "vp1";
interrupts = <GIC_SPI 247 IRQ_TYPE_EDGE_RISING>;
dss@2540000 {
compatible = "ti,k2g-dss";
reg = <0x02540000 0x400>,
<0x02550000 0x1000>,
<0x02557000 0x1000>,
<0x0255a800 0x100>,
<0x0255ac00 0x100>;
reg-names = "cfg", "common", "vid1", "ovr1", "vp1";
clocks = <&k2g_clks 0x2 0>,
<&k2g_clks 0x2 1>;
clock-names = "fck", "vp1";
interrupts = <GIC_SPI 247 IRQ_TYPE_EDGE_RISING>;
power-domains = <&k2g_pds 0x2>;
power-domains = <&k2g_pds 0x2>;
max-memory-bandwidth = <230000000>;
max-memory-bandwidth = <230000000>;
port {
dpi_out: endpoint {
remote-endpoint = <&sii9022_in>;
};
port {
dpi_out: endpoint {
remote-endpoint = <&sii9022_in>;
};
};
};

2
Documentation/devicetree/bindings/display/verisilicon,dc.yaml
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@@ -75,6 +75,8 @@ required:
- interrupts
- clocks
- clock-names
- resets
- reset-names
- ports
additionalProperties: false

2
Documentation/devicetree/bindings/dsp/mediatek,mt8195-dsp.yaml
View File

@@ -81,7 +81,7 @@ examples:
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
dsp@10803000 {
compatible = "mediatek,mt8195-dsp";
compatible = "mediatek,mt8195-dsp";
reg = <0x10803000 0x1000>,
<0x10840000 0x40000>;
reg-names = "cfg", "sram";

15
Documentation/devicetree/bindings/dts-coding-style.rst
View File

@@ -114,15 +114,16 @@ Order of Properties in Device Node
The following order of properties in device nodes is preferred:
1. "compatible"
2. "reg"
3. "ranges"
4. Standard/common properties (defined by common bindings, e.g. without
1. "device_type" (if applicable)
2. "compatible"
3. "reg"
4. "ranges"
5. Standard/common properties (defined by common bindings, e.g. without
vendor-prefixes)
5. Vendor-specific properties
6. "status" (if applicable), preceded by a blank line if there is content
6. Vendor-specific properties
7. "status" (if applicable), preceded by a blank line if there is content
before the property
7. Child nodes, where each node is preceded with a blank line
8. Child nodes, where each node is preceded with a blank line
The "status" property is by default "okay", thus it can be omitted.

2
Documentation/devicetree/bindings/dvfs/performance-domain.yaml
View File

@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Generic performance domains
maintainers:
- Sudeep Holla <sudeep.holla@arm.com>
- Sudeep Holla <sudeep.holla@kernel.org>
description: |+
This binding is intended for performance management of groups of devices or

2
Documentation/devicetree/bindings/firmware/arm,scmi.yaml
View File

@@ -8,7 +8,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: System Control and Management Interface (SCMI) Message Protocol
maintainers:
- Sudeep Holla <sudeep.holla@arm.com>
- Sudeep Holla <sudeep.holla@kernel.org>
description: |
The SCMI is intended to allow agents such as OSPM to manage various functions

2
Documentation/devicetree/bindings/firmware/arm,scpi.yaml
View File

@@ -8,7 +8,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: System Control and Power Interface (SCPI) Message Protocol
maintainers:
- Sudeep Holla <sudeep.holla@arm.com>
- Sudeep Holla <sudeep.holla@kernel.org>
description: |
Firmware implementing the SCPI described in ARM document number ARM DUI

3
Documentation/devicetree/bindings/firmware/qcom,scm.yaml
View File

@@ -68,6 +68,7 @@ properties:
- qcom,scm-sdx55
- qcom,scm-sdx65
- qcom,scm-sdx75
- qcom,scm-shikra
- qcom,scm-sm6115
- qcom,scm-sm6125
- qcom,scm-sm6350
@@ -156,6 +157,7 @@ allOf:
- qcom,scm-msm8974
- qcom,scm-msm8976
- qcom,scm-qcm2290
- qcom,scm-shikra
- qcom,scm-sm6375
then:
required:
@@ -175,6 +177,7 @@ allOf:
- qcom,scm-msm8660
- qcom,scm-msm8960
- qcom,scm-qcm2290
- qcom,scm-shikra
- qcom,scm-sm6375
then:
properties:

2
Documentation/devicetree/bindings/gpio/st,nomadik-gpio.yaml
View File

@@ -85,7 +85,7 @@ examples:
- |
gpio@8012e080 {
compatible = "st,nomadik-gpio";
reg = <0x8012e080 0x80>;
reg = <0x8012e080 0x80>;
interrupts = <0 120 0x4>;
#gpio-cells = <2>;
gpio-controller;

1
Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml
View File

@@ -15,6 +15,7 @@ properties:
oneOf:
- items:
- enum:
- mediatek,mt8173-gpu
- renesas,r8a7796-gpu
- renesas,r8a77961-gpu
- const: img,img-gx6250

2
Documentation/devicetree/bindings/i2c/samsung,s3c2410-i2c.yaml
View File

@@ -35,7 +35,7 @@ properties:
gpios:
description: |
The order of the GPIOs should be the following:: <SDA, SCL>. The GPIO
The order of the GPIOs should be the following: <SDA, SCL>. The GPIO
specifier depends on the gpio controller. Required in all cases except
for "samsung,s3c2440-hdmiphy-i2c" whose input/output lines are
permanently wired to the respective client.

2
Documentation/devicetree/bindings/i2c/st,sti-i2c.yaml
View File

@@ -60,7 +60,7 @@ examples:
i2c@fed40000 {
compatible = "st,comms-ssc4-i2c";
reg = <0xfed40000 0x110>;
interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_s_a0_ls CLK_ICN_REG>;
clock-names = "ssc";
clock-frequency = <400000>;

6
Documentation/devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml
View File

@@ -13,7 +13,7 @@ description: |
Bandwidth Monitor measures current throughput on buses between various NoC
fabrics and provides information when it crosses configured thresholds.
Certain SoCs might have more than one Bandwidth Monitors, for example on SDM845::
Certain SoCs might have more than one Bandwidth Monitors, for example on SDM845:
- Measuring the bandwidth between CPUs and Last Level Cache Controller -
called just BWMON,
- Measuring the bandwidth between Last Level Cache Controller and memory
@@ -25,9 +25,11 @@ properties:
- const: qcom,msm8998-bwmon # BWMON v4
- items:
- enum:
- qcom,eliza-cpu-bwmon
- qcom,glymur-cpu-bwmon
- qcom,hawi-cpu-bwmon
- qcom,kaanapali-cpu-bwmon
- qcom,maili-cpu-bwmon
- qcom,qcm2290-cpu-bwmon
- qcom,qcs615-cpu-bwmon
- qcom,qcs8300-cpu-bwmon
@@ -46,12 +48,14 @@ properties:
- const: qcom,sdm845-bwmon # BWMON v4, unified register space
- items:
- enum:
- qcom,eliza-llcc-bwmon
- qcom,hawi-llcc-bwmon
- qcom,qcs615-llcc-bwmon
- qcom,qcs8300-llcc-bwmon
- qcom,sa8775p-llcc-bwmon
- qcom,sc7180-llcc-bwmon
- qcom,sc8280xp-llcc-bwmon
- qcom,shikra-cpu-bwmon
- qcom,sm6350-cpu-bwmon
- qcom,sm8250-llcc-bwmon
- qcom,sm8550-llcc-bwmon

14
Documentation/devicetree/bindings/interconnect/samsung,exynos-bus.yaml
View File

@@ -23,7 +23,7 @@ description: |
The each AXI bus has the owned source clock but, has not the only owned power
line. The power line might be shared among one more sub-blocks. So, we can
divide into two type of device as the role of each sub-block. There are two
type of bus devices as following::
type of bus devices as following:
- parent bus device
- passive bus device
@@ -44,8 +44,8 @@ description: |
able to support the bus frequency for all Exynos SoCs.
Detailed correlation between sub-blocks and power line according
to Exynos SoC::
- In case of Exynos3250, there are two power line as following::
to Exynos SoC:
- In case of Exynos3250, there are two power line as following:
VDD_MIF |--- DMC (Dynamic Memory Controller)
VDD_INT |--- LEFTBUS (parent device)
@@ -89,7 +89,7 @@ description: |
|L5 |200000 |200000 |400000 |300000 | ||1000000 |
----------------------------------------------------------
- In case of Exynos4210, there is one power line as following::
- In case of Exynos4210, there is one power line as following:
VDD_INT |--- DMC (parent device, Dynamic Memory Controller)
|--- LEFTBUS
|--- PERIL
@@ -106,7 +106,7 @@ description: |
|--- LCD0
|--- LCD1
- In case of Exynos4x12, there are two power line as following::
- In case of Exynos4x12, there are two power line as following:
VDD_MIF |--- DMC (Dynamic Memory Controller)
VDD_INT |--- LEFTBUS (parent device)
@@ -124,7 +124,7 @@ description: |
|--- LCD0
|--- ISP
- In case of Exynos5422, there are two power line as following::
- In case of Exynos5422, there are two power line as following:
VDD_MIF |--- DREX 0 (parent device, DRAM EXpress controller)
|--- DREX 1
@@ -143,7 +143,7 @@ description: |
|--- FSYS
|--- FSYS2
- In case of Exynos5433, there is VDD_INT power line as following::
- In case of Exynos5433, there is VDD_INT power line as following:
VDD_INT |--- G2D (parent device)
|--- MSCL
|--- GSCL

3
Documentation/devicetree/bindings/interrupt-controller/allwinner,sun7i-a20-sc-nmi.yaml
View File

@@ -33,6 +33,9 @@ properties:
- allwinner,sun50i-a100-nmi
- allwinner,sun50i-h616-nmi
- const: allwinner,sun9i-a80-nmi
- items:
- const: allwinner,sun60i-a733-nmi
- const: allwinner,sun55i-a523-nmi
reg:
maxItems: 1

3
Documentation/devicetree/bindings/interrupt-controller/mediatek,mt6577-sysirq.yaml
View File

@@ -49,7 +49,8 @@ properties:
interrupt-controller: true
"#interrupt-cells":
$ref: arm,gic.yaml#/properties/#interrupt-cells
const: 3
description: The cells have the same encoding as defined in arm,gic.yaml.
required:
- reg

1
Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
View File

@@ -66,6 +66,7 @@ properties:
- spacemit,k1-plic
- starfive,jh7100-plic
- starfive,jh7110-plic
- starfive,jhb100-plic
- tenstorrent,blackhole-plic
- const: sifive,plic-1.0.0
- items:

4
Documentation/devicetree/bindings/leds/qcom,pm8058-led.yaml
View File

@@ -10,10 +10,10 @@ maintainers:
- Krzysztof Kozlowski <krzk@kernel.org>
description: |
The Qualcomm PM8058 contains an LED block for up to six LEDs:: three normal
The Qualcomm PM8058 contains an LED block for up to six LEDs: three normal
LEDs, two "flash" LEDs and one "keypad backlight" LED. The names are quoted
because sometimes these LED drivers are used for wildly different things than
flash or keypad backlight:: their names are more of a suggestion than a
flash or keypad backlight: their names are more of a suggestion than a
hard-wired usecase.
Hardware-wise the different LEDs support slightly different output currents.

6
Documentation/devicetree/bindings/leds/skyworks,aat1290.yaml
View File

@@ -11,7 +11,7 @@ maintainers:
- Krzysztof Kozlowski <krzk@kernel.org>
description: |
The device is controlled through two pins:: FL_EN and EN_SET. The pins when,
The device is controlled through two pins: FL_EN and EN_SET. The pins when,
asserted high, enable flash strobe and movie mode (max 1/2 of flash current)
respectively. In order to add a capability of selecting the strobe signal
source (e.g. CPU or camera sensor) there is an additional switch required,
@@ -39,11 +39,11 @@ properties:
flash-max-microamp:
description: |
Maximum flash LED supply current can be calculated using following
formula:: I = 1A * 162 kOhm / Rset.
formula: I = 1A * 162 kOhm / Rset.
flash-max-timeout-us:
description: |
Maximum flash timeout can be calculated using following formula::
Maximum flash timeout can be calculated using following formula:
T = 8.82 * 10^9 * Ct.
required:

2
Documentation/devicetree/bindings/mailbox/arm,mhuv3.yaml
View File

@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: ARM MHUv3 Mailbox Controller
maintainers:
- Sudeep Holla <sudeep.holla@arm.com>
- Sudeep Holla <sudeep.holla@kernel.org>
- Cristian Marussi <cristian.marussi@arm.com>
description: |

2
Documentation/devicetree/bindings/mailbox/st,sti-mailbox.yaml
View File

@@ -42,7 +42,7 @@ additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
mailbox0: mailbox@8f00000 {
mailbox@8f00000 {
compatible = "st,stih407-mailbox";
reg = <0x8f00000 0x1000>;
interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;

2
Documentation/devicetree/bindings/media/cec/cec-gpio.yaml
View File

@@ -14,7 +14,7 @@ description: |
hooked up to a pull-up GPIO line and - optionally - the HPD line is hooked up
to another GPIO line.
Please note:: the maximum voltage for the CEC line is 3.63V, for the HPD and
Please note: the maximum voltage for the CEC line is 3.63V, for the HPD and
5V lines it is 5.3V. So you may need some sort of level conversion
circuitry when connecting them to a GPIO line.

106
Documentation/devicetree/bindings/media/ti,da850-vpif.txt
View File

@@ -1,106 +0,0 @@
Texas Instruments VPIF
----------------------
The TI Video Port InterFace (VPIF) is the primary component for video
capture and display on the DA850/AM18x family of TI DaVinci/Sitara
SoCs.
TI Document reference: SPRUH82C, Chapter 35
http://www.ti.com/lit/pdf/spruh82
Required properties:
- compatible: must be "ti,da850-vpif"
- reg: physical base address and length of the registers set for the device;
- interrupts: should contain IRQ line for the VPIF
Video Capture:
VPIF has a 16-bit parallel bus input, supporting 2 8-bit channels or a
single 16-bit channel. It should contain one or two port child nodes
with child 'endpoint' node. If there are two ports then port@0 must
describe the input and port@1 output channels. Please refer to the
bindings defined in
Documentation/devicetree/bindings/media/video-interfaces.txt.
Example using 2 8-bit input channels, one of which is connected to an
I2C-connected TVP5147 decoder:
vpif: vpif@217000 {
compatible = "ti,da850-vpif";
reg = <0x217000 0x1000>;
interrupts = <92>;
port@0 {
vpif_input_ch0: endpoint@0 {
reg = <0>;
bus-width = <8>;
remote-endpoint = <&composite_in>;
};
vpif_input_ch1: endpoint@1 {
reg = <1>;
bus-width = <8>;
data-shift = <8>;
};
};
port@1 {
vpif_output_ch0: endpoint {
bus-width = <8>;
remote-endpoint = <&composite_out>;
};
};
};
[ ... ]
&i2c0 {
tvp5147@5d {
compatible = "ti,tvp5147";
reg = <0x5d>;
port {
composite_in: endpoint {
hsync-active = <1>;
vsync-active = <1>;
pclk-sample = <0>;
/* VPIF channel 0 (lower 8-bits) */
remote-endpoint = <&vpif_input_ch0>;
bus-width = <8>;
};
};
};
adv7343@2a {
compatible = "adi,adv7343";
reg = <0x2a>;
port {
composite_out: endpoint {
adi,dac-enable = <1 1 1>;
adi,sd-dac-enable = <1>;
remote-endpoint = <&vpif_output_ch0>;
bus-width = <8>;
};
};
};
};
Alternatively, an example when the bus is configured as a single
16-bit input (e.g. for raw-capture mode):
vpif: vpif@217000 {
compatible = "ti,da850-vpif";
reg = <0x217000 0x1000>;
interrupts = <92>;
port {
vpif_ch0: endpoint {
bus-width = <16>;
};
};
};

168
Documentation/devicetree/bindings/media/ti,da850-vpif.yaml Normal file
View File

@@ -0,0 +1,168 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/ti,da850-vpif.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Texas Instruments DA850/AM18x Video Port Interface (VPIF)
maintainers:
- Lad, Prabhakar <prabhakar.csengg@gmail.com>
description:
The Video Port Interface (VPIF) is the primary component for video capture
and display on the DA850/AM18x family of TI DaVinci/Sitara SoCs.
TI Document reference:- SPRUH82C, Chapter 35
https://www.ti.com/lit/pdf/spruh82
properties:
compatible:
const: ti,da850-vpif
reg:
maxItems: 1
interrupts:
maxItems: 1
power-domains:
maxItems: 1
'#address-cells':
const: 1
'#size-cells':
const: 0
port:
$ref: /schemas/graph.yaml#/$defs/port-base
unevaluatedProperties: false
description:
VPIF port when the bus is configured as a single 16-bit input
properties:
endpoint:
$ref: video-interfaces.yaml#
unevaluatedProperties: false
properties:
bus-width:
enum: [8, 16]
patternProperties:
^port@[0-1]$:
$ref: /schemas/graph.yaml#/$defs/port-base
unevaluatedProperties: false
description:
VPIF has a 16-bit parallel bus input, supporting 2 8-bit channels or a
single 16-bit channel. It should contain one or two port child nodes
with child 'endpoint' node. If there are two ports then port@0 must
describe the input and port@1 output channels.
properties:
endpoint:
$ref: video-interfaces.yaml#
unevaluatedProperties: false
properties:
bus-width:
enum: [8, 16]
endpoint@0:
$ref: video-interfaces.yaml#
unevaluatedProperties: false
description:
First 8-bit channel using the lower data lines [7:0].
properties:
bus-width:
const: 8
data-shift:
const: 0
endpoint@1:
$ref: video-interfaces.yaml#
unevaluatedProperties: false
description:
Second 8-bit channel using the upper data lines [15:8].
properties:
bus-width:
const: 8
data-shift:
const: 8
anyOf:
- properties:
endpoint@0: false
endpoint@1: false
- properties:
endpoint: false
required:
- compatible
- reg
- interrupts
oneOf:
- properties:
port@0: false
port@1: false
- properties:
port: false
additionalProperties: false
examples:
- |
vpif@217000 {
compatible = "ti,da850-vpif";
reg = <0x217000 0x1000>;
interrupts = <92>;
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
vpif_input_ch0: endpoint@0 {
reg = <0>;
bus-width = <8>;
remote-endpoint = <&composite_in>;
};
vpif_input_ch1: endpoint@1 {
reg = <1>;
bus-width = <8>;
data-shift = <8>;
};
};
port@1 {
reg = <1>;
vpif_output_ch0: endpoint {
bus-width = <8>;
remote-endpoint = <&composite_out>;
};
};
};
- |
vpif@217000 {
compatible = "ti,da850-vpif";
reg = <0x217000 0x1000>;
interrupts = <92>;
port {
vpif_ch0: endpoint {
bus-width = <16>;
};
};
};

2
Documentation/devicetree/bindings/memory-controllers/renesas,dbsc.yaml
View File

@@ -13,7 +13,7 @@ description: |
Renesas SoCs contain one or more memory controllers. These memory
controllers differ from one SoC variant to another, and are called by
different names, e.g. "DDR Bus Controller (DBSC)", "DDR3 Bus State Controller
(DBSC3)", or "SDRAM Bus State Controller (SBSC)").
(DBSC3)", or "SDRAM Bus State Controller (SBSC)".
properties:
compatible:

2
Documentation/devicetree/bindings/mfd/maxim,max77620.yaml
View File

@@ -311,7 +311,7 @@ examples:
in-sd3-supply = <&vdd_5v0_vbus>;
in-ldo0-1-supply = <&vdd_1v8_vio>;
in-ldo2-supply = <&vdd_3v3_vbat>;
in-ldo2-supply = <&vdd_3v3_vbat>;
in-ldo3-5-supply = <&vdd_3v3_vbat>;
in-ldo4-6-supply = <&vdd_3v3_vbat>;
in-ldo7-8-supply = <&vdd_1v8_vio>;

2
Documentation/devicetree/bindings/mmc/samsung,exynos-dw-mshc.yaml
View File

@@ -85,7 +85,7 @@ properties:
description: |
The value of CIU TX and RX clock phase shift value for HS400 mode
operation.
Valid values for SDR and DDR CIU clock timing::
Valid values for SDR and DDR CIU clock timing:
- valid value for tx phase shift and rx phase shift is 0 to 7.
- when CIU clock divider value is set to 3, all possible 8 phase shift
values can be used.

34
Documentation/devicetree/bindings/net/wireless/qcom,ath10k.yaml
View File

@@ -390,22 +390,22 @@ examples:
<GIC_SPI 46 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 47 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi0",
"msi1",
"msi2",
"msi3",
"msi4",
"msi5",
"msi6",
"msi7",
"msi8",
"msi9",
"msi10",
"msi11",
"msi12",
"msi13",
"msi14",
"msi15",
"legacy";
interrupt-names = "msi0",
"msi1",
"msi2",
"msi3",
"msi4",
"msi5",
"msi6",
"msi7",
"msi8",
"msi9",
"msi10",
"msi11",
"msi12",
"msi13",
"msi14",
"msi15",
"legacy";
ieee80211-freq-limit = <5470000 5875000>;
};

28
Documentation/devicetree/bindings/opp/opp-v2.yaml
View File

@@ -293,9 +293,9 @@ examples:
opp-microvolt = <970000>, /* Supply 0 */
<960000>, /* Supply 1 */
<960000>; /* Supply 2 */
opp-microamp = <70000>, /* Supply 0 */
<70000>, /* Supply 1 */
<70000>; /* Supply 2 */
opp-microamp = <70000>, /* Supply 0 */
<70000>, /* Supply 1 */
<70000>; /* Supply 2 */
clock-latency-ns = <300000>;
};
@@ -306,9 +306,9 @@ examples:
opp-microvolt = <975000 970000 985000>, /* Supply 0 */
<965000 960000 975000>, /* Supply 1 */
<965000 960000 975000>; /* Supply 2 */
opp-microamp = <70000>, /* Supply 0 */
<70000>, /* Supply 1 */
<70000>; /* Supply 2 */
opp-microamp = <70000>, /* Supply 0 */
<70000>, /* Supply 1 */
<70000>; /* Supply 2 */
clock-latency-ns = <300000>;
};
@@ -317,11 +317,11 @@ examples:
opp-1000000002 {
opp-hz = /bits/ 64 <1000000002>;
opp-microvolt = <975000 970000 985000>, /* Supply 0 */
<965000 960000 975000>, /* Supply 1 */
<965000 960000 975000>; /* Supply 2 */
opp-microamp = <70000>, /* Supply 0 */
<0>, /* Supply 1 doesn't need this */
<70000>; /* Supply 2 */
<965000 960000 975000>, /* Supply 1 */
<965000 960000 975000>; /* Supply 2 */
opp-microamp = <70000>, /* Supply 0 */
<0>, /* Supply 1 doesn't need this */
<70000>; /* Supply 2 */
clock-latency-ns = <300000>;
};
};
@@ -405,8 +405,8 @@ examples:
opp-hz = /bits/ 64 <1000000000>;
opp-microvolt-slow = <915000 900000 925000>;
opp-microvolt-fast = <975000 970000 985000>;
opp-microamp-slow = <70000>;
opp-microamp-fast = <71000>;
opp-microamp-slow = <70000>;
opp-microamp-fast = <71000>;
};
opp-1200000000 {
@@ -415,7 +415,7 @@ examples:
<925000 910000 935000>; /* Supply vcc1 */
opp-microvolt-fast = <975000 970000 985000>, /* Supply vcc0 */
<965000 960000 975000>; /* Supply vcc1 */
opp-microamp = <70000>; /* Will be used for both slow/fast */
opp-microamp = <70000>; /* Will be used for both slow/fast */
};
};

4
Documentation/devicetree/bindings/phy/samsung,mipi-video-phy.yaml
View File

@@ -13,14 +13,14 @@ maintainers:
description: |
For samsung,s5pv210-mipi-video-phy compatible PHYs the second cell in the
PHY specifier identifies the PHY and its meaning is as follows::
PHY specifier identifies the PHY and its meaning is as follows:
0 - MIPI CSIS 0,
1 - MIPI DSIM 0,
2 - MIPI CSIS 1,
3 - MIPI DSIM 1.
samsung,exynos5420-mipi-video-phy and samsung,exynos5433-mipi-video-phy
support additional fifth PHY::
support additional fifth PHY:
4 - MIPI CSIS 2.
properties:

2
Documentation/devicetree/bindings/phy/samsung,usb2-phy.yaml
View File

@@ -14,7 +14,7 @@ maintainers:
description: |
The first phandle argument in the PHY specifier identifies the PHY, its
meaning is compatible dependent. For the currently supported SoCs (Exynos4210
and Exynos4212) it is as follows::
and Exynos4212) it is as follows:
0 - USB device ("device"),
1 - USB host ("host"),
2 - HSIC0 ("hsic0"),

2
Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml
View File

@@ -14,7 +14,7 @@ maintainers:
description: |
For samsung,exynos5250-usbdrd-phy and samsung,exynos5420-usbdrd-phy
compatible PHYs, the second cell in the PHY specifier identifies the
PHY id, which is interpreted as follows::
PHY id, which is interpreted as follows:
0 - UTMI+ type phy,
1 - PIPE3 type phy.

2
Documentation/devicetree/bindings/pinctrl/mediatek,mt7988-pinctrl.yaml
View File

@@ -573,7 +573,7 @@ examples:
uart0_pins: uart0-pins {
mux {
function = "uart";
groups = "uart0";
groups = "uart0";
};
};
};

2
Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml
View File

@@ -18,7 +18,7 @@ description: |
All the pin controller nodes should be represented in the aliases node using
the following format 'pinctrl{n}' where n is a unique number for the alias.
The controller supports three types of interrupts::
The controller supports three types of interrupts:
- External GPIO interrupts (see interrupts property in pin controller node);
- External wake-up interrupts - multiplexed (capable of waking up the system

2
Documentation/devicetree/bindings/power/renesas,rcar-sysc.yaml
View File

@@ -13,7 +13,7 @@ maintainers:
description: |
The R-Car (RZ/G) System Controller provides power management for the CPU
cores and various coprocessors.
The power domain IDs for consumers are defined in header files::
The power domain IDs for consumers are defined in header files:
include/dt-bindings/power/r8*-sysc.h
properties:

67
Documentation/devicetree/bindings/power/reset/keystone-reset.txt
View File

@@ -1,67 +0,0 @@
* Device tree bindings for Texas Instruments keystone reset
This node is intended to allow SoC reset in case of software reset
of selected watchdogs.
The Keystone SoCs can contain up to 4 watchdog timers to reset
SoC. Each watchdog timer event input is connected to the Reset Mux
block. The Reset Mux block can be configured to cause reset or not.
Additionally soft or hard reset can be configured.
Required properties:
- compatible: ti,keystone-reset
- ti,syscon-pll: phandle/offset pair. The phandle to syscon used to
access pll controller registers and the offset to use
reset control registers.
- ti,syscon-dev: phandle/offset pair. The phandle to syscon used to
access device state control registers and the offset
in order to use mux block registers for all watchdogs.
Optional properties:
- ti,soft-reset: Boolean option indicating soft reset.
By default hard reset is used.
- ti,wdt-list: WDT list that can cause SoC reset. It's not related
to WDT driver, it's just needed to enable a SoC related
reset that's triggered by one of WDTs. The list is
in format: <0>, <2>; It can be in random order and
begins from 0 to 3, as keystone can contain up to 4 SoC
reset watchdogs and can be in random order.
Example 1:
Setup keystone reset so that in case software reset or
WDT0 is triggered it issues hard reset for SoC.
pllctrl: pll-controller@2310000 {
compatible = "ti,keystone-pllctrl", "syscon";
reg = <0x02310000 0x200>;
};
devctrl: device-state-control@2620000 {
compatible = "ti,keystone-devctrl", "syscon";
reg = <0x02620000 0x1000>;
};
rstctrl: reset-controller {
compatible = "ti,keystone-reset";
ti,syscon-pll = <&pllctrl 0xe4>;
ti,syscon-dev = <&devctrl 0x328>;
ti,wdt-list = <0>;
};
Example 2:
Setup keystone reset so that in case of software reset or
WDT0 or WDT2 is triggered it issues soft reset for SoC.
rstctrl: reset-controller {
compatible = "ti,keystone-reset";
ti,syscon-pll = <&pllctrl 0xe4>;
ti,syscon-dev = <&devctrl 0x328>;
ti,wdt-list = <0>, <2>;
ti,soft-reset;
};

8
Documentation/devicetree/bindings/power/reset/restart-handler.yaml
View File

@@ -18,12 +18,12 @@ properties:
priority:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
A priority ranging from 0 to 255 according to the following guidelines::
0:: Restart handler of last resort, with limited restart capabilities.
128:: Typical, default restart handler; use if no other restart handler
A priority ranging from 0 to 255 according to the following guidelines:
0: Restart handler of last resort, with limited restart capabilities.
128: Typical, default restart handler; use if no other restart handler
is expected to be available, and/or if restart functionality is
sufficient to restart the entire system.
255:: Highest priority restart handler, will preempt all other restart handlers.
255: Highest priority restart handler, will preempt all other restart handlers.
minimum: 0
maximum: 255

81
Documentation/devicetree/bindings/power/reset/ti,keystone-reset.yaml Normal file
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@@ -0,0 +1,81 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/power/reset/ti,keystone-reset.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: TI Keystone SoC Reset Controller
maintainers:
- Andrew Davis <afd@ti.com>
description:
This is intended to allow SoC reset in case of software reset of selected
watchdogs. The Keystone SoCs can contain up to 4 watchdog timers to reset
SoC. Each watchdog timer event input is connected to the Reset Mux block. The
Reset Mux block can be configured to cause reset or not. Additionally soft or
hard reset can be configured.
properties:
compatible:
const: ti,keystone-reset
reg:
maxItems: 1
ti,syscon-pll:
$ref: /schemas/types.yaml#/definitions/phandle-array
description:
The phandle to syscon used to access pll controller registers and the
offset to use reset control registers.
items:
- items:
- description: phandle to pll controller syscon
- description: offset within pll controller register space
ti,syscon-dev:
$ref: /schemas/types.yaml#/definitions/phandle-array
description:
The phandle to syscon used to access device state control registers and
the offset in order to use mux block registers for all watchdogs.
items:
- items:
- description: phandle to device state control syscon
- description: offset within device state control register
ti,soft-reset:
type: boolean
description:
Boolean option indicating soft reset. By default hard reset is used.
ti,wdt-list:
$ref: /schemas/types.yaml#/definitions/uint32-array
description:
WDT list that can cause SoC reset. It's not related to WDT driver, it's
just needed to enable a SoC related reset that's triggered by one of
WDTs. The list is in format- <0>, <2>; It can be in random order and
begins from 0 to 3, as keystone can contain up to 4 SoC reset watchdogs
and can be in random order.
minItems: 1
maxItems: 4
items:
minimum: 0
maximum: 3
required:
- compatible
- reg
- ti,syscon-pll
- ti,syscon-dev
additionalProperties: false
examples:
- |
reset-controller@328 {
compatible = "ti,keystone-reset";
reg = <0x328 0x10>;
ti,syscon-pll = <&pllctrl 0xe4>;
ti,syscon-dev = <&devctrl 0x328>;
ti,wdt-list = <0>;
};

4
Documentation/devicetree/bindings/power/supply/maxim,max17042.yaml
View File

@@ -44,13 +44,13 @@ properties:
Defining this property enables current-sense functionality.
maxim,cold-temp:
$ref: /schemas/types.yaml#/definitions/uint32
$ref: /schemas/types.yaml#/definitions/int32
description:
Temperature threshold to report battery as cold (in tenths of degree Celsius).
Default is not to report cold events.
maxim,over-heat-temp:
$ref: /schemas/types.yaml#/definitions/uint32
$ref: /schemas/types.yaml#/definitions/int32
description:
Temperature threshold to report battery as over heated (in tenths of degree Celsius).
Default is not to report over heating events.

50
Documentation/devicetree/bindings/power/ti,smartreflex.yaml Normal file
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@@ -0,0 +1,50 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/power/ti,smartreflex.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Texas Instruments SmartReflex
maintainers:
- Eduard Bostina <egbostina@gmail.com>
description:
SmartReflex is used to set and adjust the SoC operating points.
properties:
compatible:
enum:
- ti,omap3-smartreflex-core
- ti,omap3-smartreflex-mpu-iva
- ti,omap4-smartreflex-core
- ti,omap4-smartreflex-mpu
- ti,omap4-smartreflex-iva
reg:
maxItems: 1
interrupts:
maxItems: 1
ti,hwmods:
description: Shall contain the TI interconnect module name if needed by the SoC
$ref: /schemas/types.yaml#/definitions/string
deprecated: true
required:
- compatible
- reg
- interrupts
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
smartreflex@4a0db000 {
compatible = "ti,omap4-smartreflex-iva";
reg = <0x4a0db000 0x80>;
interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
};

47
Documentation/devicetree/bindings/power/ti-smartreflex.txt
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@@ -1,47 +0,0 @@
Texas Instruments SmartReflex binding
SmartReflex is used to set and adjust the SoC operating points.
Required properties:
compatible: Shall be one of the following:
"ti,omap3-smartreflex-core"
"ti,omap3-smartreflex-mpu-iva"
"ti,omap4-smartreflex-core"
"ti,omap4-smartreflex-mpu"
"ti,omap4-smartreflex-iva"
reg: Shall contain the device instance IO range
interrupts: Shall contain the device instance interrupt
Optional properties:
ti,hwmods: Shall contain the TI interconnect module name if needed
by the SoC
Example:
smartreflex_iva: smartreflex@4a0db000 {
compatible = "ti,omap4-smartreflex-iva";
reg = <0x4a0db000 0x80>;
interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "smartreflex_iva";
};
smartreflex_core: smartreflex@4a0dd000 {
compatible = "ti,omap4-smartreflex-core";
reg = <0x4a0dd000 0x80>;
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "smartreflex_core";
};
smartreflex_mpu: smartreflex@4a0d9000 {
compatible = "ti,omap4-smartreflex-mpu";
reg = <0x4a0d9000 0x80>;
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "smartreflex_mpu";
};

12
Documentation/devicetree/bindings/ptp/fsl,ptp.yaml
View File

@@ -146,11 +146,11 @@ examples:
reg = <0x24e00 0xb0>;
interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
interrupt-parent = <&ipic>;
fsl,cksel = <1>;
fsl,cksel = <1>;
fsl,tclk-period = <10>;
fsl,tmr-prsc = <100>;
fsl,tmr-add = <0x999999a4>;
fsl,tmr-fiper1 = <0x3b9ac9f6>;
fsl,tmr-fiper2 = <0x00018696>;
fsl,max-adj = <659999998>;
fsl,tmr-prsc = <100>;
fsl,tmr-add = <0x999999a4>;
fsl,tmr-fiper1 = <0x3b9ac9f6>;
fsl,tmr-fiper2 = <0x00018696>;
fsl,max-adj = <659999998>;
};

2
Documentation/devicetree/bindings/pwm/pwm-sifive.yaml
View File

@@ -62,7 +62,7 @@ additionalProperties: false
examples:
- |
pwm: pwm@10020000 {
pwm@10020000 {
compatible = "sifive,fu540-c000-pwm", "sifive,pwm0";
reg = <0x10020000 0x1000>;
clocks = <&tlclk>;

4
Documentation/devicetree/bindings/regulator/maxim,max77802.yaml
View File

@@ -22,13 +22,13 @@ description: |
Certain regulators support "regulator-initial-mode" and "regulator-mode".
The valid modes list is defined in the dt-bindings/regulator/maxim,max77802.h
and their meaning is::
and their meaning is:
1 - Normal regulator voltage output mode.
3 - Low Power which reduces the quiescent current down to only 1uA
The standard "regulator-mode" property can only be used for regulators that
support changing their mode to Low Power Mode during suspend. These
regulators are:: bucks 2-4 and LDOs 1-35. Also, it only takes effect if the
regulators are: bucks 2-4 and LDOs 1-35. Also, it only takes effect if the
regulator has been enabled for the given suspend state using
"regulator-on-in-suspend" and has not been disabled for that state using
"regulator-off-in-suspend".

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