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ARM: dts: meson8m2: add resets for the power domain controller

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The Meson8m2 SoCs has introduced additional reset lines for the VPU
compared to Meson8. Also it uses a slightly different VPU clock
frequency compared to Meson8 since it can now achieve 364MHz thanks to
the addition of the GP_PLL.
Add the reset lines, VPU clock configuration and update the compatible
string so the implementation differences can be managed.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Link: https://lore.kernel.org/r/20200620161010.23171-3-martin.blumenstingl@googlemail.com
This commit is contained in:
Martin Blumenstingl
2020-06-20 18:10:09 +02:00
committed by Kevin Hilman
parent aecc72b14d
commit c5d3d3cf00
1 changed files with 19 additions and 0 deletions
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19
arch/arm/boot/dts/meson8m2.dtsi
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@@ -61,6 +61,25 @@ mux {
};
};
&pwrc {
compatible = "amlogic,meson8m2-pwrc";
resets = <&reset RESET_DBLK>,
<&reset RESET_PIC_DC>,
<&reset RESET_HDMI_APB>,
<&reset RESET_HDMI_SYSTEM_RESET>,
<&reset RESET_VENCI>,
<&reset RESET_VENCP>,
<&reset RESET_VDAC_4>,
<&reset RESET_VENCL>,
<&reset RESET_VIU>,
<&reset RESET_VENC>,
<&reset RESET_RDMA>;
reset-names = "dblk", "pic_dc", "hdmi_apb", "hdmi_system", "venci",
"vencp", "vdac", "vencl", "viu", "venc", "rdma";
assigned-clocks = <&clkc CLKID_VPU>;
assigned-clock-rates = <364000000>;
};
&saradc {
compatible = "amlogic,meson8m2-saradc", "amlogic,meson-saradc";
};