arm64: dts: ti: k3-am64: MDIO pinmux should belong to the MDIO node

Although usually integrated as a child of an Ethernet controller, MDIO
IP has an independent pinout. This pinout should be controlled by
the MDIO node (so if it was to be disabled for instance, the pinmux
state would reflect that).

Move the MDIO pins pinmux to the MIDO nodes.

Signed-off-by: Andrew Davis <afd@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Bryan Brattlof <bb@ti.com>
Acked-by: Vignesh Raghavendra <vigneshr@ti.com>
Link: https://lore.kernel.org/r/20221017192532.23825-8-afd@ti.com
This commit is contained in:
Andrew Davis
2022-10-17 14:25:29 -05:00
committed by Nishanth Menon
parent 3e21ec289c
commit aa62d66124
2 changed files with 8 additions and 4 deletions

View File

@@ -425,8 +425,7 @@ &usb0 {
&cpsw3g {
pinctrl-names = "default";
pinctrl-0 = <&mdio1_pins_default
&rgmii1_pins_default
pinctrl-0 = <&rgmii1_pins_default
&rgmii2_pins_default>;
};
@@ -441,6 +440,9 @@ &cpsw_port2 {
};
&cpsw3g_mdio {
pinctrl-names = "default";
pinctrl-0 = <&mdio1_pins_default>;
cpsw3g_phy0: ethernet-phy@0 {
reg = <0>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;

View File

@@ -439,8 +439,7 @@ &usb0 {
&cpsw3g {
pinctrl-names = "default";
pinctrl-0 = <&mdio1_pins_default
&rgmii1_pins_default
pinctrl-0 = <&rgmii1_pins_default
&rgmii2_pins_default>;
};
@@ -455,6 +454,9 @@ &cpsw_port2 {
};
&cpsw3g_mdio {
pinctrl-names = "default";
pinctrl-0 = <&mdio1_pins_default>;
cpsw3g_phy0: ethernet-phy@0 {
reg = <0>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;