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drm/amdgpu/gfx9.4.3: Fix MEC rollback loop in EOP IRQ setup

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Fix the error cleanup path in gfx_v9_4_3_set_userq_eop_interrupts() by
using the correct loop condition. This ensures all previously enabled
EOP IRQs are released if setup fails.

Fixes: 832f0aa050 ("drm/amdgpu/gfx9.4.3: add support for disabling kernel queues")
Reported-by: Dan Carpenter <error27@gmail.com>
Cc: Kent Russell <kent.russell@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Srinivasan Shanmugam
2026-07-10 16:33:24 +05:30
committed by Alex Deucher
parent 4c8b8472f8
commit a947c8662e
1 changed files with 1 additions and 1 deletions
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2
drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
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@@ -2331,7 +2331,7 @@ static int gfx_v9_4_3_set_userq_eop_interrupts(struct amdgpu_device *adev,
}
}
for (xcc_id--; xcc_id >= 0; xcc_id--) {
for (m = adev->gfx.mec.num_mec - 1; m <= 0; m--) {
for (m = adev->gfx.mec.num_mec - 1; m >= 0; m--) {
for (p = adev->gfx.mec.num_pipe_per_mec - 1; p >= 0; p--) {
irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
+ (m * adev->gfx.mec.num_pipe_per_mec) + p;