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arm64: dts: ti: k3-am65-ti-ipc-firmware: Refactor IPC cfg into new dtsi
The TI K3 AM65 SoCs have multiple programmable remote processors like R5Fs. The TI SDKs for AM65 SoCs offer sample firmwares which could be run on these cores to demonstrate an "echo" IPC test. Those firmware require certain memory carveouts to be reserved from system memory, timers to be reserved, and certain mailbox configurations for interrupt based messaging. These configurations could be different for a different firmware. While DT is not meant for system configurations, at least refactor these configurations from board level DTS into a dtsi for now. This dtsi for TI IPC firmware is board-independent and can be applied to all boards from the same SoC Family. This gets rid of code duplication and allows more freedom for users developing custom firmware (or no firmware) to utilize system resources better; easily by swapping out this dtsi. To maintain backward compatibility, the dtsi is included in all boards. Signed-off-by: Beleswar Padhi <b-padhi@ti.com> Link: https://patch.msgid.link/20250908142826.1828676-35-b-padhi@ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
This commit is contained in:
Beleswar Padhi
committed by
Nishanth Menon
Nishanth Menon
parent
3ad3ab0bfa
commit
a26bc9175f
@@ -59,24 +59,6 @@ mcu_r5fss0_core0_memory_region: memory@a0100000 {
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no-map;
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};
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mcu_r5fss0_core1_dma_memory_region: memory@a1000000 {
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compatible = "shared-dma-pool";
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reg = <0 0xa1000000 0 0x100000>;
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no-map;
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};
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mcu_r5fss0_core1_memory_region: memory@a1100000 {
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compatible = "shared-dma-pool";
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reg = <0 0xa1100000 0 0xf00000>;
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no-map;
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};
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rtos_ipc_memory_region: memory@a2000000 {
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reg = <0x00 0xa2000000 0x00 0x00200000>;
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alignment = <0x1000>;
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no-map;
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};
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/* To reserve the power-on(PON) reason for watchdog reset */
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wdt_reset_memory_region: wdt-memory@a2200000 {
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reg = <0x00 0xa2200000 0x00 0x1000>;
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@@ -582,44 +564,6 @@ &pcie1_rc {
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reset-gpios = <&wkup_gpio0 27 GPIO_ACTIVE_HIGH>;
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};
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&mailbox0_cluster0 {
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status = "okay";
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interrupts = <436>;
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mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
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ti,mbox-tx = <1 0 0>;
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ti,mbox-rx = <0 0 0>;
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};
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};
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&mailbox0_cluster1 {
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status = "okay";
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interrupts = <432>;
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mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
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ti,mbox-tx = <1 0 0>;
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ti,mbox-rx = <0 0 0>;
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};
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};
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&mcu_r5fss0 {
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status = "okay";
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};
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&mcu_r5fss0_core0 {
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memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
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<&mcu_r5fss0_core0_memory_region>;
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mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
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status = "okay";
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};
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&mcu_r5fss0_core1 {
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memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
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<&mcu_r5fss0_core1_memory_region>;
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mboxes = <&mailbox0_cluster1 &mbox_mcu_r5fss0_core1>;
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status = "okay";
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};
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&mcu_rti1 {
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memory-region = <&wdt_reset_memory_region>;
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};
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@@ -692,3 +636,9 @@ &mcu_r5fss0 {
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/* lock-step mode not supported on iot2050 boards */
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ti,cluster-mode = <0>;
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};
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#include "k3-am65-ti-ipc-firmware.dtsi"
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&rtos_ipc_memory_region {
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reg = <0x00 0xa2000000 0x00 0x00200000>;
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};
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64
arch/arm64/boot/dts/ti/k3-am65-ti-ipc-firmware.dtsi
Normal file
64
arch/arm64/boot/dts/ti/k3-am65-ti-ipc-firmware.dtsi
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@@ -0,0 +1,64 @@
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// SPDX-License-Identifier: GPL-2.0-only OR MIT
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/**
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* Device Tree Source for enabling IPC using TI SDK firmware on AM65 SoCs
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*
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* Copyright (C) 2016-2025 Texas Instruments Incorporated - https://www.ti.com/
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*/
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&reserved_memory {
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mcu_r5fss0_core1_dma_memory_region: memory@a1000000 {
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compatible = "shared-dma-pool";
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reg = <0 0xa1000000 0 0x100000>;
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no-map;
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};
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mcu_r5fss0_core1_memory_region: memory@a1100000 {
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compatible = "shared-dma-pool";
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reg = <0 0xa1100000 0 0xf00000>;
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no-map;
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};
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rtos_ipc_memory_region: memory@a2000000 {
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reg = <0x00 0xa2000000 0x00 0x00100000>;
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alignment = <0x1000>;
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no-map;
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};
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};
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&mailbox0_cluster0 {
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status = "okay";
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interrupts = <436>;
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mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
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ti,mbox-tx = <1 0 0>;
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ti,mbox-rx = <0 0 0>;
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};
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};
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&mailbox0_cluster1 {
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status = "okay";
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interrupts = <432>;
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mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
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ti,mbox-tx = <1 0 0>;
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ti,mbox-rx = <0 0 0>;
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};
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};
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&mcu_r5fss0 {
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status = "okay";
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};
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&mcu_r5fss0_core0 {
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memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
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<&mcu_r5fss0_core0_memory_region>;
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mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
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status = "okay";
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};
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&mcu_r5fss0_core1 {
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memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
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<&mcu_r5fss0_core1_memory_region>;
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mboxes = <&mailbox0_cluster1 &mbox_mcu_r5fss0_core1>;
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status = "okay";
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};
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@@ -61,24 +61,6 @@ mcu_r5fss0_core0_memory_region: memory@a0100000 {
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reg = <0 0xa0100000 0 0xf00000>;
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no-map;
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};
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mcu_r5fss0_core1_dma_memory_region: memory@a1000000 {
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compatible = "shared-dma-pool";
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reg = <0 0xa1000000 0 0x100000>;
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no-map;
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};
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mcu_r5fss0_core1_memory_region: memory@a1100000 {
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compatible = "shared-dma-pool";
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reg = <0 0xa1100000 0 0xf00000>;
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no-map;
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};
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rtos_ipc_memory_region: memory@a2000000 {
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reg = <0x00 0xa2000000 0x00 0x00100000>;
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alignment = <0x1000>;
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no-map;
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};
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};
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gpio-keys {
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@@ -521,44 +503,6 @@ &serdes1 {
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status = "disabled";
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};
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&mailbox0_cluster0 {
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status = "okay";
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interrupts = <436>;
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mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
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ti,mbox-tx = <1 0 0>;
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ti,mbox-rx = <0 0 0>;
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};
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};
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&mailbox0_cluster1 {
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status = "okay";
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interrupts = <432>;
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mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
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ti,mbox-tx = <1 0 0>;
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ti,mbox-rx = <0 0 0>;
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};
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};
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&mcu_r5fss0 {
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status = "okay";
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};
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&mcu_r5fss0_core0 {
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memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
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<&mcu_r5fss0_core0_memory_region>;
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mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>;
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status = "okay";
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};
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&mcu_r5fss0_core1 {
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memory-region = <&mcu_r5fss0_core1_dma_memory_region>,
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<&mcu_r5fss0_core1_memory_region>;
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mboxes = <&mailbox0_cluster1 &mbox_mcu_r5fss0_core1>;
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status = "okay";
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};
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&ospi0 {
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status = "okay";
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pinctrl-names = "default";
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@@ -653,3 +597,5 @@ &dss {
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&wkup_gpio0 {
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bootph-all;
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};
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#include "k3-am65-ti-ipc-firmware.dtsi"
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