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drm/amd/display: plumb PMO per-plane pstate methods into mode_support
[Why] mode_support reads mode_lib.ms.uclk_pstate_switch_modes to enforce the vactive pstate margin, but nothing populates it: the memset clears it and the PMO selection is never passed in. The check always sees na and never runs, so a plane with negative vactive margin can still pass and blank the display. [How] Add a const per-plane pstate-method pointer to mode_support_ex, point it at stage3.pstate_switch_modes when stage 3 has run (NULL otherwise), and copy it into mode_lib.ms after the memset. Scope the support-required check to the vactive methods it governs (vactive, fw_vactive_drr) so SVP, DRR and vblank planes are not rejected by the vactive support flag. Reviewed-by: Charlene Liu <charlene.liu@amd.com> Signed-off-by: Alexander Chechik <alexander.chechik@amd.com> Signed-off-by: Matthew Stewart <matthew.stewart2@amd.com> Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
committed by
Alex Deucher
parent
fa0300333d
commit
9fcd9c7545
@@ -554,13 +554,9 @@ bool core_dcn4_mode_support(struct dml2_core_mode_support_in_out *in_out)
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l->mode_support_ex_params.min_clk_index = in_out->min_clk_index;
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l->mode_support_ex_params.out_evaluation_info = &in_out->mode_support_result.cfg_support_info.clean_me_up.support_info;
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for (i = 0; i < l->svp_expanded_display_cfg.num_planes; i++) {
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if (i < in_out->display_cfg->display_config.num_planes)
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core->clean_me_up.mode_lib.ms.uclk_pstate_switch_modes[i] =
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in_out->display_cfg->stage3.pstate_switch_modes[i];
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else
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core->clean_me_up.mode_lib.ms.uclk_pstate_switch_modes[i] = dml2_pstate_method_na;
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}
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l->mode_support_ex_params.uclk_pstate_switch_modes =
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in_out->display_cfg->stage3.performed ?
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in_out->display_cfg->stage3.pstate_switch_modes : NULL;
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result = dml2_core_calcs_mode_support_ex(&l->mode_support_ex_params);
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@@ -8057,6 +8057,16 @@ static bool dml_core_mode_support(struct dml2_core_calcs_mode_support_ex *in_out
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memset(&mode_lib->ms, 0, sizeof(struct dml2_core_internal_mode_support));
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mode_lib->ms.num_active_planes = display_cfg->num_planes;
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for (k = 0; k < mode_lib->ms.num_active_planes; k++) {
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if (in_out_params->uclk_pstate_switch_modes &&
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!dml_is_phantom_pipe(&display_cfg->plane_descriptors[k]))
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mode_lib->ms.uclk_pstate_switch_modes[k] =
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in_out_params->uclk_pstate_switch_modes[k];
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else
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mode_lib->ms.uclk_pstate_switch_modes[k] = dml2_pstate_method_na;
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}
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get_stream_output_bpp(s->OutputBpp, display_cfg);
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mode_lib->ms.state_idx = in_out_params->min_clk_index;
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@@ -9644,14 +9654,13 @@ static bool dml_core_mode_support(struct dml2_core_calcs_mode_support_ex *in_out
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if (!display_cfg->overrides.all_streams_blanked) {
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for (k = 0; k < mode_lib->ms.num_active_planes; k++) {
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if (mode_lib->ms.uclk_pstate_switch_modes[k] == dml2_pstate_method_na)
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if (mode_lib->ms.uclk_pstate_switch_modes[k] != dml2_pstate_method_vactive &&
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mode_lib->ms.uclk_pstate_switch_modes[k] != dml2_pstate_method_fw_vactive_drr)
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continue;
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mode_lib->ms.support.global_dram_clock_change_support_required = true;
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if ((mode_lib->ms.uclk_pstate_switch_modes[k] == dml2_pstate_method_vactive ||
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mode_lib->ms.uclk_pstate_switch_modes[k] == dml2_pstate_method_fw_vactive_drr) &&
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mode_lib->ms.VActiveLatencyHidingMargin[k] < 0)
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if (mode_lib->ms.VActiveLatencyHidingMargin[k] < 0)
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mode_lib->ms.support.global_dram_clock_change_supported = false;
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}
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}
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@@ -2333,6 +2333,7 @@ struct dml2_core_calcs_mode_support_ex {
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int min_clk_index;
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//unsigned int in_state_index;
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struct dml2_core_internal_mode_support_info *out_evaluation_info;
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const enum dml2_pstate_method *uclk_pstate_switch_modes;
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};
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struct core_display_cfg_support_info;
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