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drm/amd/display: Fix rounding errors in CalculatePrefetchSchedule

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[why]

Rounding errors were causing mode validation to fail in some cases when
it should not. (IE. Increasing fclk from a lower value could lead to
validation failure, which should not happen.)

Reviewed-by: Dillon Varone <dillon.varone@amd.com>
Signed-off-by: Matthew Stewart <Matthew.Stewart2@amd.com>
Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Matthew Stewart
2026-06-19 13:41:36 -04:00
committed by Alex Deucher
parent 695bc1971e
commit fa0300333d
1 changed files with 6 additions and 3 deletions
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9
drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn4_calcs.c
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@@ -5622,7 +5622,8 @@ static bool CalculatePrefetchSchedule(struct dml2_core_internal_scratch *scratch
+ 2 * (p->PixelPTEBytesPerRow * p->HostVMInefficiencyFactor + p->meta_row_bytes + tdlut_row_bytes)
+ *p->prefetch_sw_bytes)
/ (*p->Tpre_rounded - *p->Tno_bw);
s->Tsw_est1 = *p->prefetch_sw_bytes / s->prefetch_bw1;
/* due to rounding, VM can clamp to +1/4, Row can clamp to +2/4, giving SW less time */
s->Tsw_est1 = *p->prefetch_sw_bytes / s->prefetch_bw1 - 3.0 * s->LineTime / 4.0;
} else
s->prefetch_bw1 = 0;
@@ -5646,7 +5647,8 @@ static bool CalculatePrefetchSchedule(struct dml2_core_internal_scratch *scratch
if (*p->Tpre_rounded - *p->Tno_bw - 2.0 * s->Tr0_trips_rounded > 0) {
s->prefetch_bw2 = (vm_bytes * p->HostVMInefficiencyFactor + *p->prefetch_sw_bytes) /
(*p->Tpre_rounded - *p->Tno_bw - 2.0 * s->Tr0_trips_rounded);
s->Tsw_est2 = *p->prefetch_sw_bytes / s->prefetch_bw2;
/* due to rounding, VM can clamp to +1/4 */
s->Tsw_est2 = *p->prefetch_sw_bytes / s->prefetch_bw2 - 1.0 * s->LineTime / 4.0;
} else
s->prefetch_bw2 = 0;
@@ -5660,7 +5662,8 @@ static bool CalculatePrefetchSchedule(struct dml2_core_internal_scratch *scratch
if (*p->Tpre_rounded - s->Tvm_trips_rounded > 0) {
s->prefetch_bw3 = (2 * (p->PixelPTEBytesPerRow * p->HostVMInefficiencyFactor + p->meta_row_bytes + tdlut_row_bytes) + *p->prefetch_sw_bytes) /
(*p->Tpre_rounded - s->Tvm_trips_rounded);
s->Tsw_est3 = *p->prefetch_sw_bytes / s->prefetch_bw3;
/* due to rounding, Row can clamp to +2/4 */
s->Tsw_est3 = *p->prefetch_sw_bytes / s->prefetch_bw3 - 2.0 * s->LineTime / 4.0;
} else
s->prefetch_bw3 = 0;