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perf vendor events arm64: Fix Tegra410 Olympus event 0x0197

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The name and description for NVIDIA Tegra410 Olympus implementation-defined
event 0x0197 incorrectly indicate a TXREQ limit between one quarter and
one half. Correct them to describe a TXREQ limit below one half.

Fixes: 86ff690f45 ("perf vendor events arm64: Add Tegra410 Olympus PMU events")
Signed-off-by: Besar Wicaksono <bwicaksono@nvidia.com>
Reviewed-by: Ian Rogers <irogers@google.com>
Signed-off-by: Namhyung Kim <namhyung@kernel.org>
This commit is contained in:
Besar Wicaksono
2026-08-13 17:01:55 +00:00
committed by Namhyung Kim
parent 2d85e13c55
commit 9453bc6a69
1 changed files with 3 additions and 3 deletions
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6
tools/perf/pmu-events/arch/arm64/nvidia/t410/misc.json
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@@ -316,8 +316,8 @@
},
{
"EventCode": "0x0197",
"EventName": "TXREQ_LIMIT_1QUARTER_CYCLES",
"PublicDescription": "Number of cycles in which the dynamic TXREQ limit is between 1/4 of the L2_TQ_SIZE and 1/2 of the L2_TQ_SIZE."
"EventName": "TXREQ_LIMIT_BELOW_HALF_CYCLES",
"PublicDescription": "Number of cycles in which the dynamic TXREQ limit is between 0 and 1/2 of the L2_TQ_SIZE."
},
{
"EventCode": "0x019d",
@@ -517,7 +517,7 @@
{
"EventCode": "0x01cc",
"EventName": "TXREQ_LIMIT_COUNT_CYCLES",
"PublicDescription": "This event increments by the dynamic TXREQ value, in each cycle.\nThis is a companion event of TXREQ_LIMIT_MAX_CYCLES, TXREQ_LIMIT_3QUARTER_CYCLES, TXREQ_LIMIT_HALF_CYCLES, and TXREQ_LIMIT_1QUARTER_CYCLES."
"PublicDescription": "This event increments by the dynamic TXREQ value, in each cycle.\nThis is a companion event of TXREQ_LIMIT_MAX_CYCLES, TXREQ_LIMIT_3QUARTER_CYCLES, TXREQ_LIMIT_HALF_CYCLES, and TXREQ_LIMIT_BELOW_HALF_CYCLES."
},
{
"EventCode": "0x01ce",