From 9453bc6a69ef43755f1c28d5688cacdd69fa16bd Mon Sep 17 00:00:00 2001 From: Besar Wicaksono Date: Thu, 13 Aug 2026 17:01:55 +0000 Subject: [PATCH] perf vendor events arm64: Fix Tegra410 Olympus event 0x0197 The name and description for NVIDIA Tegra410 Olympus implementation-defined event 0x0197 incorrectly indicate a TXREQ limit between one quarter and one half. Correct them to describe a TXREQ limit below one half. Fixes: 86ff690f45cc ("perf vendor events arm64: Add Tegra410 Olympus PMU events") Signed-off-by: Besar Wicaksono Reviewed-by: Ian Rogers Signed-off-by: Namhyung Kim --- tools/perf/pmu-events/arch/arm64/nvidia/t410/misc.json | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/tools/perf/pmu-events/arch/arm64/nvidia/t410/misc.json b/tools/perf/pmu-events/arch/arm64/nvidia/t410/misc.json index 8ff87d844e52..e1b45cc33b18 100644 --- a/tools/perf/pmu-events/arch/arm64/nvidia/t410/misc.json +++ b/tools/perf/pmu-events/arch/arm64/nvidia/t410/misc.json @@ -316,8 +316,8 @@ }, { "EventCode": "0x0197", - "EventName": "TXREQ_LIMIT_1QUARTER_CYCLES", - "PublicDescription": "Number of cycles in which the dynamic TXREQ limit is between 1/4 of the L2_TQ_SIZE and 1/2 of the L2_TQ_SIZE." + "EventName": "TXREQ_LIMIT_BELOW_HALF_CYCLES", + "PublicDescription": "Number of cycles in which the dynamic TXREQ limit is between 0 and 1/2 of the L2_TQ_SIZE." }, { "EventCode": "0x019d", @@ -517,7 +517,7 @@ { "EventCode": "0x01cc", "EventName": "TXREQ_LIMIT_COUNT_CYCLES", - "PublicDescription": "This event increments by the dynamic TXREQ value, in each cycle.\nThis is a companion event of TXREQ_LIMIT_MAX_CYCLES, TXREQ_LIMIT_3QUARTER_CYCLES, TXREQ_LIMIT_HALF_CYCLES, and TXREQ_LIMIT_1QUARTER_CYCLES." + "PublicDescription": "This event increments by the dynamic TXREQ value, in each cycle.\nThis is a companion event of TXREQ_LIMIT_MAX_CYCLES, TXREQ_LIMIT_3QUARTER_CYCLES, TXREQ_LIMIT_HALF_CYCLES, and TXREQ_LIMIT_BELOW_HALF_CYCLES." }, { "EventCode": "0x01ce",