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arm64: dts: qcom: qcs8300: add the first 2.5G ethernet

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Add the node for the first ethernet interface on qcs8300 platform.
Add the internal SGMII/SerDes PHY node as well.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Yijie Yang <quic_yijiyang@quicinc.com>
Link: https://lore.kernel.org/r/20241206-dts_qcs8300-v5-1-422e4fda292d@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Yijie Yang
2024-12-06 09:35:04 +08:00
committed by Bjorn Andersson
parent ce4b3c48e4
commit 86d32baddc
1 changed files with 43 additions and 0 deletions
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43
arch/arm64/boot/dts/qcom/qcs8300.dtsi
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@@ -2590,6 +2590,15 @@ cti@6900000 {
clock-names = "apb_pclk";
};
serdes0: phy@8909000 {
compatible = "qcom,qcs8300-dwmac-sgmii-phy", "qcom,sa8775p-dwmac-sgmii-phy";
reg = <0x0 0x08909000 0x0 0x00000e10>;
clocks = <&gcc GCC_SGMI_CLKREF_EN>;
clock-names = "sgmi_ref";
#phy-cells = <0>;
status = "disabled";
};
pmu@9091000 {
compatible = "qcom,qcs8300-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
reg = <0x0 0x9091000 0x0 0x1000>;
@@ -3151,6 +3160,40 @@ IPCC_MPROC_SIGNAL_GLINK_QMP
};
};
ethernet0: ethernet@23040000 {
compatible = "qcom,qcs8300-ethqos", "qcom,sa8775p-ethqos";
reg = <0x0 0x23040000 0x0 0x00010000>,
<0x0 0x23056000 0x0 0x00000100>;
reg-names = "stmmaceth", "rgmii";
interrupts = <GIC_SPI 946 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 783 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "macirq", "sfty";
clocks = <&gcc GCC_EMAC0_AXI_CLK>,
<&gcc GCC_EMAC0_SLV_AHB_CLK>,
<&gcc GCC_EMAC0_PTP_CLK>,
<&gcc GCC_EMAC0_PHY_AUX_CLK>;
clock-names = "stmmaceth",
"pclk",
"ptp_ref",
"phyaux";
power-domains = <&gcc GCC_EMAC0_GDSC>;
phys = <&serdes0>;
phy-names = "serdes";
iommus = <&apps_smmu 0x120 0xf>;
dma-coherent;
snps,tso;
snps,pbl = <32>;
rx-fifo-depth = <16384>;
tx-fifo-depth = <20480>;
status = "disabled";
};
nspa_noc: interconnect@260c0000 {
compatible = "qcom,qcs8300-nspa-noc";
reg = <0x0 0x260c0000 0x0 0x16080>;