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Merge tag 'qcom-arm32-for-6.13' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt

Browse Source 
Qualcomm Arm32 DeviceTree updates for v6.13

IPQ4019 flash partition scheme is moved to nvmem-layout. SDX55 and SDX65
PCIe EP controllers gain missing linux,pci-domain properties.

Stylistic improvements across a range of platforms and devices.

* tag 'qcom-arm32-for-6.13' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux:
  ARM: dts: qcom: ipq4019: use nvmem-layout
  ARM: dts: qcom: change labels to lower-case
  ARM: dts: qcom: sdx65: Add 'linux,pci-domain' to PCIe EP controller node
  ARM: dts: qcom: sdx55: Add 'linux,pci-domain' to PCIe EP controller node
  ARM: dts: qcom: minor whitespace cleanup
  ARM: dts: qcom: drop underscore in node names

Link: https://lore.kernel.org/r/20241104034744.14378-1-andersson@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
2024-11-12 22:36:51 +01:00
parent 2ffd61e39e ef4b38462e
commit 7e2574fafd
14 changed files with 186 additions and 181 deletions
Download Patch File Download Diff File Expand all files Collapse all files

38
arch/arm/boot/dts/qcom/qcom-apq8064.dtsi
View File

@@ -36,58 +36,58 @@ cpus {
#address-cells = <1>;
#size-cells = <0>;
CPU0: cpu@0 {
cpu0: cpu@0 {
compatible = "qcom,krait";
enable-method = "qcom,kpss-acc-v1";
device_type = "cpu";
reg = <0>;
next-level-cache = <&L2>;
next-level-cache = <&l2>;
qcom,acc = <&acc0>;
qcom,saw = <&saw0>;
cpu-idle-states = <&CPU_SPC>;
cpu-idle-states = <&cpu_spc>;
};
CPU1: cpu@1 {
cpu1: cpu@1 {
compatible = "qcom,krait";
enable-method = "qcom,kpss-acc-v1";
device_type = "cpu";
reg = <1>;
next-level-cache = <&L2>;
next-level-cache = <&l2>;
qcom,acc = <&acc1>;
qcom,saw = <&saw1>;
cpu-idle-states = <&CPU_SPC>;
cpu-idle-states = <&cpu_spc>;
};
CPU2: cpu@2 {
cpu2: cpu@2 {
compatible = "qcom,krait";
enable-method = "qcom,kpss-acc-v1";
device_type = "cpu";
reg = <2>;
next-level-cache = <&L2>;
next-level-cache = <&l2>;
qcom,acc = <&acc2>;
qcom,saw = <&saw2>;
cpu-idle-states = <&CPU_SPC>;
cpu-idle-states = <&cpu_spc>;
};
CPU3: cpu@3 {
cpu3: cpu@3 {
compatible = "qcom,krait";
enable-method = "qcom,kpss-acc-v1";
device_type = "cpu";
reg = <3>;
next-level-cache = <&L2>;
next-level-cache = <&l2>;
qcom,acc = <&acc3>;
qcom,saw = <&saw3>;
cpu-idle-states = <&CPU_SPC>;
cpu-idle-states = <&cpu_spc>;
};
L2: l2-cache {
l2: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
idle-states {
CPU_SPC: cpu-spc {
cpu_spc: cpu-spc {
compatible = "qcom,idle-state-spc",
"arm,idle-state";
entry-latency-us = <400>;
@@ -675,7 +675,7 @@ qfprom: efuse@700000 {
tsens_calib: calib@404 {
reg = <0x404 0x10>;
};
tsens_backup: backup_calib@414 {
tsens_backup: backup-calib@414 {
reg = <0x414 0x10>;
};
};
@@ -1625,7 +1625,7 @@ etm@1a1c000 {
clocks = <&rpmcc RPM_QDSS_CLK>;
clock-names = "apb_pclk";
cpu = <&CPU0>;
cpu = <&cpu0>;
out-ports {
port {
@@ -1643,7 +1643,7 @@ etm@1a1d000 {
clocks = <&rpmcc RPM_QDSS_CLK>;
clock-names = "apb_pclk";
cpu = <&CPU1>;
cpu = <&cpu1>;
out-ports {
port {
@@ -1661,7 +1661,7 @@ etm@1a1e000 {
clocks = <&rpmcc RPM_QDSS_CLK>;
clock-names = "apb_pclk";
cpu = <&CPU2>;
cpu = <&cpu2>;
out-ports {
port {
@@ -1679,7 +1679,7 @@ etm@1a1f000 {
clocks = <&rpmcc RPM_QDSS_CLK>;
clock-names = "apb_pclk";
cpu = <&CPU3>;
cpu = <&cpu3>;
out-ports {
port {

78
arch/arm/boot/dts/qcom/qcom-apq8084.dtsi
View File

@@ -17,7 +17,7 @@ reserved-memory {
#size-cells = <1>;
ranges;
smem_mem: smem_region@fa00000 {
smem_mem: smem-region@fa00000 {
reg = <0xfa00000 0x200000>;
no-map;
};
@@ -32,10 +32,10 @@ cpu@0 {
compatible = "qcom,krait";
reg = <0>;
enable-method = "qcom,kpss-acc-v2";
next-level-cache = <&L2>;
next-level-cache = <&l2>;
qcom,acc = <&acc0>;
qcom,saw = <&saw0>;
cpu-idle-states = <&CPU_SPC>;
cpu-idle-states = <&cpu_spc>;
};
cpu@1 {
@@ -43,10 +43,10 @@ cpu@1 {
compatible = "qcom,krait";
reg = <1>;
enable-method = "qcom,kpss-acc-v2";
next-level-cache = <&L2>;
next-level-cache = <&l2>;
qcom,acc = <&acc1>;
qcom,saw = <&saw1>;
cpu-idle-states = <&CPU_SPC>;
cpu-idle-states = <&cpu_spc>;
};
cpu@2 {
@@ -54,10 +54,10 @@ cpu@2 {
compatible = "qcom,krait";
reg = <2>;
enable-method = "qcom,kpss-acc-v2";
next-level-cache = <&L2>;
next-level-cache = <&l2>;
qcom,acc = <&acc2>;
qcom,saw = <&saw2>;
cpu-idle-states = <&CPU_SPC>;
cpu-idle-states = <&cpu_spc>;
};
cpu@3 {
@@ -65,13 +65,13 @@ cpu@3 {
compatible = "qcom,krait";
reg = <3>;
enable-method = "qcom,kpss-acc-v2";
next-level-cache = <&L2>;
next-level-cache = <&l2>;
qcom,acc = <&acc3>;
qcom,saw = <&saw3>;
cpu-idle-states = <&CPU_SPC>;
cpu-idle-states = <&cpu_spc>;
};
L2: l2-cache {
l2: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
@@ -79,7 +79,7 @@ L2: l2-cache {
};
idle-states {
CPU_SPC: cpu-spc {
cpu_spc: cpu-spc {
compatible = "qcom,idle-state-spc",
"arm,idle-state";
entry-latency-us = <150>;
@@ -311,7 +311,7 @@ tsens_s9_p1: s9-p1@d8 {
bits = <0 6>;
};
tsens_s10_p1: s10_p1@d8 {
tsens_s10_p1: s10-p1@d8 {
reg = <0xd8 0x2>;
bits = <6 6>;
};
@@ -371,137 +371,137 @@ tsens_s9_p2: s9-p2@e1 {
bits = <4 6>;
};
tsens_s10_p2: s10_p2@e2 {
tsens_s10_p2: s10-p2@e2 {
reg = <0xe2 0x2>;
bits = <2 6>;
};
tsens_s5_p2_backup: s5-p2_backup@e3 {
tsens_s5_p2_backup: s5-p2-backup@e3 {
reg = <0xe3 0x2>;
bits = <0 6>;
};
tsens_mode_backup: mode_backup@e3 {
tsens_mode_backup: mode-backup@e3 {
reg = <0xe3 0x1>;
bits = <6 2>;
};
tsens_s6_p2_backup: s6-p2_backup@e4 {
tsens_s6_p2_backup: s6-p2-backup@e4 {
reg = <0xe4 0x1>;
bits = <0 6>;
};
tsens_s7_p2_backup: s7-p2_backup@e4 {
tsens_s7_p2_backup: s7-p2-backup@e4 {
reg = <0xe4 0x2>;
bits = <6 6>;
};
tsens_s8_p2_backup: s8-p2_backup@e5 {
tsens_s8_p2_backup: s8-p2-backup@e5 {
reg = <0xe5 0x2>;
bits = <4 6>;
};
tsens_s9_p2_backup: s9-p2_backup@e6 {
tsens_s9_p2_backup: s9-p2-backup@e6 {
reg = <0xe6 0x2>;
bits = <2 6>;
};
tsens_s10_p2_backup: s10_p2_backup@e7 {
tsens_s10_p2_backup: s10-p2-backup@e7 {
reg = <0xe7 0x1>;
bits = <0 6>;
};
tsens_base1_backup: base1_backup@440 {
tsens_base1_backup: base1-backup@440 {
reg = <0x440 0x1>;
bits = <0 8>;
};
tsens_s0_p1_backup: s0-p1_backup@441 {
tsens_s0_p1_backup: s0-p1-backup@441 {
reg = <0x441 0x1>;
bits = <0 6>;
};
tsens_s1_p1_backup: s1-p1_backup@442 {
tsens_s1_p1_backup: s1-p1-backup@442 {
reg = <0x441 0x2>;
bits = <6 6>;
};
tsens_s2_p1_backup: s2-p1_backup@442 {
tsens_s2_p1_backup: s2-p1-backup@442 {
reg = <0x442 0x2>;
bits = <4 6>;
};
tsens_s3_p1_backup: s3-p1_backup@443 {
tsens_s3_p1_backup: s3-p1-backup@443 {
reg = <0x443 0x1>;
bits = <2 6>;
};
tsens_s4_p1_backup: s4-p1_backup@444 {
tsens_s4_p1_backup: s4-p1-backup@444 {
reg = <0x444 0x1>;
bits = <0 6>;
};
tsens_s5_p1_backup: s5-p1_backup@444 {
tsens_s5_p1_backup: s5-p1-backup@444 {
reg = <0x444 0x2>;
bits = <6 6>;
};
tsens_s6_p1_backup: s6-p1_backup@445 {
tsens_s6_p1_backup: s6-p1-backup@445 {
reg = <0x445 0x2>;
bits = <4 6>;
};
tsens_s7_p1_backup: s7-p1_backup@446 {
tsens_s7_p1_backup: s7-p1-backup@446 {
reg = <0x446 0x1>;
bits = <2 6>;
};
tsens_use_backup: use_backup@447 {
tsens_use_backup: use-backup@447 {
reg = <0x447 0x1>;
bits = <5 3>;
};
tsens_s8_p1_backup: s8-p1_backup@448 {
tsens_s8_p1_backup: s8-p1-backup@448 {
reg = <0x448 0x1>;
bits = <0 6>;
};
tsens_s9_p1_backup: s9-p1_backup@448 {
tsens_s9_p1_backup: s9-p1-backup@448 {
reg = <0x448 0x2>;
bits = <6 6>;
};
tsens_s10_p1_backup: s10_p1_backup@449 {
tsens_s10_p1_backup: s10-p1-backup@449 {
reg = <0x449 0x2>;
bits = <4 6>;
};
tsens_base2_backup: base2_backup@44a {
tsens_base2_backup: base2-backup@44a {
reg = <0x44a 0x2>;
bits = <2 8>;
};
tsens_s0_p2_backup: s0-p2_backup@44b {
tsens_s0_p2_backup: s0-p2-backup@44b {
reg = <0x44b 0x3>;
bits = <2 6>;
};
tsens_s1_p2_backup: s1-p2_backup@44c {
tsens_s1_p2_backup: s1-p2-backup@44c {
reg = <0x44c 0x1>;
bits = <0 6>;
};
tsens_s2_p2_backup: s2-p2_backup@44c {
tsens_s2_p2_backup: s2-p2-backup@44c {
reg = <0x44c 0x2>;
bits = <6 6>;
};
tsens_s3_p2_backup: s3-p2_backup@44d {
tsens_s3_p2_backup: s3-p2-backup@44d {
reg = <0x44d 0x2>;
bits = <4 6>;
};
tsens_s4_p2_backup: s4-p2_backup@44e {
tsens_s4_p2_backup: s4-p2-backup@44e {
reg = <0x44e 0x1>;
bits = <2 6>;
};

19
arch/arm/boot/dts/qcom/qcom-ipq4018-ap120c-ac.dtsi
View File

@@ -166,16 +166,19 @@ partition@170000 {
label = "ART";
reg = <0x00170000 0x00010000>;
read-only;
compatible = "nvmem-cells";
#address-cells = <1>;
#size-cells = <1>;
precal_art_1000: precal@1000 {
reg = <0x1000 0x2f20>;
};
nvmem-layout {
compatible = "fixed-layout";
#address-cells = <1>;
#size-cells = <1>;
precal_art_5000: precal@5000 {
reg = <0x5000 0x2f20>;
precal_art_1000: precal@1000 {
reg = <0x1000 0x2f20>;
};
precal_art_5000: precal@5000 {
reg = <0x5000 0x2f20>;
};
};
};

2
arch/arm/boot/dts/qcom/qcom-ipq4018-jalapeno.dts
View File

@@ -25,7 +25,7 @@ mdc-pins {
};
};
serial_pins: serial-state{
serial_pins: serial-state {
pins = "gpio60", "gpio61";
function = "blsp_uart0";
bias-disable;

10
arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi
View File

@@ -47,7 +47,7 @@ cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a7";
enable-method = "qcom,kpss-acc-v2";
next-level-cache = <&L2>;
next-level-cache = <&l2>;
qcom,acc = <&acc0>;
qcom,saw = <&saw0>;
reg = <0x0>;
@@ -61,7 +61,7 @@ cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a7";
enable-method = "qcom,kpss-acc-v2";
next-level-cache = <&L2>;
next-level-cache = <&l2>;
qcom,acc = <&acc1>;
qcom,saw = <&saw1>;
reg = <0x1>;
@@ -75,7 +75,7 @@ cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a7";
enable-method = "qcom,kpss-acc-v2";
next-level-cache = <&L2>;
next-level-cache = <&l2>;
qcom,acc = <&acc2>;
qcom,saw = <&saw2>;
reg = <0x2>;
@@ -89,7 +89,7 @@ cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a7";
enable-method = "qcom,kpss-acc-v2";
next-level-cache = <&L2>;
next-level-cache = <&l2>;
qcom,acc = <&acc3>;
qcom,saw = <&saw3>;
reg = <0x3>;
@@ -99,7 +99,7 @@ cpu@3 {
operating-points-v2 = <&cpu0_opp_table>;
};
L2: l2-cache {
l2: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;

8
arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi
View File

@@ -27,7 +27,7 @@ cpu0: cpu@0 {
enable-method = "qcom,kpss-acc-v1";
device_type = "cpu";
reg = <0>;
next-level-cache = <&L2>;
next-level-cache = <&l2>;
qcom,acc = <&acc0>;
qcom,saw = <&saw0>;
};
@@ -37,12 +37,12 @@ cpu1: cpu@1 {
enable-method = "qcom,kpss-acc-v1";
device_type = "cpu";
reg = <1>;
next-level-cache = <&L2>;
next-level-cache = <&l2>;
qcom,acc = <&acc1>;
qcom,saw = <&saw1>;
};
L2: l2-cache {
l2: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
@@ -383,7 +383,7 @@ speedbin_efuse: speedbin@c0 {
tsens_calib: calib@400 {
reg = <0x400 0xb>;
};
tsens_calib_backup: calib_backup@410 {
tsens_calib_backup: calib-backup@410 {
reg = <0x410 0xb>;
};
};

4
arch/arm/boot/dts/qcom/qcom-mdm9615.dtsi
View File

@@ -30,7 +30,7 @@ cpu0: cpu@0 {
compatible = "arm,cortex-a5";
reg = <0>;
device_type = "cpu";
next-level-cache = <&L2>;
next-level-cache = <&l2>;
};
};
@@ -61,7 +61,7 @@ soc: soc {
ranges;
compatible = "simple-bus";
L2: cache-controller@2040000 {
l2: cache-controller@2040000 {
compatible = "arm,pl310-cache";
reg = <0x02040000 0x1000>;
arm,data-latency = <2 2 0>;

34
arch/arm/boot/dts/qcom/qcom-msm8226.dtsi
View File

@@ -39,12 +39,12 @@ cpus {
#address-cells = <1>;
#size-cells = <0>;
CPU0: cpu@0 {
cpu0: cpu@0 {
compatible = "arm,cortex-a7";
enable-method = "qcom,msm8226-smp";
device_type = "cpu";
reg = <0>;
next-level-cache = <&L2>;
next-level-cache = <&l2>;
clocks = <&apcs>;
operating-points-v2 = <&cpu_opp_table>;
qcom,acc = <&acc0>;
@@ -52,12 +52,12 @@ CPU0: cpu@0 {
#cooling-cells = <2>;
};
CPU1: cpu@1 {
cpu1: cpu@1 {
compatible = "arm,cortex-a7";
enable-method = "qcom,msm8226-smp";
device_type = "cpu";
reg = <1>;
next-level-cache = <&L2>;
next-level-cache = <&l2>;
clocks = <&apcs>;
operating-points-v2 = <&cpu_opp_table>;
qcom,acc = <&acc1>;
@@ -65,12 +65,12 @@ CPU1: cpu@1 {
#cooling-cells = <2>;
};
CPU2: cpu@2 {
cpu2: cpu@2 {
compatible = "arm,cortex-a7";
enable-method = "qcom,msm8226-smp";
device_type = "cpu";
reg = <2>;
next-level-cache = <&L2>;
next-level-cache = <&l2>;
clocks = <&apcs>;
operating-points-v2 = <&cpu_opp_table>;
qcom,acc = <&acc2>;
@@ -78,12 +78,12 @@ CPU2: cpu@2 {
#cooling-cells = <2>;
};
CPU3: cpu@3 {
cpu3: cpu@3 {
compatible = "arm,cortex-a7";
enable-method = "qcom,msm8226-smp";
device_type = "cpu";
reg = <3>;
next-level-cache = <&L2>;
next-level-cache = <&l2>;
clocks = <&apcs>;
operating-points-v2 = <&cpu_opp_table>;
qcom,acc = <&acc3>;
@@ -91,7 +91,7 @@ CPU3: cpu@3 {
#cooling-cells = <2>;
};
L2: l2-cache {
l2: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
@@ -1264,10 +1264,10 @@ cpu0-thermal {
cooling-maps {
map0 {
trip = <&cpu_alert0>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
@@ -1295,10 +1295,10 @@ cpu1-thermal {
cooling-maps {
map0 {
trip = <&cpu_alert1>;
cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};

6
arch/arm/boot/dts/qcom/qcom-msm8660.dtsi
View File

@@ -22,7 +22,7 @@ cpu@0 {
enable-method = "qcom,gcc-msm8660";
device_type = "cpu";
reg = <0>;
next-level-cache = <&L2>;
next-level-cache = <&l2>;
};
cpu@1 {
@@ -30,10 +30,10 @@ cpu@1 {
enable-method = "qcom,gcc-msm8660";
device_type = "cpu";
reg = <1>;
next-level-cache = <&L2>;
next-level-cache = <&l2>;
};
L2: l2-cache {
l2: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;

6
arch/arm/boot/dts/qcom/qcom-msm8960.dtsi
View File

@@ -25,7 +25,7 @@ cpu@0 {
enable-method = "qcom,kpss-acc-v1";
device_type = "cpu";
reg = <0>;
next-level-cache = <&L2>;
next-level-cache = <&l2>;
qcom,acc = <&acc0>;
qcom,saw = <&saw0>;
};
@@ -35,12 +35,12 @@ cpu@1 {
enable-method = "qcom,kpss-acc-v1";
device_type = "cpu";
reg = <1>;
next-level-cache = <&L2>;
next-level-cache = <&l2>;
qcom,acc = <&acc1>;
qcom,saw = <&saw1>;
};
L2: l2-cache {
l2: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;

2
arch/arm/boot/dts/qcom/qcom-msm8974-lge-nexus5-hammerhead.dts
View File

@@ -167,7 +167,7 @@ &blsp1_i2c3 {
status = "okay";
clock-frequency = <100000>;
avago_apds993@39 {
sensor@39 {
compatible = "avago,apds9930";
reg = <0x39>;
interrupts-extended = <&tlmm 61 IRQ_TYPE_EDGE_FALLING>;

92
arch/arm/boot/dts/qcom/qcom-msm8974.dtsi
View File

@@ -35,51 +35,51 @@ cpus {
#size-cells = <0>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
CPU0: cpu@0 {
cpu0: cpu@0 {
compatible = "qcom,krait";
enable-method = "qcom,kpss-acc-v2";
device_type = "cpu";
reg = <0>;
next-level-cache = <&L2>;
next-level-cache = <&l2>;
qcom,acc = <&acc0>;
qcom,saw = <&saw0>;
cpu-idle-states = <&CPU_SPC>;
cpu-idle-states = <&cpu_spc>;
};
CPU1: cpu@1 {
cpu1: cpu@1 {
compatible = "qcom,krait";
enable-method = "qcom,kpss-acc-v2";
device_type = "cpu";
reg = <1>;
next-level-cache = <&L2>;
next-level-cache = <&l2>;
qcom,acc = <&acc1>;
qcom,saw = <&saw1>;
cpu-idle-states = <&CPU_SPC>;
cpu-idle-states = <&cpu_spc>;
};
CPU2: cpu@2 {
cpu2: cpu@2 {
compatible = "qcom,krait";
enable-method = "qcom,kpss-acc-v2";
device_type = "cpu";
reg = <2>;
next-level-cache = <&L2>;
next-level-cache = <&l2>;
qcom,acc = <&acc2>;
qcom,saw = <&saw2>;
cpu-idle-states = <&CPU_SPC>;
cpu-idle-states = <&cpu_spc>;
};
CPU3: cpu@3 {
cpu3: cpu@3 {
compatible = "qcom,krait";
enable-method = "qcom,kpss-acc-v2";
device_type = "cpu";
reg = <3>;
next-level-cache = <&L2>;
next-level-cache = <&l2>;
qcom,acc = <&acc3>;
qcom,saw = <&saw3>;
cpu-idle-states = <&CPU_SPC>;
cpu-idle-states = <&cpu_spc>;
};
L2: l2-cache {
l2: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-unified;
@@ -87,7 +87,7 @@ L2: l2-cache {
};
idle-states {
CPU_SPC: cpu-spc {
cpu_spc: cpu-spc {
compatible = "qcom,idle-state-spc",
"arm,idle-state";
entry-latency-us = <150>;
@@ -960,7 +960,7 @@ etm@fc33c000 {
clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk";
cpu = <&CPU0>;
cpu = <&cpu0>;
out-ports {
port {
@@ -978,7 +978,7 @@ etm@fc33d000 {
clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk";
cpu = <&CPU1>;
cpu = <&cpu1>;
out-ports {
port {
@@ -996,7 +996,7 @@ etm@fc33e000 {
clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk";
cpu = <&CPU2>;
cpu = <&cpu2>;
out-ports {
port {
@@ -1014,7 +1014,7 @@ etm@fc33f000 {
clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>;
clock-names = "apb_pclk", "atclk";
cpu = <&CPU3>;
cpu = <&cpu3>;
out-ports {
port {
@@ -1299,7 +1299,7 @@ tsens_s9_p1: s9-p1@d8 {
bits = <0 6>;
};
tsens_s10_p1: s10_p1@d8 {
tsens_s10_p1: s10-p1@d8 {
reg = <0xd8 0x2>;
bits = <6 6>;
};
@@ -1359,137 +1359,137 @@ tsens_s9_p2: s9-p2@e1 {
bits = <4 6>;
};
tsens_s10_p2: s10_p2@e2 {
tsens_s10_p2: s10-p2@e2 {
reg = <0xe2 0x2>;
bits = <2 6>;
};
tsens_s5_p2_backup: s5-p2_backup@e3 {
tsens_s5_p2_backup: s5-p2-backup@e3 {
reg = <0xe3 0x2>;
bits = <0 6>;
};
tsens_mode_backup: mode_backup@e3 {
tsens_mode_backup: mode-backup@e3 {
reg = <0xe3 0x1>;
bits = <6 2>;
};
tsens_s6_p2_backup: s6-p2_backup@e4 {
tsens_s6_p2_backup: s6-p2-backup@e4 {
reg = <0xe4 0x1>;
bits = <0 6>;
};
tsens_s7_p2_backup: s7-p2_backup@e4 {
tsens_s7_p2_backup: s7-p2-backup@e4 {
reg = <0xe4 0x2>;
bits = <6 6>;
};
tsens_s8_p2_backup: s8-p2_backup@e5 {
tsens_s8_p2_backup: s8-p2-backup@e5 {
reg = <0xe5 0x2>;
bits = <4 6>;
};
tsens_s9_p2_backup: s9-p2_backup@e6 {
tsens_s9_p2_backup: s9-p2-backup@e6 {
reg = <0xe6 0x2>;
bits = <2 6>;
};
tsens_s10_p2_backup: s10_p2_backup@e7 {
tsens_s10_p2_backup: s10-p2-backup@e7 {
reg = <0xe7 0x1>;
bits = <0 6>;
};
tsens_base1_backup: base1_backup@440 {
tsens_base1_backup: base1-backup@440 {
reg = <0x440 0x1>;
bits = <0 8>;
};
tsens_s0_p1_backup: s0-p1_backup@441 {
tsens_s0_p1_backup: s0-p1-backup@441 {
reg = <0x441 0x1>;
bits = <0 6>;
};
tsens_s1_p1_backup: s1-p1_backup@442 {
tsens_s1_p1_backup: s1-p1-backup@442 {
reg = <0x441 0x2>;
bits = <6 6>;
};
tsens_s2_p1_backup: s2-p1_backup@442 {
tsens_s2_p1_backup: s2-p1-backup@442 {
reg = <0x442 0x2>;
bits = <4 6>;
};
tsens_s3_p1_backup: s3-p1_backup@443 {
tsens_s3_p1_backup: s3-p1-backup@443 {
reg = <0x443 0x1>;
bits = <2 6>;
};
tsens_s4_p1_backup: s4-p1_backup@444 {
tsens_s4_p1_backup: s4-p1-backup@444 {
reg = <0x444 0x1>;
bits = <0 6>;
};
tsens_s5_p1_backup: s5-p1_backup@444 {
tsens_s5_p1_backup: s5-p1-backup@444 {
reg = <0x444 0x2>;
bits = <6 6>;
};
tsens_s6_p1_backup: s6-p1_backup@445 {
tsens_s6_p1_backup: s6-p1-backup@445 {
reg = <0x445 0x2>;
bits = <4 6>;
};
tsens_s7_p1_backup: s7-p1_backup@446 {
tsens_s7_p1_backup: s7-p1-backup@446 {
reg = <0x446 0x1>;
bits = <2 6>;
};
tsens_use_backup: use_backup@447 {
tsens_use_backup: use-backup@447 {
reg = <0x447 0x1>;
bits = <5 3>;
};
tsens_s8_p1_backup: s8-p1_backup@448 {
tsens_s8_p1_backup: s8-p1-backup@448 {
reg = <0x448 0x1>;
bits = <0 6>;
};
tsens_s9_p1_backup: s9-p1_backup@448 {
tsens_s9_p1_backup: s9-p1-backup@448 {
reg = <0x448 0x2>;
bits = <6 6>;
};
tsens_s10_p1_backup: s10_p1_backup@449 {
tsens_s10_p1_backup: s10-p1-backup@449 {
reg = <0x449 0x2>;
bits = <4 6>;
};
tsens_base2_backup: base2_backup@44a {
tsens_base2_backup: base2-backup@44a {
reg = <0x44a 0x2>;
bits = <2 8>;
};
tsens_s0_p2_backup: s0-p2_backup@44b {
tsens_s0_p2_backup: s0-p2-backup@44b {
reg = <0x44b 0x3>;
bits = <2 6>;
};
tsens_s1_p2_backup: s1-p2_backup@44c {
tsens_s1_p2_backup: s1-p2-backup@44c {
reg = <0x44c 0x1>;
bits = <0 6>;
};
tsens_s2_p2_backup: s2-p2_backup@44c {
tsens_s2_p2_backup: s2-p2-backup@44c {
reg = <0x44c 0x2>;
bits = <6 6>;
};
tsens_s3_p2_backup: s3-p2_backup@44d {
tsens_s3_p2_backup: s3-p2-backup@44d {
reg = <0x44d 0x2>;
bits = <4 6>;
};
tsens_s4_p2_backup: s4-p2_backup@44e {
tsens_s4_p2_backup: s4-p2-backup@44e {
reg = <0x44e 0x1>;
bits = <2 6>;
};

1
arch/arm/boot/dts/qcom/qcom-sdx55.dtsi
View File

@@ -437,6 +437,7 @@ pcie_ep: pcie-ep@1c00000 {
phy-names = "pciephy";
max-link-speed = <3>;
num-lanes = <2>;
linux,pci-domain = <0>;
status = "disabled";
};

67
arch/arm/boot/dts/qcom/qcom-sdx65.dtsi
View File

@@ -345,6 +345,7 @@ pcie_ep: pcie-ep@1c00000 {
max-link-speed = <3>;
num-lanes = <2>;
linux,pci-domain = <0>;
status = "disabled";
};
@@ -592,39 +593,39 @@ apps_smmu: iommu@15000000 {
reg = <0x15000000 0x40000>;
#iommu-cells = <2>;
#global-interrupts = <1>;
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;
};
intc: interrupt-controller@17800000 {