From 8bcf94778ed3f5aaf14d2df8b35db76d105ddc89 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 5 Sep 2024 17:46:53 +0200 Subject: [PATCH 1/6] ARM: dts: qcom: drop underscore in node names Underscores should not be used in node names (dtc with W=2 warns about them), so replace them with hyphens. Use also generic name for avago,apds9930 node, because generic naming is favored by Devicetree spec. Functional impact checked with comparing before/after DTBs with dtx_diff and fdtdump. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240905-dts-cleanup-v1-1-f4c5f7b2c8c2@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom/qcom-apq8064.dtsi | 2 +- arch/arm/boot/dts/qcom/qcom-apq8084.dtsi | 58 +++++++++---------- arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi | 2 +- .../qcom-msm8974-lge-nexus5-hammerhead.dts | 2 +- arch/arm/boot/dts/qcom/qcom-msm8974.dtsi | 56 +++++++++--------- 5 files changed, 60 insertions(+), 60 deletions(-) diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi index ac7494ed633e..1bc935d90085 100644 --- a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi @@ -675,7 +675,7 @@ qfprom: efuse@700000 { tsens_calib: calib@404 { reg = <0x404 0x10>; }; - tsens_backup: backup_calib@414 { + tsens_backup: backup-calib@414 { reg = <0x414 0x10>; }; }; diff --git a/arch/arm/boot/dts/qcom/qcom-apq8084.dtsi b/arch/arm/boot/dts/qcom/qcom-apq8084.dtsi index 014e6c5ee889..40dbbf8655f0 100644 --- a/arch/arm/boot/dts/qcom/qcom-apq8084.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-apq8084.dtsi @@ -17,7 +17,7 @@ reserved-memory { #size-cells = <1>; ranges; - smem_mem: smem_region@fa00000 { + smem_mem: smem-region@fa00000 { reg = <0xfa00000 0x200000>; no-map; }; @@ -311,7 +311,7 @@ tsens_s9_p1: s9-p1@d8 { bits = <0 6>; }; - tsens_s10_p1: s10_p1@d8 { + tsens_s10_p1: s10-p1@d8 { reg = <0xd8 0x2>; bits = <6 6>; }; @@ -371,137 +371,137 @@ tsens_s9_p2: s9-p2@e1 { bits = <4 6>; }; - tsens_s10_p2: s10_p2@e2 { + tsens_s10_p2: s10-p2@e2 { reg = <0xe2 0x2>; bits = <2 6>; }; - tsens_s5_p2_backup: s5-p2_backup@e3 { + tsens_s5_p2_backup: s5-p2-backup@e3 { reg = <0xe3 0x2>; bits = <0 6>; }; - tsens_mode_backup: mode_backup@e3 { + tsens_mode_backup: mode-backup@e3 { reg = <0xe3 0x1>; bits = <6 2>; }; - tsens_s6_p2_backup: s6-p2_backup@e4 { + tsens_s6_p2_backup: s6-p2-backup@e4 { reg = <0xe4 0x1>; bits = <0 6>; }; - tsens_s7_p2_backup: s7-p2_backup@e4 { + tsens_s7_p2_backup: s7-p2-backup@e4 { reg = <0xe4 0x2>; bits = <6 6>; }; - tsens_s8_p2_backup: s8-p2_backup@e5 { + tsens_s8_p2_backup: s8-p2-backup@e5 { reg = <0xe5 0x2>; bits = <4 6>; }; - tsens_s9_p2_backup: s9-p2_backup@e6 { + tsens_s9_p2_backup: s9-p2-backup@e6 { reg = <0xe6 0x2>; bits = <2 6>; }; - tsens_s10_p2_backup: s10_p2_backup@e7 { + tsens_s10_p2_backup: s10-p2-backup@e7 { reg = <0xe7 0x1>; bits = <0 6>; }; - tsens_base1_backup: base1_backup@440 { + tsens_base1_backup: base1-backup@440 { reg = <0x440 0x1>; bits = <0 8>; }; - tsens_s0_p1_backup: s0-p1_backup@441 { + tsens_s0_p1_backup: s0-p1-backup@441 { reg = <0x441 0x1>; bits = <0 6>; }; - tsens_s1_p1_backup: s1-p1_backup@442 { + tsens_s1_p1_backup: s1-p1-backup@442 { reg = <0x441 0x2>; bits = <6 6>; }; - tsens_s2_p1_backup: s2-p1_backup@442 { + tsens_s2_p1_backup: s2-p1-backup@442 { reg = <0x442 0x2>; bits = <4 6>; }; - tsens_s3_p1_backup: s3-p1_backup@443 { + tsens_s3_p1_backup: s3-p1-backup@443 { reg = <0x443 0x1>; bits = <2 6>; }; - tsens_s4_p1_backup: s4-p1_backup@444 { + tsens_s4_p1_backup: s4-p1-backup@444 { reg = <0x444 0x1>; bits = <0 6>; }; - tsens_s5_p1_backup: s5-p1_backup@444 { + tsens_s5_p1_backup: s5-p1-backup@444 { reg = <0x444 0x2>; bits = <6 6>; }; - tsens_s6_p1_backup: s6-p1_backup@445 { + tsens_s6_p1_backup: s6-p1-backup@445 { reg = <0x445 0x2>; bits = <4 6>; }; - tsens_s7_p1_backup: s7-p1_backup@446 { + tsens_s7_p1_backup: s7-p1-backup@446 { reg = <0x446 0x1>; bits = <2 6>; }; - tsens_use_backup: use_backup@447 { + tsens_use_backup: use-backup@447 { reg = <0x447 0x1>; bits = <5 3>; }; - tsens_s8_p1_backup: s8-p1_backup@448 { + tsens_s8_p1_backup: s8-p1-backup@448 { reg = <0x448 0x1>; bits = <0 6>; }; - tsens_s9_p1_backup: s9-p1_backup@448 { + tsens_s9_p1_backup: s9-p1-backup@448 { reg = <0x448 0x2>; bits = <6 6>; }; - tsens_s10_p1_backup: s10_p1_backup@449 { + tsens_s10_p1_backup: s10-p1-backup@449 { reg = <0x449 0x2>; bits = <4 6>; }; - tsens_base2_backup: base2_backup@44a { + tsens_base2_backup: base2-backup@44a { reg = <0x44a 0x2>; bits = <2 8>; }; - tsens_s0_p2_backup: s0-p2_backup@44b { + tsens_s0_p2_backup: s0-p2-backup@44b { reg = <0x44b 0x3>; bits = <2 6>; }; - tsens_s1_p2_backup: s1-p2_backup@44c { + tsens_s1_p2_backup: s1-p2-backup@44c { reg = <0x44c 0x1>; bits = <0 6>; }; - tsens_s2_p2_backup: s2-p2_backup@44c { + tsens_s2_p2_backup: s2-p2-backup@44c { reg = <0x44c 0x2>; bits = <6 6>; }; - tsens_s3_p2_backup: s3-p2_backup@44d { + tsens_s3_p2_backup: s3-p2-backup@44d { reg = <0x44d 0x2>; bits = <4 6>; }; - tsens_s4_p2_backup: s4-p2_backup@44e { + tsens_s4_p2_backup: s4-p2-backup@44e { reg = <0x44e 0x1>; bits = <2 6>; }; diff --git a/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi index 759a59c2bdbc..0f02f59c282a 100644 --- a/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi @@ -383,7 +383,7 @@ speedbin_efuse: speedbin@c0 { tsens_calib: calib@400 { reg = <0x400 0xb>; }; - tsens_calib_backup: calib_backup@410 { + tsens_calib_backup: calib-backup@410 { reg = <0x410 0xb>; }; }; diff --git a/arch/arm/boot/dts/qcom/qcom-msm8974-lge-nexus5-hammerhead.dts b/arch/arm/boot/dts/qcom/qcom-msm8974-lge-nexus5-hammerhead.dts index fdb6e22986cf..261044fdfee8 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8974-lge-nexus5-hammerhead.dts +++ b/arch/arm/boot/dts/qcom/qcom-msm8974-lge-nexus5-hammerhead.dts @@ -167,7 +167,7 @@ &blsp1_i2c3 { status = "okay"; clock-frequency = <100000>; - avago_apds993@39 { + sensor@39 { compatible = "avago,apds9930"; reg = <0x39>; interrupts-extended = <&tlmm 61 IRQ_TYPE_EDGE_FALLING>; diff --git a/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi index 1bd87170252d..742d2104b4fe 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi @@ -1299,7 +1299,7 @@ tsens_s9_p1: s9-p1@d8 { bits = <0 6>; }; - tsens_s10_p1: s10_p1@d8 { + tsens_s10_p1: s10-p1@d8 { reg = <0xd8 0x2>; bits = <6 6>; }; @@ -1359,137 +1359,137 @@ tsens_s9_p2: s9-p2@e1 { bits = <4 6>; }; - tsens_s10_p2: s10_p2@e2 { + tsens_s10_p2: s10-p2@e2 { reg = <0xe2 0x2>; bits = <2 6>; }; - tsens_s5_p2_backup: s5-p2_backup@e3 { + tsens_s5_p2_backup: s5-p2-backup@e3 { reg = <0xe3 0x2>; bits = <0 6>; }; - tsens_mode_backup: mode_backup@e3 { + tsens_mode_backup: mode-backup@e3 { reg = <0xe3 0x1>; bits = <6 2>; }; - tsens_s6_p2_backup: s6-p2_backup@e4 { + tsens_s6_p2_backup: s6-p2-backup@e4 { reg = <0xe4 0x1>; bits = <0 6>; }; - tsens_s7_p2_backup: s7-p2_backup@e4 { + tsens_s7_p2_backup: s7-p2-backup@e4 { reg = <0xe4 0x2>; bits = <6 6>; }; - tsens_s8_p2_backup: s8-p2_backup@e5 { + tsens_s8_p2_backup: s8-p2-backup@e5 { reg = <0xe5 0x2>; bits = <4 6>; }; - tsens_s9_p2_backup: s9-p2_backup@e6 { + tsens_s9_p2_backup: s9-p2-backup@e6 { reg = <0xe6 0x2>; bits = <2 6>; }; - tsens_s10_p2_backup: s10_p2_backup@e7 { + tsens_s10_p2_backup: s10-p2-backup@e7 { reg = <0xe7 0x1>; bits = <0 6>; }; - tsens_base1_backup: base1_backup@440 { + tsens_base1_backup: base1-backup@440 { reg = <0x440 0x1>; bits = <0 8>; }; - tsens_s0_p1_backup: s0-p1_backup@441 { + tsens_s0_p1_backup: s0-p1-backup@441 { reg = <0x441 0x1>; bits = <0 6>; }; - tsens_s1_p1_backup: s1-p1_backup@442 { + tsens_s1_p1_backup: s1-p1-backup@442 { reg = <0x441 0x2>; bits = <6 6>; }; - tsens_s2_p1_backup: s2-p1_backup@442 { + tsens_s2_p1_backup: s2-p1-backup@442 { reg = <0x442 0x2>; bits = <4 6>; }; - tsens_s3_p1_backup: s3-p1_backup@443 { + tsens_s3_p1_backup: s3-p1-backup@443 { reg = <0x443 0x1>; bits = <2 6>; }; - tsens_s4_p1_backup: s4-p1_backup@444 { + tsens_s4_p1_backup: s4-p1-backup@444 { reg = <0x444 0x1>; bits = <0 6>; }; - tsens_s5_p1_backup: s5-p1_backup@444 { + tsens_s5_p1_backup: s5-p1-backup@444 { reg = <0x444 0x2>; bits = <6 6>; }; - tsens_s6_p1_backup: s6-p1_backup@445 { + tsens_s6_p1_backup: s6-p1-backup@445 { reg = <0x445 0x2>; bits = <4 6>; }; - tsens_s7_p1_backup: s7-p1_backup@446 { + tsens_s7_p1_backup: s7-p1-backup@446 { reg = <0x446 0x1>; bits = <2 6>; }; - tsens_use_backup: use_backup@447 { + tsens_use_backup: use-backup@447 { reg = <0x447 0x1>; bits = <5 3>; }; - tsens_s8_p1_backup: s8-p1_backup@448 { + tsens_s8_p1_backup: s8-p1-backup@448 { reg = <0x448 0x1>; bits = <0 6>; }; - tsens_s9_p1_backup: s9-p1_backup@448 { + tsens_s9_p1_backup: s9-p1-backup@448 { reg = <0x448 0x2>; bits = <6 6>; }; - tsens_s10_p1_backup: s10_p1_backup@449 { + tsens_s10_p1_backup: s10-p1-backup@449 { reg = <0x449 0x2>; bits = <4 6>; }; - tsens_base2_backup: base2_backup@44a { + tsens_base2_backup: base2-backup@44a { reg = <0x44a 0x2>; bits = <2 8>; }; - tsens_s0_p2_backup: s0-p2_backup@44b { + tsens_s0_p2_backup: s0-p2-backup@44b { reg = <0x44b 0x3>; bits = <2 6>; }; - tsens_s1_p2_backup: s1-p2_backup@44c { + tsens_s1_p2_backup: s1-p2-backup@44c { reg = <0x44c 0x1>; bits = <0 6>; }; - tsens_s2_p2_backup: s2-p2_backup@44c { + tsens_s2_p2_backup: s2-p2-backup@44c { reg = <0x44c 0x2>; bits = <6 6>; }; - tsens_s3_p2_backup: s3-p2_backup@44d { + tsens_s3_p2_backup: s3-p2-backup@44d { reg = <0x44d 0x2>; bits = <4 6>; }; - tsens_s4_p2_backup: s4-p2_backup@44e { + tsens_s4_p2_backup: s4-p2-backup@44e { reg = <0x44e 0x1>; bits = <2 6>; }; From 8fefd116273e9e94d7478eef9f483c3eecdc7d1c Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 5 Sep 2024 17:46:54 +0200 Subject: [PATCH 2/6] ARM: dts: qcom: minor whitespace cleanup The DTS code coding style expects exactly one space around '=' or '{' characters. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20240905-dts-cleanup-v1-2-f4c5f7b2c8c2@linaro.org Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/qcom-ipq4018-jalapeno.dts | 2 +- arch/arm/boot/dts/qcom/qcom-sdx65.dtsi | 66 +++++++++---------- 2 files changed, 34 insertions(+), 34 deletions(-) diff --git a/arch/arm/boot/dts/qcom/qcom-ipq4018-jalapeno.dts b/arch/arm/boot/dts/qcom/qcom-ipq4018-jalapeno.dts index ac3b30072a22..6640ea7b6acb 100644 --- a/arch/arm/boot/dts/qcom/qcom-ipq4018-jalapeno.dts +++ b/arch/arm/boot/dts/qcom/qcom-ipq4018-jalapeno.dts @@ -25,7 +25,7 @@ mdc-pins { }; }; - serial_pins: serial-state{ + serial_pins: serial-state { pins = "gpio60", "gpio61"; function = "blsp_uart0"; bias-disable; diff --git a/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi index a949454212e9..9354896da6e6 100644 --- a/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi @@ -592,39 +592,39 @@ apps_smmu: iommu@15000000 { reg = <0x15000000 0x40000>; #iommu-cells = <2>; #global-interrupts = <1>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; }; intc: interrupt-controller@17800000 { From 2014756b70d8a77fcac6fc5ce51e5dfca505a4e9 Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Wed, 28 Aug 2024 21:16:17 +0530 Subject: [PATCH 3/6] ARM: dts: qcom: sdx55: Add 'linux,pci-domain' to PCIe EP controller node 'linux,pci-domain' property provides the PCI domain number for the PCI endpoint controllers in a SoC. If this property is not present, then an unstable (across boots) unique number will be assigned. Use this property to specify the domain number based on the actual hardware instance of the PCI endpoint controllers in SDX55 SoC. Reviewed-by: Konrad Dybcio Signed-off-by: Manivannan Sadhasivam Link: https://lore.kernel.org/r/20240828-pci-qcom-hotplug-v4-7-263a385fbbcb@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom/qcom-sdx55.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi index 68fa5859d263..d0f6120b665d 100644 --- a/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi @@ -437,6 +437,7 @@ pcie_ep: pcie-ep@1c00000 { phy-names = "pciephy"; max-link-speed = <3>; num-lanes = <2>; + linux,pci-domain = <0>; status = "disabled"; }; From 46cc68727f4b9155b3d21de2f2ed9c754a9c7c4f Mon Sep 17 00:00:00 2001 From: Manivannan Sadhasivam Date: Wed, 28 Aug 2024 21:16:18 +0530 Subject: [PATCH 4/6] ARM: dts: qcom: sdx65: Add 'linux,pci-domain' to PCIe EP controller node 'linux,pci-domain' property provides the PCI domain number for the PCI endpoint controllers in a SoC. If this property is not present, then an unstable (across boots) unique number will be assigned. Use this property to specify the domain number based on the actual hardware instance of the PCI endpoint controllers in SDX65 SoC. Reviewed-by: Konrad Dybcio Signed-off-by: Manivannan Sadhasivam Link: https://lore.kernel.org/r/20240828-pci-qcom-hotplug-v4-8-263a385fbbcb@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom/qcom-sdx65.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi index 9354896da6e6..3bc67bb8c1eb 100644 --- a/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi @@ -345,6 +345,7 @@ pcie_ep: pcie-ep@1c00000 { max-link-speed = <3>; num-lanes = <2>; + linux,pci-domain = <0>; status = "disabled"; }; From 7b49c9cf4b77a69f03297f515c89e94f21c9b1c0 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Tue, 22 Oct 2024 17:47:43 +0200 Subject: [PATCH 5/6] ARM: dts: qcom: change labels to lower-case DTS coding style expects labels to be lowercase. No functional impact. Verified with comparing decompiled DTB (dtx_diff and fdtdump+diff). Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20241022-dts-qcom-label-v3-18-0505bc7d2c56@linaro.org Signed-off-by: Bjorn Andersson --- arch/arm/boot/dts/qcom/qcom-apq8064.dtsi | 36 ++++++++++++------------ arch/arm/boot/dts/qcom/qcom-apq8084.dtsi | 20 ++++++------- arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi | 10 +++---- arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi | 6 ++-- arch/arm/boot/dts/qcom/qcom-mdm9615.dtsi | 4 +-- arch/arm/boot/dts/qcom/qcom-msm8226.dtsi | 34 +++++++++++----------- arch/arm/boot/dts/qcom/qcom-msm8660.dtsi | 6 ++-- arch/arm/boot/dts/qcom/qcom-msm8960.dtsi | 6 ++-- arch/arm/boot/dts/qcom/qcom-msm8974.dtsi | 36 ++++++++++++------------ 9 files changed, 79 insertions(+), 79 deletions(-) diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi index 1bc935d90085..5f1a6b4b7644 100644 --- a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi @@ -36,58 +36,58 @@ cpus { #address-cells = <1>; #size-cells = <0>; - CPU0: cpu@0 { + cpu0: cpu@0 { compatible = "qcom,krait"; enable-method = "qcom,kpss-acc-v1"; device_type = "cpu"; reg = <0>; - next-level-cache = <&L2>; + next-level-cache = <&l2>; qcom,acc = <&acc0>; qcom,saw = <&saw0>; - cpu-idle-states = <&CPU_SPC>; + cpu-idle-states = <&cpu_spc>; }; - CPU1: cpu@1 { + cpu1: cpu@1 { compatible = "qcom,krait"; enable-method = "qcom,kpss-acc-v1"; device_type = "cpu"; reg = <1>; - next-level-cache = <&L2>; + next-level-cache = <&l2>; qcom,acc = <&acc1>; qcom,saw = <&saw1>; - cpu-idle-states = <&CPU_SPC>; + cpu-idle-states = <&cpu_spc>; }; - CPU2: cpu@2 { + cpu2: cpu@2 { compatible = "qcom,krait"; enable-method = "qcom,kpss-acc-v1"; device_type = "cpu"; reg = <2>; - next-level-cache = <&L2>; + next-level-cache = <&l2>; qcom,acc = <&acc2>; qcom,saw = <&saw2>; - cpu-idle-states = <&CPU_SPC>; + cpu-idle-states = <&cpu_spc>; }; - CPU3: cpu@3 { + cpu3: cpu@3 { compatible = "qcom,krait"; enable-method = "qcom,kpss-acc-v1"; device_type = "cpu"; reg = <3>; - next-level-cache = <&L2>; + next-level-cache = <&l2>; qcom,acc = <&acc3>; qcom,saw = <&saw3>; - cpu-idle-states = <&CPU_SPC>; + cpu-idle-states = <&cpu_spc>; }; - L2: l2-cache { + l2: l2-cache { compatible = "cache"; cache-level = <2>; cache-unified; }; idle-states { - CPU_SPC: cpu-spc { + cpu_spc: cpu-spc { compatible = "qcom,idle-state-spc", "arm,idle-state"; entry-latency-us = <400>; @@ -1625,7 +1625,7 @@ etm@1a1c000 { clocks = <&rpmcc RPM_QDSS_CLK>; clock-names = "apb_pclk"; - cpu = <&CPU0>; + cpu = <&cpu0>; out-ports { port { @@ -1643,7 +1643,7 @@ etm@1a1d000 { clocks = <&rpmcc RPM_QDSS_CLK>; clock-names = "apb_pclk"; - cpu = <&CPU1>; + cpu = <&cpu1>; out-ports { port { @@ -1661,7 +1661,7 @@ etm@1a1e000 { clocks = <&rpmcc RPM_QDSS_CLK>; clock-names = "apb_pclk"; - cpu = <&CPU2>; + cpu = <&cpu2>; out-ports { port { @@ -1679,7 +1679,7 @@ etm@1a1f000 { clocks = <&rpmcc RPM_QDSS_CLK>; clock-names = "apb_pclk"; - cpu = <&CPU3>; + cpu = <&cpu3>; out-ports { port { diff --git a/arch/arm/boot/dts/qcom/qcom-apq8084.dtsi b/arch/arm/boot/dts/qcom/qcom-apq8084.dtsi index 40dbbf8655f0..cee0694ef127 100644 --- a/arch/arm/boot/dts/qcom/qcom-apq8084.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-apq8084.dtsi @@ -32,10 +32,10 @@ cpu@0 { compatible = "qcom,krait"; reg = <0>; enable-method = "qcom,kpss-acc-v2"; - next-level-cache = <&L2>; + next-level-cache = <&l2>; qcom,acc = <&acc0>; qcom,saw = <&saw0>; - cpu-idle-states = <&CPU_SPC>; + cpu-idle-states = <&cpu_spc>; }; cpu@1 { @@ -43,10 +43,10 @@ cpu@1 { compatible = "qcom,krait"; reg = <1>; enable-method = "qcom,kpss-acc-v2"; - next-level-cache = <&L2>; + next-level-cache = <&l2>; qcom,acc = <&acc1>; qcom,saw = <&saw1>; - cpu-idle-states = <&CPU_SPC>; + cpu-idle-states = <&cpu_spc>; }; cpu@2 { @@ -54,10 +54,10 @@ cpu@2 { compatible = "qcom,krait"; reg = <2>; enable-method = "qcom,kpss-acc-v2"; - next-level-cache = <&L2>; + next-level-cache = <&l2>; qcom,acc = <&acc2>; qcom,saw = <&saw2>; - cpu-idle-states = <&CPU_SPC>; + cpu-idle-states = <&cpu_spc>; }; cpu@3 { @@ -65,13 +65,13 @@ cpu@3 { compatible = "qcom,krait"; reg = <3>; enable-method = "qcom,kpss-acc-v2"; - next-level-cache = <&L2>; + next-level-cache = <&l2>; qcom,acc = <&acc3>; qcom,saw = <&saw3>; - cpu-idle-states = <&CPU_SPC>; + cpu-idle-states = <&cpu_spc>; }; - L2: l2-cache { + l2: l2-cache { compatible = "cache"; cache-level = <2>; cache-unified; @@ -79,7 +79,7 @@ L2: l2-cache { }; idle-states { - CPU_SPC: cpu-spc { + cpu_spc: cpu-spc { compatible = "qcom,idle-state-spc", "arm,idle-state"; entry-latency-us = <150>; diff --git a/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi index 56415ab34083..06b20c196faf 100644 --- a/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi @@ -47,7 +47,7 @@ cpu@0 { device_type = "cpu"; compatible = "arm,cortex-a7"; enable-method = "qcom,kpss-acc-v2"; - next-level-cache = <&L2>; + next-level-cache = <&l2>; qcom,acc = <&acc0>; qcom,saw = <&saw0>; reg = <0x0>; @@ -61,7 +61,7 @@ cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a7"; enable-method = "qcom,kpss-acc-v2"; - next-level-cache = <&L2>; + next-level-cache = <&l2>; qcom,acc = <&acc1>; qcom,saw = <&saw1>; reg = <0x1>; @@ -75,7 +75,7 @@ cpu@2 { device_type = "cpu"; compatible = "arm,cortex-a7"; enable-method = "qcom,kpss-acc-v2"; - next-level-cache = <&L2>; + next-level-cache = <&l2>; qcom,acc = <&acc2>; qcom,saw = <&saw2>; reg = <0x2>; @@ -89,7 +89,7 @@ cpu@3 { device_type = "cpu"; compatible = "arm,cortex-a7"; enable-method = "qcom,kpss-acc-v2"; - next-level-cache = <&L2>; + next-level-cache = <&l2>; qcom,acc = <&acc3>; qcom,saw = <&saw3>; reg = <0x3>; @@ -99,7 +99,7 @@ cpu@3 { operating-points-v2 = <&cpu0_opp_table>; }; - L2: l2-cache { + l2: l2-cache { compatible = "cache"; cache-level = <2>; cache-unified; diff --git a/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi index 0f02f59c282a..96e973501535 100644 --- a/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi @@ -27,7 +27,7 @@ cpu0: cpu@0 { enable-method = "qcom,kpss-acc-v1"; device_type = "cpu"; reg = <0>; - next-level-cache = <&L2>; + next-level-cache = <&l2>; qcom,acc = <&acc0>; qcom,saw = <&saw0>; }; @@ -37,12 +37,12 @@ cpu1: cpu@1 { enable-method = "qcom,kpss-acc-v1"; device_type = "cpu"; reg = <1>; - next-level-cache = <&L2>; + next-level-cache = <&l2>; qcom,acc = <&acc1>; qcom,saw = <&saw1>; }; - L2: l2-cache { + l2: l2-cache { compatible = "cache"; cache-level = <2>; cache-unified; diff --git a/arch/arm/boot/dts/qcom/qcom-mdm9615.dtsi b/arch/arm/boot/dts/qcom/qcom-mdm9615.dtsi index 573feb3218c3..7de8d6c55016 100644 --- a/arch/arm/boot/dts/qcom/qcom-mdm9615.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-mdm9615.dtsi @@ -30,7 +30,7 @@ cpu0: cpu@0 { compatible = "arm,cortex-a5"; reg = <0>; device_type = "cpu"; - next-level-cache = <&L2>; + next-level-cache = <&l2>; }; }; @@ -61,7 +61,7 @@ soc: soc { ranges; compatible = "simple-bus"; - L2: cache-controller@2040000 { + l2: cache-controller@2040000 { compatible = "arm,pl310-cache"; reg = <0x02040000 0x1000>; arm,data-latency = <2 2 0>; diff --git a/arch/arm/boot/dts/qcom/qcom-msm8226.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8226.dtsi index 3a685ff7e8cc..64c8ac94f352 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8226.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-msm8226.dtsi @@ -39,12 +39,12 @@ cpus { #address-cells = <1>; #size-cells = <0>; - CPU0: cpu@0 { + cpu0: cpu@0 { compatible = "arm,cortex-a7"; enable-method = "qcom,msm8226-smp"; device_type = "cpu"; reg = <0>; - next-level-cache = <&L2>; + next-level-cache = <&l2>; clocks = <&apcs>; operating-points-v2 = <&cpu_opp_table>; qcom,acc = <&acc0>; @@ -52,12 +52,12 @@ CPU0: cpu@0 { #cooling-cells = <2>; }; - CPU1: cpu@1 { + cpu1: cpu@1 { compatible = "arm,cortex-a7"; enable-method = "qcom,msm8226-smp"; device_type = "cpu"; reg = <1>; - next-level-cache = <&L2>; + next-level-cache = <&l2>; clocks = <&apcs>; operating-points-v2 = <&cpu_opp_table>; qcom,acc = <&acc1>; @@ -65,12 +65,12 @@ CPU1: cpu@1 { #cooling-cells = <2>; }; - CPU2: cpu@2 { + cpu2: cpu@2 { compatible = "arm,cortex-a7"; enable-method = "qcom,msm8226-smp"; device_type = "cpu"; reg = <2>; - next-level-cache = <&L2>; + next-level-cache = <&l2>; clocks = <&apcs>; operating-points-v2 = <&cpu_opp_table>; qcom,acc = <&acc2>; @@ -78,12 +78,12 @@ CPU2: cpu@2 { #cooling-cells = <2>; }; - CPU3: cpu@3 { + cpu3: cpu@3 { compatible = "arm,cortex-a7"; enable-method = "qcom,msm8226-smp"; device_type = "cpu"; reg = <3>; - next-level-cache = <&L2>; + next-level-cache = <&l2>; clocks = <&apcs>; operating-points-v2 = <&cpu_opp_table>; qcom,acc = <&acc3>; @@ -91,7 +91,7 @@ CPU3: cpu@3 { #cooling-cells = <2>; }; - L2: l2-cache { + l2: l2-cache { compatible = "cache"; cache-level = <2>; cache-unified; @@ -1264,10 +1264,10 @@ cpu0-thermal { cooling-maps { map0 { trip = <&cpu_alert0>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; @@ -1295,10 +1295,10 @@ cpu1-thermal { cooling-maps { map0 { trip = <&cpu_alert1>; - cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; diff --git a/arch/arm/boot/dts/qcom/qcom-msm8660.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8660.dtsi index a66c474cd1aa..3f69b98d0041 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8660.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-msm8660.dtsi @@ -22,7 +22,7 @@ cpu@0 { enable-method = "qcom,gcc-msm8660"; device_type = "cpu"; reg = <0>; - next-level-cache = <&L2>; + next-level-cache = <&l2>; }; cpu@1 { @@ -30,10 +30,10 @@ cpu@1 { enable-method = "qcom,gcc-msm8660"; device_type = "cpu"; reg = <1>; - next-level-cache = <&L2>; + next-level-cache = <&l2>; }; - L2: l2-cache { + l2: l2-cache { compatible = "cache"; cache-level = <2>; cache-unified; diff --git a/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi index ebc43c5c6e5f..865fe7cc3951 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-msm8960.dtsi @@ -25,7 +25,7 @@ cpu@0 { enable-method = "qcom,kpss-acc-v1"; device_type = "cpu"; reg = <0>; - next-level-cache = <&L2>; + next-level-cache = <&l2>; qcom,acc = <&acc0>; qcom,saw = <&saw0>; }; @@ -35,12 +35,12 @@ cpu@1 { enable-method = "qcom,kpss-acc-v1"; device_type = "cpu"; reg = <1>; - next-level-cache = <&L2>; + next-level-cache = <&l2>; qcom,acc = <&acc1>; qcom,saw = <&saw1>; }; - L2: l2-cache { + l2: l2-cache { compatible = "cache"; cache-level = <2>; cache-unified; diff --git a/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi index 742d2104b4fe..e3f9c56a778c 100644 --- a/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi @@ -35,51 +35,51 @@ cpus { #size-cells = <0>; interrupts = ; - CPU0: cpu@0 { + cpu0: cpu@0 { compatible = "qcom,krait"; enable-method = "qcom,kpss-acc-v2"; device_type = "cpu"; reg = <0>; - next-level-cache = <&L2>; + next-level-cache = <&l2>; qcom,acc = <&acc0>; qcom,saw = <&saw0>; - cpu-idle-states = <&CPU_SPC>; + cpu-idle-states = <&cpu_spc>; }; - CPU1: cpu@1 { + cpu1: cpu@1 { compatible = "qcom,krait"; enable-method = "qcom,kpss-acc-v2"; device_type = "cpu"; reg = <1>; - next-level-cache = <&L2>; + next-level-cache = <&l2>; qcom,acc = <&acc1>; qcom,saw = <&saw1>; - cpu-idle-states = <&CPU_SPC>; + cpu-idle-states = <&cpu_spc>; }; - CPU2: cpu@2 { + cpu2: cpu@2 { compatible = "qcom,krait"; enable-method = "qcom,kpss-acc-v2"; device_type = "cpu"; reg = <2>; - next-level-cache = <&L2>; + next-level-cache = <&l2>; qcom,acc = <&acc2>; qcom,saw = <&saw2>; - cpu-idle-states = <&CPU_SPC>; + cpu-idle-states = <&cpu_spc>; }; - CPU3: cpu@3 { + cpu3: cpu@3 { compatible = "qcom,krait"; enable-method = "qcom,kpss-acc-v2"; device_type = "cpu"; reg = <3>; - next-level-cache = <&L2>; + next-level-cache = <&l2>; qcom,acc = <&acc3>; qcom,saw = <&saw3>; - cpu-idle-states = <&CPU_SPC>; + cpu-idle-states = <&cpu_spc>; }; - L2: l2-cache { + l2: l2-cache { compatible = "cache"; cache-level = <2>; cache-unified; @@ -87,7 +87,7 @@ L2: l2-cache { }; idle-states { - CPU_SPC: cpu-spc { + cpu_spc: cpu-spc { compatible = "qcom,idle-state-spc", "arm,idle-state"; entry-latency-us = <150>; @@ -960,7 +960,7 @@ etm@fc33c000 { clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; clock-names = "apb_pclk", "atclk"; - cpu = <&CPU0>; + cpu = <&cpu0>; out-ports { port { @@ -978,7 +978,7 @@ etm@fc33d000 { clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; clock-names = "apb_pclk", "atclk"; - cpu = <&CPU1>; + cpu = <&cpu1>; out-ports { port { @@ -996,7 +996,7 @@ etm@fc33e000 { clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; clock-names = "apb_pclk", "atclk"; - cpu = <&CPU2>; + cpu = <&cpu2>; out-ports { port { @@ -1014,7 +1014,7 @@ etm@fc33f000 { clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; clock-names = "apb_pclk", "atclk"; - cpu = <&CPU3>; + cpu = <&cpu3>; out-ports { port { From ef4b38462e627f58bc929fc502e601dd396f1ae2 Mon Sep 17 00:00:00 2001 From: Rosen Penev Date: Mon, 21 Oct 2024 17:24:44 -0700 Subject: [PATCH 6/6] ARM: dts: qcom: ipq4019: use nvmem-layout nvmem-layout is a more flexible replacement for nvmem-cells. Signed-off-by: Rosen Penev Link: https://lore.kernel.org/r/20241022002444.843484-1-rosenp@gmail.com Signed-off-by: Bjorn Andersson --- .../boot/dts/qcom/qcom-ipq4018-ap120c-ac.dtsi | 19 +++++++++++-------- 1 file changed, 11 insertions(+), 8 deletions(-) diff --git a/arch/arm/boot/dts/qcom/qcom-ipq4018-ap120c-ac.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq4018-ap120c-ac.dtsi index 0d23c03fae33..a6d4390efa7c 100644 --- a/arch/arm/boot/dts/qcom/qcom-ipq4018-ap120c-ac.dtsi +++ b/arch/arm/boot/dts/qcom/qcom-ipq4018-ap120c-ac.dtsi @@ -166,16 +166,19 @@ partition@170000 { label = "ART"; reg = <0x00170000 0x00010000>; read-only; - compatible = "nvmem-cells"; - #address-cells = <1>; - #size-cells = <1>; - precal_art_1000: precal@1000 { - reg = <0x1000 0x2f20>; - }; + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; - precal_art_5000: precal@5000 { - reg = <0x5000 0x2f20>; + precal_art_1000: precal@1000 { + reg = <0x1000 0x2f20>; + }; + + precal_art_5000: precal@5000 { + reg = <0x5000 0x2f20>; + }; }; };