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Merge tag 'renesas-arm-dt-for-v6.1-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into arm/dt

Browse Source 
Renesas ARM DT updates for v6.1

  - SDHI and eMMC support for the R-Car S4-8 SoC and the Spider
    development board,
  - Timer (CMT and TMU) and SPI (MSIOF) support for the R-Car S4-8 SoC,
  - External and GPIO interrupt support for the RZ/G2L and RZ/V2L SoCs,
  - Initial support for the R-Car H3Ne-1.7G (R8A779MB) SoC,
  - SPI DMA support for the RZ/G2UL, RZ/G2L, and RZ/V2L SoCs,
  - Pin control and I2C support for the RZ/V2M SoC and the RZ/V2M
    Evaluation Kit,
  - initial support for the R-Car V3H2 (R8A77980A) SoC and the Condor-I
    development board,
  - Miscellaneous fixes and improvements.

* tag 'renesas-arm-dt-for-v6.1-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: (33 commits)
  arm64: dts: renesas: Add V3H2 Condor-I board support
  arm64: dts: renesas: Add r8a77980a.dtsi
  arm64: dts: renesas: Add condor-common.dtsi
  arm64: dts: renesas: Drop clock-names property from RPC node
  arm64: dts: renesas: r8a779f0: Add MSIOF nodes
  arm64: dts: renesas: r8a774a1: Put I2C aliases to board files
  arm64: dts: renesas: r8a774e1: Rename i2c_dvfs to iic_pmic
  arm64: dts: renesas: r8a779a0: Put I2C aliases to board files
  arm64: dts: renesas: r8a77990: Put I2C aliases to board files
  arm64: dts: renesas: r8a77980: Put I2C aliases to board files
  arm64: dts: renesas: r8a77970: Put I2C aliases to board files
  arm64: dts: renesas: r8a779{51|60|65}: Put I2C aliases to board files
  arm64: dts: renesas: rzv2m evk: Enable i2c
  arm64: dts: renesas: r9a09g011: Add i2c nodes
  arm64: dts: renesas: r9a09g011: Add pinctrl node
  arm64: dts: renesas: r9a07g043: Fix SCI{Rx,Tx} interrupt types
  arm64: dts: renesas: r9a07g054: Fix SCI{Rx,Tx} interrupt types
  arm64: dts: renesas: r9a07g044: Fix SCI{Rx,Tx} interrupt types
  arm64: dts: renesas: r9a07g043: Fix audio clk node names
  arm64: dts: renesas: r9a07g054: Add DMA support to RSPI
  ...

Link: https://lore.kernel.org/r/cover.1662111128.git.geert+renesas@glider.be
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
2022-09-02 12:22:49 +02:00
parent 70fed748cd 6f67580ca9
commit 73bf60ba7c
35 changed files with 1198 additions and 639 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
arch/arm64/boot/dts/renesas/Makefile
View File

@@ -56,6 +56,7 @@ dtb-$(CONFIG_ARCH_R8A77970) += r8a77970-v3msk.dtb
dtb-$(CONFIG_ARCH_R8A77980) += r8a77980-condor.dtb
dtb-$(CONFIG_ARCH_R8A77980) += r8a77980-v3hsk.dtb
dtb-$(CONFIG_ARCH_R8A77980) += r8a77980a-condor-i.dtb
dtb-$(CONFIG_ARCH_R8A77990) += r8a77990-ebisu.dtb

548
arch/arm64/boot/dts/renesas/condor-common.dtsi Normal file
View File

@@ -0,0 +1,548 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the Condor board with R-Car V3H
*
* Copyright (C) 2018 Renesas Electronics Corp.
* Copyright (C) 2018 Cogent Embedded, Inc.
*/
#include <dt-bindings/gpio/gpio.h>
/ {
aliases {
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
i2c3 = &i2c3;
i2c4 = &i2c4;
i2c5 = &i2c5;
serial0 = &scif0;
ethernet0 = &gether;
};
chosen {
stdout-path = "serial0:115200n8";
};
d1_8v: regulator-2 {
compatible = "regulator-fixed";
regulator-name = "D1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
d3_3v: regulator-0 {
compatible = "regulator-fixed";
regulator-name = "D3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
hdmi-out {
compatible = "hdmi-connector";
type = "a";
port {
hdmi_con: endpoint {
remote-endpoint = <&adv7511_out>;
};
};
};
lvds-decoder {
compatible = "thine,thc63lvd1024";
vcc-supply = <&d3_3v>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
thc63lvd1024_in: endpoint {
remote-endpoint = <&lvds0_out>;
};
};
port@2 {
reg = <2>;
thc63lvd1024_out: endpoint {
remote-endpoint = <&adv7511_in>;
};
};
};
};
memory@48000000 {
device_type = "memory";
/* first 128MB is reserved for secure area. */
reg = <0 0x48000000 0 0x78000000>;
};
vddq_vin01: regulator-1 {
compatible = "regulator-fixed";
regulator-name = "VDDQ_VIN01";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
x1_clk: x1-clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <148500000>;
};
};
&canfd {
pinctrl-0 = <&canfd0_pins>;
pinctrl-names = "default";
status = "okay";
channel0 {
status = "okay";
};
};
&csi40 {
status = "okay";
ports {
port@0 {
csi40_in: endpoint {
clock-lanes = <0>;
data-lanes = <1 2 3 4>;
remote-endpoint = <&max9286_out0>;
};
};
};
};
&csi41 {
status = "okay";
ports {
port@0 {
csi41_in: endpoint {
clock-lanes = <0>;
data-lanes = <1 2 3 4>;
remote-endpoint = <&max9286_out1>;
};
};
};
};
&du {
clocks = <&cpg CPG_MOD 724>,
<&x1_clk>;
clock-names = "du.0", "dclkin.0";
status = "okay";
};
&extal_clk {
clock-frequency = <16666666>;
};
&extalr_clk {
clock-frequency = <32768>;
};
&gether {
pinctrl-0 = <&gether_pins>;
pinctrl-names = "default";
phy-mode = "rgmii-id";
phy-handle = <&phy0>;
renesas,no-ether-link;
status = "okay";
phy0: ethernet-phy@0 {
compatible = "ethernet-phy-id0022.1622",
"ethernet-phy-ieee802.3-c22";
rxc-skew-ps = <1500>;
reg = <0>;
interrupt-parent = <&gpio4>;
interrupts = <23 IRQ_TYPE_LEVEL_LOW>;
reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
};
};
&i2c0 {
pinctrl-0 = <&i2c0_pins>;
pinctrl-names = "default";
status = "okay";
clock-frequency = <400000>;
io_expander0: gpio@20 {
compatible = "onnn,pca9654";
reg = <0x20>;
gpio-controller;
#gpio-cells = <2>;
};
io_expander1: gpio@21 {
compatible = "onnn,pca9654";
reg = <0x21>;
gpio-controller;
#gpio-cells = <2>;
};
hdmi@39 {
compatible = "adi,adv7511w";
reg = <0x39>;
interrupt-parent = <&gpio1>;
interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
avdd-supply = <&d1_8v>;
dvdd-supply = <&d1_8v>;
pvdd-supply = <&d1_8v>;
bgvdd-supply = <&d1_8v>;
dvdd-3v-supply = <&d3_3v>;
adi,input-depth = <8>;
adi,input-colorspace = "rgb";
adi,input-clock = "1x";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
adv7511_in: endpoint {
remote-endpoint = <&thc63lvd1024_out>;
};
};
port@1 {
reg = <1>;
adv7511_out: endpoint {
remote-endpoint = <&hdmi_con>;
};
};
};
};
};
&i2c1 {
pinctrl-0 = <&i2c1_pins>;
pinctrl-names = "default";
status = "okay";
clock-frequency = <400000>;
gmsl0: gmsl-deserializer@48 {
compatible = "maxim,max9286";
reg = <0x48>;
maxim,gpio-poc = <0 GPIO_ACTIVE_LOW>;
enable-gpios = <&io_expander0 0 GPIO_ACTIVE_HIGH>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
};
port@1 {
reg = <1>;
};
port@2 {
reg = <2>;
};
port@3 {
reg = <3>;
};
port@4 {
reg = <4>;
max9286_out0: endpoint {
clock-lanes = <0>;
data-lanes = <1 2 3 4>;
remote-endpoint = <&csi40_in>;
};
};
};
i2c-mux {
#address-cells = <1>;
#size-cells = <0>;
i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
status = "disabled";
};
i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
status = "disabled";
};
i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
status = "disabled";
};
i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
status = "disabled";
};
};
};
gmsl1: gmsl-deserializer@4a {
compatible = "maxim,max9286";
reg = <0x4a>;
maxim,gpio-poc = <0 GPIO_ACTIVE_LOW>;
enable-gpios = <&io_expander1 0 GPIO_ACTIVE_HIGH>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
};
port@1 {
reg = <1>;
};
port@2 {
reg = <2>;
};
port@3 {
reg = <3>;
};
port@4 {
reg = <4>;
max9286_out1: endpoint {
clock-lanes = <0>;
data-lanes = <1 2 3 4>;
remote-endpoint = <&csi41_in>;
};
};
};
i2c-mux {
#address-cells = <1>;
#size-cells = <0>;
i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
status = "disabled";
};
i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
status = "disabled";
};
i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
status = "disabled";
};
i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
status = "disabled";
};
};
};
};
&lvds0 {
status = "okay";
ports {
port@1 {
lvds0_out: endpoint {
remote-endpoint = <&thc63lvd1024_in>;
};
};
};
};
&mmc0 {
pinctrl-0 = <&mmc_pins>;
pinctrl-1 = <&mmc_pins>;
pinctrl-names = "default", "state_uhs";
vmmc-supply = <&d3_3v>;
vqmmc-supply = <&vddq_vin01>;
mmc-hs200-1_8v;
bus-width = <8>;
no-sd;
no-sdio;
non-removable;
status = "okay";
};
&pciec {
status = "okay";
};
&pcie_bus_clk {
clock-frequency = <100000000>;
};
&pcie_phy {
status = "okay";
};
&pfc {
canfd0_pins: canfd0 {
groups = "canfd0_data_a";
function = "canfd0";
};
gether_pins: gether {
groups = "gether_mdio_a", "gether_rgmii",
"gether_txcrefclk", "gether_txcrefclk_mega";
function = "gether";
};
i2c0_pins: i2c0 {
groups = "i2c0";
function = "i2c0";
};
i2c1_pins: i2c1 {
groups = "i2c1";
function = "i2c1";
};
mmc_pins: mmc {
groups = "mmc_data8", "mmc_ctrl", "mmc_ds";
function = "mmc";
power-source = <1800>;
};
qspi0_pins: qspi0 {
groups = "qspi0_ctrl", "qspi0_data4";
function = "qspi0";
};
scif0_pins: scif0 {
groups = "scif0_data";
function = "scif0";
};
scif_clk_pins: scif_clk {
groups = "scif_clk_b";
function = "scif_clk";
};
};
&rpc {
pinctrl-0 = <&qspi0_pins>;
pinctrl-names = "default";
status = "okay";
flash@0 {
compatible = "spansion,s25fs512s", "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <50000000>;
spi-rx-bus-width = <4>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
bootparam@0 {
reg = <0x00000000 0x040000>;
read-only;
};
cr7@40000 {
reg = <0x00040000 0x080000>;
read-only;
};
cert_header_sa3@c0000 {
reg = <0x000c0000 0x080000>;
read-only;
};
bl2@140000 {
reg = <0x00140000 0x040000>;
read-only;
};
cert_header_sa6@180000 {
reg = <0x00180000 0x040000>;
read-only;
};
bl31@1c0000 {
reg = <0x001c0000 0x460000>;
read-only;
};
uboot@640000 {
reg = <0x00640000 0x0c0000>;
read-only;
};
uboot-env@700000 {
reg = <0x00700000 0x040000>;
read-only;
};
dtb@740000 {
reg = <0x00740000 0x080000>;
};
kernel@7c0000 {
reg = <0x007c0000 0x1400000>;
};
user@1bc0000 {
reg = <0x01bc0000 0x2440000>;
};
};
};
};
&rwdt {
timeout-sec = <60>;
status = "okay";
};
&scif0 {
pinctrl-0 = <&scif0_pins>, <&scif_clk_pins>;
pinctrl-names = "default";
status = "okay";
};
&scif_clk {
clock-frequency = <14745600>;
};

8
arch/arm64/boot/dts/renesas/ebisu.dtsi
View File

@@ -13,6 +13,14 @@ / {
compatible = "renesas,ebisu";
aliases {
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
i2c3 = &i2c3;
i2c4 = &i2c4;
i2c5 = &i2c5;
i2c6 = &i2c6;
i2c7 = &i2c7;
serial0 = &scif2;
ethernet0 = &avb;
mmc0 = &sdhi3;

8
arch/arm64/boot/dts/renesas/hihope-common.dtsi
View File

@@ -10,6 +10,14 @@
/ {
aliases {
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
i2c3 = &i2c3;
i2c4 = &i2c4;
i2c5 = &i2c5;
i2c6 = &i2c6;
i2c7 = &iic_pmic;
serial0 = &scif2;
serial1 = &hscif0;
mmc0 = &sdhi3;

8
arch/arm64/boot/dts/renesas/r8a774a1-beacon-rzg2m-kit.dts
View File

@@ -14,6 +14,14 @@ / {
compatible = "beacon,beacon-rzg2m", "renesas,r8a774a1";
aliases {
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
i2c3 = &i2c3;
i2c4 = &i2c4;
i2c5 = &i2c5;
i2c6 = &i2c6;
i2c7 = &iic_pmic;
serial0 = &scif2;
serial1 = &hscif0;
serial2 = &hscif1;

12
arch/arm64/boot/dts/renesas/r8a774a1.dtsi
View File

@@ -17,17 +17,6 @@ / {
#address-cells = <2>;
#size-cells = <2>;
aliases {
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
i2c3 = &i2c3;
i2c4 = &i2c4;
i2c5 = &i2c5;
i2c6 = &i2c6;
i2c7 = &iic_pmic;
};
/*
* The external audio clocks are configured as 0 Hz fixed frequency
* clocks by default.
@@ -2334,7 +2323,6 @@ rpc: spi@ee200000 {
reg-names = "regs", "dirmap", "wbuf";
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 917>;
clock-names = "rpc";
power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>;
resets = <&cpg 917>;
#address-cells = <1>;

1
arch/arm64/boot/dts/renesas/r8a774b1.dtsi
View File

@@ -2191,7 +2191,6 @@ rpc: spi@ee200000 {
reg-names = "regs", "dirmap", "wbuf";
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 917>;
clock-names = "rpc";
power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
resets = <&cpg 917>;
#address-cells = <1>;

1
arch/arm64/boot/dts/renesas/r8a774c0.dtsi
View File

@@ -1671,7 +1671,6 @@ rpc: spi@ee200000 {
reg-names = "regs", "dirmap", "wbuf";
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 917>;
clock-names = "rpc";
power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>;
resets = <&cpg 917>;
#address-cells = <1>;

3
arch/arm64/boot/dts/renesas/r8a774e1.dtsi
View File

@@ -769,7 +769,7 @@ i2c6: i2c@e66e8000 {
status = "disabled";
};
i2c_dvfs: i2c@e60b0000 {
iic_pmic: i2c@e60b0000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "renesas,iic-r8a774e1",
@@ -2423,7 +2423,6 @@ rpc: spi@ee200000 {
reg-names = "regs", "dirmap", "wbuf";
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 917>;
clock-names = "rpc";
power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>;
resets = <&cpg 917>;
#address-cells = <1>;

11
arch/arm64/boot/dts/renesas/r8a77951.dtsi
View File

@@ -21,17 +21,6 @@ / {
#address-cells = <2>;
#size-cells = <2>;
aliases {
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
i2c3 = &i2c3;
i2c4 = &i2c4;
i2c5 = &i2c5;
i2c6 = &i2c6;
i2c7 = &i2c_dvfs;
};
/*
* The external audio clocks are configured as 0 Hz fixed frequency
* clocks by default.

11
arch/arm64/boot/dts/renesas/r8a77960.dtsi
View File

@@ -16,17 +16,6 @@ / {
#address-cells = <2>;
#size-cells = <2>;
aliases {
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
i2c3 = &i2c3;
i2c4 = &i2c4;
i2c5 = &i2c5;
i2c6 = &i2c6;
i2c7 = &i2c_dvfs;
};
/*
* The external audio clocks are configured as 0 Hz fixed frequency
* clocks by default.

11
arch/arm64/boot/dts/renesas/r8a77965.dtsi
View File

@@ -21,17 +21,6 @@ / {
#address-cells = <2>;
#size-cells = <2>;
aliases {
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
i2c3 = &i2c3;
i2c4 = &i2c4;
i2c5 = &i2c5;
i2c6 = &i2c6;
i2c7 = &i2c_dvfs;
};
/*
* The external audio clocks are configured as 0 Hz fixed frequency
* clocks by default.

5
arch/arm64/boot/dts/renesas/r8a77970-eagle.dts
View File

@@ -15,6 +15,11 @@ / {
compatible = "renesas,eagle", "renesas,r8a77970";
aliases {
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
i2c3 = &i2c3;
i2c4 = &i2c4;
serial0 = &scif0;
ethernet0 = &avb;
};

5
arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts
View File

@@ -15,6 +15,11 @@ / {
compatible = "renesas,v3msk", "renesas,r8a77970";
aliases {
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
i2c3 = &i2c3;
i2c4 = &i2c4;
serial0 = &scif0;
};

9
arch/arm64/boot/dts/renesas/r8a77970.dtsi
View File

@@ -16,14 +16,6 @@ / {
#address-cells = <2>;
#size-cells = <2>;
aliases {
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
i2c3 = &i2c3;
i2c4 = &i2c4;
};
/* External CAN clock - to be overridden by boards that provide it */
can_clk: can {
compatible = "fixed-clock";
@@ -1053,7 +1045,6 @@ rpc: spi@ee200000 {
reg-names = "regs", "dirmap", "wbuf";
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 917>;
clock-names = "rpc";
power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
resets = <&cpg 917>;
#address-cells = <1>;

534
arch/arm64/boot/dts/renesas/r8a77980-condor.dts
View File

@@ -8,541 +8,9 @@
/dts-v1/;
#include "r8a77980.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include "condor-common.dtsi"
/ {
model = "Renesas Condor board based on r8a77980";
compatible = "renesas,condor", "renesas,r8a77980";
aliases {
serial0 = &scif0;
ethernet0 = &gether;
};
chosen {
stdout-path = "serial0:115200n8";
};
d1_8v: regulator-2 {
compatible = "regulator-fixed";
regulator-name = "D1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
d3_3v: regulator-0 {
compatible = "regulator-fixed";
regulator-name = "D3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
hdmi-out {
compatible = "hdmi-connector";
type = "a";
port {
hdmi_con: endpoint {
remote-endpoint = <&adv7511_out>;
};
};
};
lvds-decoder {
compatible = "thine,thc63lvd1024";
vcc-supply = <&d3_3v>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
thc63lvd1024_in: endpoint {
remote-endpoint = <&lvds0_out>;
};
};
port@2 {
reg = <2>;
thc63lvd1024_out: endpoint {
remote-endpoint = <&adv7511_in>;
};
};
};
};
memory@48000000 {
device_type = "memory";
/* first 128MB is reserved for secure area. */
reg = <0 0x48000000 0 0x78000000>;
};
vddq_vin01: regulator-1 {
compatible = "regulator-fixed";
regulator-name = "VDDQ_VIN01";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
x1_clk: x1-clock {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <148500000>;
};
};
&canfd {
pinctrl-0 = <&canfd0_pins>;
pinctrl-names = "default";
status = "okay";
channel0 {
status = "okay";
};
};
&csi40 {
status = "okay";
ports {
port@0 {
csi40_in: endpoint {
clock-lanes = <0>;
data-lanes = <1 2 3 4>;
remote-endpoint = <&max9286_out0>;
};
};
};
};
&csi41 {
status = "okay";
ports {
port@0 {
csi41_in: endpoint {
clock-lanes = <0>;
data-lanes = <1 2 3 4>;
remote-endpoint = <&max9286_out1>;
};
};
};
};
&du {
clocks = <&cpg CPG_MOD 724>,
<&x1_clk>;
clock-names = "du.0", "dclkin.0";
status = "okay";
};
&extal_clk {
clock-frequency = <16666666>;
};
&extalr_clk {
clock-frequency = <32768>;
};
&gether {
pinctrl-0 = <&gether_pins>;
pinctrl-names = "default";
phy-mode = "rgmii-id";
phy-handle = <&phy0>;
renesas,no-ether-link;
status = "okay";
phy0: ethernet-phy@0 {
compatible = "ethernet-phy-id0022.1622",
"ethernet-phy-ieee802.3-c22";
rxc-skew-ps = <1500>;
reg = <0>;
interrupt-parent = <&gpio4>;
interrupts = <23 IRQ_TYPE_LEVEL_LOW>;
reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
};
};
&i2c0 {
pinctrl-0 = <&i2c0_pins>;
pinctrl-names = "default";
status = "okay";
clock-frequency = <400000>;
io_expander0: gpio@20 {
compatible = "onnn,pca9654";
reg = <0x20>;
gpio-controller;
#gpio-cells = <2>;
};
io_expander1: gpio@21 {
compatible = "onnn,pca9654";
reg = <0x21>;
gpio-controller;
#gpio-cells = <2>;
};
hdmi@39 {
compatible = "adi,adv7511w";
reg = <0x39>;
interrupt-parent = <&gpio1>;
interrupts = <20 IRQ_TYPE_LEVEL_LOW>;
avdd-supply = <&d1_8v>;
dvdd-supply = <&d1_8v>;
pvdd-supply = <&d1_8v>;
bgvdd-supply = <&d1_8v>;
dvdd-3v-supply = <&d3_3v>;
adi,input-depth = <8>;
adi,input-colorspace = "rgb";
adi,input-clock = "1x";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
adv7511_in: endpoint {
remote-endpoint = <&thc63lvd1024_out>;
};
};
port@1 {
reg = <1>;
adv7511_out: endpoint {
remote-endpoint = <&hdmi_con>;
};
};
};
};
};
&i2c1 {
pinctrl-0 = <&i2c1_pins>;
pinctrl-names = "default";
status = "okay";
clock-frequency = <400000>;
gmsl0: gmsl-deserializer@48 {
compatible = "maxim,max9286";
reg = <0x48>;
maxim,gpio-poc = <0 GPIO_ACTIVE_LOW>;
enable-gpios = <&io_expander0 0 GPIO_ACTIVE_HIGH>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
};
port@1 {
reg = <1>;
};
port@2 {
reg = <2>;
};
port@3 {
reg = <3>;
};
port@4 {
reg = <4>;
max9286_out0: endpoint {
clock-lanes = <0>;
data-lanes = <1 2 3 4>;
remote-endpoint = <&csi40_in>;
};
};
};
i2c-mux {
#address-cells = <1>;
#size-cells = <0>;
i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
status = "disabled";
};
i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
status = "disabled";
};
i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
status = "disabled";
};
i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
status = "disabled";
};
};
};
gmsl1: gmsl-deserializer@4a {
compatible = "maxim,max9286";
reg = <0x4a>;
maxim,gpio-poc = <0 GPIO_ACTIVE_LOW>;
enable-gpios = <&io_expander1 0 GPIO_ACTIVE_HIGH>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
};
port@1 {
reg = <1>;
};
port@2 {
reg = <2>;
};
port@3 {
reg = <3>;
};
port@4 {
reg = <4>;
max9286_out1: endpoint {
clock-lanes = <0>;
data-lanes = <1 2 3 4>;
remote-endpoint = <&csi41_in>;
};
};
};
i2c-mux {
#address-cells = <1>;
#size-cells = <0>;
i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
status = "disabled";
};
i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
status = "disabled";
};
i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
status = "disabled";
};
i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
status = "disabled";
};
};
};
};
&lvds0 {
status = "okay";
ports {
port@1 {
lvds0_out: endpoint {
remote-endpoint = <&thc63lvd1024_in>;
};
};
};
};
&mmc0 {
pinctrl-0 = <&mmc_pins>;
pinctrl-1 = <&mmc_pins>;
pinctrl-names = "default", "state_uhs";
vmmc-supply = <&d3_3v>;
vqmmc-supply = <&vddq_vin01>;
mmc-hs200-1_8v;
bus-width = <8>;
no-sd;
no-sdio;
non-removable;
status = "okay";
};
&pciec {
status = "okay";
};
&pcie_bus_clk {
clock-frequency = <100000000>;
};
&pcie_phy {
status = "okay";
};
&pfc {
canfd0_pins: canfd0 {
groups = "canfd0_data_a";
function = "canfd0";
};
gether_pins: gether {
groups = "gether_mdio_a", "gether_rgmii",
"gether_txcrefclk", "gether_txcrefclk_mega";
function = "gether";
};
i2c0_pins: i2c0 {
groups = "i2c0";
function = "i2c0";
};
i2c1_pins: i2c1 {
groups = "i2c1";
function = "i2c1";
};
mmc_pins: mmc {
groups = "mmc_data8", "mmc_ctrl", "mmc_ds";
function = "mmc";
power-source = <1800>;
};
qspi0_pins: qspi0 {
groups = "qspi0_ctrl", "qspi0_data4";
function = "qspi0";
};
scif0_pins: scif0 {
groups = "scif0_data";
function = "scif0";
};
scif_clk_pins: scif_clk {
groups = "scif_clk_b";
function = "scif_clk";
};
};
&rpc {
pinctrl-0 = <&qspi0_pins>;
pinctrl-names = "default";
status = "okay";
flash@0 {
compatible = "spansion,s25fs512s", "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <50000000>;
spi-rx-bus-width = <4>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
bootparam@0 {
reg = <0x00000000 0x040000>;
read-only;
};
cr7@40000 {
reg = <0x00040000 0x080000>;
read-only;
};
cert_header_sa3@c0000 {
reg = <0x000c0000 0x080000>;
read-only;
};
bl2@140000 {
reg = <0x00140000 0x040000>;
read-only;
};
cert_header_sa6@180000 {
reg = <0x00180000 0x040000>;
read-only;
};
bl31@1c0000 {
reg = <0x001c0000 0x460000>;
read-only;
};
uboot@640000 {
reg = <0x00640000 0x0c0000>;
read-only;
};
uboot-env@700000 {
reg = <0x00700000 0x040000>;
read-only;
};
dtb@740000 {
reg = <0x00740000 0x080000>;
};
kernel@7c0000 {
reg = <0x007c0000 0x1400000>;
};
user@1bc0000 {
reg = <0x01bc0000 0x2440000>;
};
};
};
};
&rwdt {
timeout-sec = <60>;
status = "okay";
};
&scif0 {
pinctrl-0 = <&scif0_pins>, <&scif_clk_pins>;
pinctrl-names = "default";
status = "okay";
};
&scif_clk {
clock-frequency = <14745600>;
};

6
arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts
View File

@@ -15,6 +15,12 @@ / {
compatible = "renesas,v3hsk", "renesas,r8a77980";
aliases {
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
i2c3 = &i2c3;
i2c4 = &i2c4;
i2c5 = &i2c5;
serial0 = &scif0;
ethernet0 = &gether;
};

10
arch/arm64/boot/dts/renesas/r8a77980.dtsi
View File

@@ -16,15 +16,6 @@ / {
#address-cells = <2>;
#size-cells = <2>;
aliases {
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
i2c3 = &i2c3;
i2c4 = &i2c4;
i2c5 = &i2c5;
};
/* External CAN clock - to be overridden by boards that provide it */
can_clk: can {
compatible = "fixed-clock";
@@ -1359,7 +1350,6 @@ rpc: spi@ee200000 {
reg-names = "regs", "dirmap", "wbuf";
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 917>;
clock-names = "rpc";
power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
resets = <&cpg 917>;
#address-cells = <1>;

15
arch/arm64/boot/dts/renesas/r8a77980a-condor-i.dts Normal file
View File

@@ -0,0 +1,15 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Device Tree Source for the Condor-I board on r8a77980A (ES2.0)
*
* Copyright (C) 2022 Renesas Electronics Corp.
*/
/dts-v1/;
#include "r8a77980a.dtsi"
#include "condor-common.dtsi"
/ {
model = "Renesas Condor-I board based on r8a77980A (ES2.0)";
compatible = "renesas,condor-i", "renesas,r8a77980a", "renesas,r8a77980";
};

11
arch/arm64/boot/dts/renesas/r8a77980a.dtsi Normal file
View File

@@ -0,0 +1,11 @@
// SPDX-License-Identifier: (GPL-2.0 or MIT)
/*
* Device Tree Source for the R-Car V3H2 (R8A77980A) SoC
*
* Copyright (C) 2022 Renesas Electronics Corp.
*/
#include "r8a77980.dtsi"
/ {
compatible = "renesas,r8a77980a", "renesas,r8a77980";
};

11
arch/arm64/boot/dts/renesas/r8a77990.dtsi
View File

@@ -14,17 +14,6 @@ / {
#address-cells = <2>;
#size-cells = <2>;
aliases {
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
i2c3 = &i2c3;
i2c4 = &i2c4;
i2c5 = &i2c5;
i2c6 = &i2c6;
i2c7 = &i2c7;
};
/*
* The external audio clocks are configured as 0 Hz fixed frequency
* clocks by default.

7
arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi
View File

@@ -16,6 +16,13 @@ / {
compatible = "renesas,falcon-cpu", "renesas,r8a779a0";
aliases {
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
i2c3 = &i2c3;
i2c4 = &i2c4;
i2c5 = &i2c5;
i2c6 = &i2c6;
serial0 = &scif0;
};

11
arch/arm64/boot/dts/renesas/r8a779a0.dtsi
View File

@@ -14,16 +14,6 @@ / {
#address-cells = <2>;
#size-cells = <2>;
aliases {
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
i2c3 = &i2c3;
i2c4 = &i2c4;
i2c5 = &i2c5;
i2c6 = &i2c6;
};
/* External CAN clock - to be overridden by boards that provide it */
can_clk: can {
compatible = "fixed-clock";
@@ -2096,7 +2086,6 @@ rpc: spi@ee200000 {
reg-names = "regs", "dirmap", "wbuf";
interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 629>;
clock-names = "rpc";
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
resets = <&cpg 629>;
#address-cells = <1>;

45
arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi
View File

@@ -21,6 +21,24 @@ memory@480000000 {
device_type = "memory";
reg = <0x4 0x80000000 0x0 0x80000000>;
};
reg_1p8v: regulator-1p8v {
compatible = "regulator-fixed";
regulator-name = "fixed-1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
};
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "fixed-3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
};
&extal_clk {
@@ -46,6 +64,27 @@ eeprom@50 {
};
};
/*
* This board also has a microSD slot which we will not support upstream
* because we cannot directly switch voltages in software.
*/
&mmc0 {
pinctrl-0 = <&mmc_pins>;
pinctrl-1 = <&mmc_pins>;
pinctrl-names = "default", "state_uhs";
vmmc-supply = <&reg_3p3v>;
vqmmc-supply = <&reg_1p8v>;
mmc-hs200-1_8v;
mmc-hs400-1_8v;
bus-width = <8>;
no-sd;
no-sdio;
non-removable;
full-pwr-cycle-in-suspend;
status = "okay";
};
&pfc {
pinctrl-0 = <&scif_clk_pins>;
pinctrl-names = "default";
@@ -55,6 +94,12 @@ i2c4_pins: i2c4 {
function = "i2c4";
};
mmc_pins: mmc {
groups = "mmc_data8", "mmc_ctrl", "mmc_ds";
function = "mmc";
power-source = <1800>;
};
scif0_pins: scif0 {
groups = "scif0_data", "scif0_ctrl";
function = "scif0";

212
arch/arm64/boot/dts/renesas/r8a779f0.dtsi
View File

@@ -301,6 +301,76 @@ gpio3: gpio@e6051980 {
#interrupt-cells = <2>;
};
cmt0: timer@e60f0000 {
compatible = "renesas,r8a779f0-cmt0",
"renesas,rcar-gen4-cmt0";
reg = <0 0xe60f0000 0 0x1004>;
interrupts = <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 910>;
clock-names = "fck";
power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
resets = <&cpg 910>;
status = "disabled";
};
cmt1: timer@e6130000 {
compatible = "renesas,r8a779f0-cmt1",
"renesas,rcar-gen4-cmt1";
reg = <0 0xe6130000 0 0x1004>;
interrupts = <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 911>;
clock-names = "fck";
power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
resets = <&cpg 911>;
status = "disabled";
};
cmt2: timer@e6140000 {
compatible = "renesas,r8a779f0-cmt1",
"renesas,rcar-gen4-cmt1";
reg = <0 0xe6140000 0 0x1004>;
interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 912>;
clock-names = "fck";
power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
resets = <&cpg 912>;
status = "disabled";
};
cmt3: timer@e6148000 {
compatible = "renesas,r8a779f0-cmt1",
"renesas,rcar-gen4-cmt1";
reg = <0 0xe6148000 0 0x1004>;
interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 913>;
clock-names = "fck";
power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
resets = <&cpg 913>;
status = "disabled";
};
cpg: clock-controller@e6150000 {
compatible = "renesas,r8a779f0-cpg-mssr";
reg = <0 0xe6150000 0 0x4000>;
@@ -334,6 +404,71 @@ tsc: thermal@e6198000 {
#thermal-sensor-cells = <1>;
};
tmu0: timer@e61e0000 {
compatible = "renesas,tmu-r8a779f0", "renesas,tmu";
reg = <0 0xe61e0000 0 0x30>;
interrupts = <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 713>;
clock-names = "fck";
power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
resets = <&cpg 713>;
status = "disabled";
};
tmu1: timer@e6fc0000 {
compatible = "renesas,tmu-r8a779f0", "renesas,tmu";
reg = <0 0xe6fc0000 0 0x30>;
interrupts = <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 714>;
clock-names = "fck";
power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
resets = <&cpg 714>;
status = "disabled";
};
tmu2: timer@e6fd0000 {
compatible = "renesas,tmu-r8a779f0", "renesas,tmu";
reg = <0 0xe6fd0000 0 0x30>;
interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 482 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 483 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 715>;
clock-names = "fck";
power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
resets = <&cpg 715>;
status = "disabled";
};
tmu3: timer@e6fe0000 {
compatible = "renesas,tmu-r8a779f0", "renesas,tmu";
reg = <0 0xe6fe0000 0 0x30>;
interrupts = <GIC_SPI 485 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 716>;
clock-names = "fck";
power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
resets = <&cpg 716>;
status = "disabled";
};
tmu4: timer@ffc00000 {
compatible = "renesas,tmu-r8a779f0", "renesas,tmu";
reg = <0 0xffc00000 0 0x30>;
interrupts = <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 717>;
clock-names = "fck";
power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
resets = <&cpg 717>;
status = "disabled";
};
i2c0: i2c@e6500000 {
compatible = "renesas,i2c-r8a779f0",
"renesas,rcar-gen4-i2c";
@@ -584,6 +719,70 @@ scif4: serial@e6c40000 {
status = "disabled";
};
msiof0: spi@e6e90000 {
compatible = "renesas,msiof-r8a779f0",
"renesas,rcar-gen4-msiof";
reg = <0 0xe6e90000 0 0x0064>;
interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 618>;
dmas = <&dmac0 0x41>, <&dmac0 0x40>,
<&dmac1 0x41>, <&dmac1 0x40>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
resets = <&cpg 618>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
msiof1: spi@e6ea0000 {
compatible = "renesas,msiof-r8a779f0",
"renesas,rcar-gen4-msiof";
reg = <0 0xe6ea0000 0 0x0064>;
interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 619>;
dmas = <&dmac0 0x43>, <&dmac0 0x42>,
<&dmac1 0x43>, <&dmac1 0x42>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
resets = <&cpg 619>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
msiof2: spi@e6c00000 {
compatible = "renesas,msiof-r8a779f0",
"renesas,rcar-gen4-msiof";
reg = <0 0xe6c00000 0 0x0064>;
interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 620>;
dmas = <&dmac0 0x45>, <&dmac0 0x44>,
<&dmac1 0x45>, <&dmac1 0x44>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
resets = <&cpg 620>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
msiof3: spi@e6c10000 {
compatible = "renesas,msiof-r8a779f0",
"renesas,rcar-gen4-msiof";
reg = <0 0xe6c10000 0 0x0064>;
interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 621>;
dmas = <&dmac0 0x47>, <&dmac0 0x46>,
<&dmac1 0x47>, <&dmac1 0x46>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
resets = <&cpg 621>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
dmac0: dma-controller@e7350000 {
compatible = "renesas,dmac-r8a779f0",
"renesas,rcar-gen4-dmac";
@@ -670,6 +869,19 @@ dmac1: dma-controller@e7351000 {
<&ipmmu_ds0 30>, <&ipmmu_ds0 31>;
};
mmc0: mmc@ee140000 {
compatible = "renesas,sdhi-r8a779f0",
"renesas,rcar-gen4-sdhi";
reg = <0 0xee140000 0 0x2000>;
interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 706>, <&cpg CPG_CORE R8A779F0_CLK_SD0H>;
clock-names = "core", "clkh";
power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
resets = <&cpg 706>;
max-frequency = <200000000>;
status = "disabled";
};
ipmmu_rt0: iommu@ee480000 {
compatible = "renesas,ipmmu-r8a779f0",
"renesas,rcar-gen4-ipmmu-vmsa";

12
arch/arm64/boot/dts/renesas/r8a779mb.dtsi Normal file
View File

@@ -0,0 +1,12 @@
// SPDX-License-Identifier: (GPL-2.0 or MIT)
/*
* Device Tree Source for the R-Car H3Ne-1.7G (R8A779MB) SoC
*
* Copyright (C) 2022 Glider bv
*/
#include "r8a77951.dtsi"
/ {
compatible = "renesas,r8a779mb", "renesas,r8a7795";
};

18
arch/arm64/boot/dts/renesas/r9a07g043.dtsi
View File

@@ -13,14 +13,14 @@ / {
#address-cells = <2>;
#size-cells = <2>;
audio_clk1: audio-clk1 {
audio_clk1: audio1-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
/* This value must be overridden by boards that provide it */
clock-frequency = <0>;
};
audio_clk2: audio-clk2 {
audio_clk2: audio2-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
/* This value must be overridden by boards that provide it */
@@ -196,6 +196,8 @@ spi0: spi@1004ac00 {
interrupt-names = "error", "rx", "tx";
clocks = <&cpg CPG_MOD R9A07G043_RSPI0_CLKB>;
resets = <&cpg R9A07G043_RSPI0_RST>;
dmas = <&dmac 0x2e95>, <&dmac 0x2e96>;
dma-names = "tx", "rx";
power-domains = <&cpg>;
num-cs = <1>;
#address-cells = <1>;
@@ -212,6 +214,8 @@ spi1: spi@1004b000 {
interrupt-names = "error", "rx", "tx";
clocks = <&cpg CPG_MOD R9A07G043_RSPI1_CLKB>;
resets = <&cpg R9A07G043_RSPI1_RST>;
dmas = <&dmac 0x2e99>, <&dmac 0x2e9a>;
dma-names = "tx", "rx";
power-domains = <&cpg>;
num-cs = <1>;
#address-cells = <1>;
@@ -228,6 +232,8 @@ spi2: spi@1004b400 {
interrupt-names = "error", "rx", "tx";
clocks = <&cpg CPG_MOD R9A07G043_RSPI2_CLKB>;
resets = <&cpg R9A07G043_RSPI2_RST>;
dmas = <&dmac 0x2e9d>, <&dmac 0x2e9e>;
dma-names = "tx", "rx";
power-domains = <&cpg>;
num-cs = <1>;
#address-cells = <1>;
@@ -334,8 +340,8 @@ sci0: serial@1004d000 {
compatible = "renesas,r9a07g043-sci", "renesas,sci";
reg = <0 0x1004d000 0 0x400>;
interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 406 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 407 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "eri", "rxi", "txi", "tei";
clocks = <&cpg CPG_MOD R9A07G043_SCI0_CLKP>;
@@ -349,8 +355,8 @@ sci1: serial@1004d400 {
compatible = "renesas,r9a07g043-sci", "renesas,sci";
reg = <0 0x1004d400 0 0x400>;
interrupts = <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 410 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 411 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "eri", "rxi", "txi", "tei";
clocks = <&cpg CPG_MOD R9A07G043_SCI1_CLKP>;

73
arch/arm64/boot/dts/renesas/r9a07g044.dtsi
View File

@@ -261,6 +261,8 @@ spi0: spi@1004ac00 {
interrupt-names = "error", "rx", "tx";
clocks = <&cpg CPG_MOD R9A07G044_RSPI0_CLKB>;
resets = <&cpg R9A07G044_RSPI0_RST>;
dmas = <&dmac 0x2e95>, <&dmac 0x2e96>;
dma-names = "tx", "rx";
power-domains = <&cpg>;
num-cs = <1>;
#address-cells = <1>;
@@ -277,6 +279,8 @@ spi1: spi@1004b000 {
interrupt-names = "error", "rx", "tx";
clocks = <&cpg CPG_MOD R9A07G044_RSPI1_CLKB>;
resets = <&cpg R9A07G044_RSPI1_RST>;
dmas = <&dmac 0x2e99>, <&dmac 0x2e9a>;
dma-names = "tx", "rx";
power-domains = <&cpg>;
num-cs = <1>;
#address-cells = <1>;
@@ -293,6 +297,8 @@ spi2: spi@1004b400 {
interrupt-names = "error", "rx", "tx";
clocks = <&cpg CPG_MOD R9A07G044_RSPI2_CLKB>;
resets = <&cpg R9A07G044_RSPI2_RST>;
dmas = <&dmac 0x2e9d>, <&dmac 0x2e9e>;
dma-names = "tx", "rx";
power-domains = <&cpg>;
num-cs = <1>;
#address-cells = <1>;
@@ -394,8 +400,8 @@ sci0: serial@1004d000 {
compatible = "renesas,r9a07g044-sci", "renesas,sci";
reg = <0 0x1004d000 0 0x400>;
interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 406 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 407 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "eri", "rxi", "txi", "tei";
clocks = <&cpg CPG_MOD R9A07G044_SCI0_CLKP>;
@@ -409,8 +415,8 @@ sci1: serial@1004d400 {
compatible = "renesas,r9a07g044-sci", "renesas,sci";
reg = <0 0x1004d400 0 0x400>;
interrupts = <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 410 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 411 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "eri", "rxi", "txi", "tei";
clocks = <&cpg CPG_MOD R9A07G044_SCI1_CLKP>;
@@ -638,6 +644,10 @@ pinctrl: pinctrl@11030000 {
reg = <0 0x11030000 0 0x10000>;
gpio-controller;
#gpio-cells = <2>;
#address-cells = <2>;
#interrupt-cells = <2>;
interrupt-parent = <&irqc>;
interrupt-controller;
gpio-ranges = <&pinctrl 0 0 392>;
clocks = <&cpg CPG_MOD R9A07G044_GPIO_HCLK>;
power-domains = <&cpg>;
@@ -646,6 +656,61 @@ pinctrl: pinctrl@11030000 {
<&cpg R9A07G044_GPIO_SPARE_RESETN>;
};
irqc: interrupt-controller@110a0000 {
compatible = "renesas,r9a07g044-irqc",
"renesas,rzg2l-irqc";
#interrupt-cells = <2>;
#address-cells = <0>;
interrupt-controller;
reg = <0 0x110a0000 0 0x10000>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD R9A07G044_IA55_CLK>,
<&cpg CPG_MOD R9A07G044_IA55_PCLK>;
clock-names = "clk", "pclk";
power-domains = <&cpg>;
resets = <&cpg R9A07G044_IA55_RESETN>;
};
dmac: dma-controller@11820000 {
compatible = "renesas,r9a07g044-dmac",
"renesas,rz-dmac";

73
arch/arm64/boot/dts/renesas/r9a07g054.dtsi
View File

@@ -261,6 +261,8 @@ spi0: spi@1004ac00 {
interrupt-names = "error", "rx", "tx";
clocks = <&cpg CPG_MOD R9A07G054_RSPI0_CLKB>;
resets = <&cpg R9A07G054_RSPI0_RST>;
dmas = <&dmac 0x2e95>, <&dmac 0x2e96>;
dma-names = "tx", "rx";
power-domains = <&cpg>;
num-cs = <1>;
#address-cells = <1>;
@@ -277,6 +279,8 @@ spi1: spi@1004b000 {
interrupt-names = "error", "rx", "tx";
clocks = <&cpg CPG_MOD R9A07G054_RSPI1_CLKB>;
resets = <&cpg R9A07G054_RSPI1_RST>;
dmas = <&dmac 0x2e99>, <&dmac 0x2e9a>;
dma-names = "tx", "rx";
power-domains = <&cpg>;
num-cs = <1>;
#address-cells = <1>;
@@ -293,6 +297,8 @@ spi2: spi@1004b400 {
interrupt-names = "error", "rx", "tx";
clocks = <&cpg CPG_MOD R9A07G054_RSPI2_CLKB>;
resets = <&cpg R9A07G054_RSPI2_RST>;
dmas = <&dmac 0x2e9d>, <&dmac 0x2e9e>;
dma-names = "tx", "rx";
power-domains = <&cpg>;
num-cs = <1>;
#address-cells = <1>;
@@ -399,8 +405,8 @@ sci0: serial@1004d000 {
compatible = "renesas,r9a07g054-sci", "renesas,sci";
reg = <0 0x1004d000 0 0x400>;
interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 406 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 407 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "eri", "rxi", "txi", "tei";
clocks = <&cpg CPG_MOD R9A07G054_SCI0_CLKP>;
@@ -414,8 +420,8 @@ sci1: serial@1004d400 {
compatible = "renesas,r9a07g054-sci", "renesas,sci";
reg = <0 0x1004d400 0 0x400>;
interrupts = <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 410 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 411 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "eri", "rxi", "txi", "tei";
clocks = <&cpg CPG_MOD R9A07G054_SCI1_CLKP>;
@@ -644,6 +650,10 @@ pinctrl: pinctrl@11030000 {
reg = <0 0x11030000 0 0x10000>;
gpio-controller;
#gpio-cells = <2>;
#address-cells = <2>;
#interrupt-cells = <2>;
interrupt-parent = <&irqc>;
interrupt-controller;
gpio-ranges = <&pinctrl 0 0 392>;
clocks = <&cpg CPG_MOD R9A07G054_GPIO_HCLK>;
power-domains = <&cpg>;
@@ -652,6 +662,61 @@ pinctrl: pinctrl@11030000 {
<&cpg R9A07G054_GPIO_SPARE_RESETN>;
};
irqc: interrupt-controller@110a0000 {
compatible = "renesas,r9a07g054-irqc",
"renesas,rzg2l-irqc";
#interrupt-cells = <2>;
#address-cells = <0>;
interrupt-controller;
reg = <0 0x110a0000 0 0x10000>;
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD R9A07G054_IA55_CLK>,
<&cpg CPG_MOD R9A07G054_IA55_PCLK>;
clock-names = "clk", "pclk";
power-domains = <&cpg>;
resets = <&cpg R9A07G054_IA55_RESETN>;
};
dmac: dma-controller@11820000 {
compatible = "renesas,r9a07g054-dmac",
"renesas,rz-dmac";

27
arch/arm64/boot/dts/renesas/r9a09g011-v2mevk2.dts
View File

@@ -7,6 +7,7 @@
/dts-v1/;
#include "r9a09g011.dtsi"
#include <dt-bindings/pinctrl/rzv2m-pinctrl.h>
/ {
model = "RZ/V2M Evaluation Kit 2.0";
@@ -53,6 +54,32 @@ &extal_clk {
clock-frequency = <48000000>;
};
&i2c0 {
pinctrl-0 = <&i2c0_pins>;
pinctrl-names = "default";
clock-frequency = <400000>;
status = "okay";
};
&i2c2 {
pinctrl-0 = <&i2c2_pins>;
pinctrl-names = "default";
clock-frequency = <100000>;
status = "okay";
};
&pinctrl {
i2c0_pins: i2c0 {
pinmux = <RZV2M_PORT_PINMUX(5, 0, 2)>, /* SDA */
<RZV2M_PORT_PINMUX(5, 1, 2)>; /* SCL */
};
i2c2_pins: i2c2 {
pinmux = <RZV2M_PORT_PINMUX(3, 8, 2)>, /* SDA */
<RZV2M_PORT_PINMUX(3, 9, 2)>; /* SCL */
};
};
&uart0 {
status = "okay";
};

78
arch/arm64/boot/dts/renesas/r9a09g011.dtsi
View File

@@ -123,6 +123,34 @@ cpg: clock-controller@a3500000 {
#power-domain-cells = <0>;
};
i2c0: i2c@a4030000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "renesas,i2c-r9a09g011", "renesas,rzv2m-i2c";
reg = <0 0xa4030000 0 0x80>;
interrupts = <GIC_SPI 232 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 236 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "tia", "tis";
clocks = <&cpg CPG_MOD R9A09G011_IIC_PCLK0>;
resets = <&cpg R9A09G011_IIC_GPA_PRESETN>;
power-domains = <&cpg>;
status = "disabled";
};
i2c2: i2c@a4030100 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "renesas,i2c-r9a09g011", "renesas,rzv2m-i2c";
reg = <0 0xa4030100 0 0x80>;
interrupts = <GIC_SPI 234 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 238 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "tia", "tis";
clocks = <&cpg CPG_MOD R9A09G011_IIC_PCLK1>;
resets = <&cpg R9A09G011_IIC_GPB_PRESETN>;
power-domains = <&cpg>;
status = "disabled";
};
uart0: serial@a4040000 {
compatible = "renesas,r9a09g011-uart", "renesas,em-uart";
reg = <0 0xa4040000 0 0x80>;
@@ -132,6 +160,56 @@ uart0: serial@a4040000 {
clock-names = "sclk", "pclk";
status = "disabled";
};
pinctrl: pinctrl@b6250000 {
compatible = "renesas,r9a09g011-pinctrl";
reg = <0 0xb6250000 0 0x800>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pinctrl 0 0 352>;
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD R9A09G011_PFC_PCLK>;
power-domains = <&cpg>;
resets = <&cpg R9A09G011_PFC_PRESETN>;
};
};
timer {

11
arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi
View File

@@ -6,6 +6,7 @@
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irqc-rzg2l.h>
#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
/* SW1[2] should be at position 2/OFF to enable 64 GB eMMC */
@@ -94,6 +95,8 @@ phy0: ethernet-phy@7 {
compatible = "ethernet-phy-id0022.1640",
"ethernet-phy-ieee802.3-c22";
reg = <7>;
interrupt-parent = <&irqc>;
interrupts = <RZG2L_IRQ2 IRQ_TYPE_LEVEL_LOW>;
rxc-skew-psec = <2400>;
txc-skew-psec = <2400>;
rxdv-skew-psec = <0>;
@@ -120,6 +123,8 @@ phy1: ethernet-phy@7 {
compatible = "ethernet-phy-id0022.1640",
"ethernet-phy-ieee802.3-c22";
reg = <7>;
interrupt-parent = <&irqc>;
interrupts = <RZG2L_IRQ3 IRQ_TYPE_LEVEL_LOW>;
rxc-skew-psec = <2400>;
txc-skew-psec = <2400>;
rxdv-skew-psec = <0>;
@@ -171,7 +176,8 @@ eth0_pins: eth0 {
<RZG2L_PORT_PINMUX(25, 0, 1)>, /* ET0_RXD0 */
<RZG2L_PORT_PINMUX(25, 1, 1)>, /* ET0_RXD1 */
<RZG2L_PORT_PINMUX(26, 0, 1)>, /* ET0_RXD2 */
<RZG2L_PORT_PINMUX(26, 1, 1)>; /* ET0_RXD3 */
<RZG2L_PORT_PINMUX(26, 1, 1)>, /* ET0_RXD3 */
<RZG2L_PORT_PINMUX(1, 0, 1)>; /* IRQ2 */
};
eth1_pins: eth1 {
@@ -189,7 +195,8 @@ eth1_pins: eth1 {
<RZG2L_PORT_PINMUX(34, 1, 1)>, /* ET1_RXD0 */
<RZG2L_PORT_PINMUX(35, 0, 1)>, /* ET1_RXD1 */
<RZG2L_PORT_PINMUX(35, 1, 1)>, /* ET1_RXD2 */
<RZG2L_PORT_PINMUX(36, 0, 1)>; /* ET1_RXD3 */
<RZG2L_PORT_PINMUX(36, 0, 1)>, /* ET1_RXD3 */
<RZG2L_PORT_PINMUX(1, 1, 1)>; /* IRQ3 */
};
gpio-sd0-pwr-en-hog {

8
arch/arm64/boot/dts/renesas/salvator-common.dtsi
View File

@@ -33,6 +33,14 @@
/ {
aliases {
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
i2c3 = &i2c3;
i2c4 = &i2c4;
i2c5 = &i2c5;
i2c6 = &i2c6;
i2c7 = &i2c_dvfs;
serial0 = &scif2;
serial1 = &hscif1;
ethernet0 = &avb;

8
arch/arm64/boot/dts/renesas/ulcb.dtsi
View File

@@ -21,6 +21,14 @@ / {
model = "Renesas R-Car Gen3 ULCB board";
aliases {
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
i2c3 = &i2c3;
i2c4 = &i2c4;
i2c5 = &i2c5;
i2c6 = &i2c6;
i2c7 = &i2c_dvfs;
serial0 = &scif2;
ethernet0 = &avb;
mmc0 = &sdhi2;

25
include/dt-bindings/interrupt-controller/irqc-rzg2l.h Normal file
View File

@@ -0,0 +1,25 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* This header provides constants for Renesas RZ/G2L family IRQC bindings.
*
* Copyright (C) 2022 Renesas Electronics Corp.
*
*/
#ifndef __DT_BINDINGS_IRQC_RZG2L_H
#define __DT_BINDINGS_IRQC_RZG2L_H
/* NMI maps to SPI0 */
#define RZG2L_NMI 0
/* IRQ0-7 map to SPI1-8 */
#define RZG2L_IRQ0 1
#define RZG2L_IRQ1 2
#define RZG2L_IRQ2 3
#define RZG2L_IRQ3 4
#define RZG2L_IRQ4 5
#define RZG2L_IRQ5 6
#define RZG2L_IRQ6 7
#define RZG2L_IRQ7 8
#endif /* __DT_BINDINGS_IRQC_RZG2L_H */