From 6a24768c6e301a48c0610f0fac6f4461750ebf16 Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Mon, 11 Jul 2022 15:46:55 +0200 Subject: [PATCH 01/33] arm64: dts: renesas: r8a779f0: Add SDHI0 support Extracted from a larger BSP patch made by Linh Phung. Signed-off-by: Wolfram Sang Reviewed-by: Yoshihiro Shimoda Tested-by: Yoshihiro Shimoda Link: https://lore.kernel.org/r/20220711134656.277730-3-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a779f0.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi index 384817ffa4de..0c59a93cbaaa 100644 --- a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi @@ -670,6 +670,19 @@ dmac1: dma-controller@e7351000 { <&ipmmu_ds0 30>, <&ipmmu_ds0 31>; }; + mmc0: mmc@ee140000 { + compatible = "renesas,sdhi-r8a779f0", + "renesas,rcar-gen4-sdhi"; + reg = <0 0xee140000 0 0x2000>; + interrupts = ; + clocks = <&cpg CPG_MOD 706>, <&cpg CPG_CORE R8A779F0_CLK_SD0H>; + clock-names = "core", "clkh"; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 706>; + max-frequency = <200000000>; + status = "disabled"; + }; + ipmmu_rt0: iommu@ee480000 { compatible = "renesas,ipmmu-r8a779f0", "renesas,rcar-gen4-ipmmu-vmsa"; From 1ada3e53b78afc03d30f5fd7e9d54f297d09cf61 Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Mon, 11 Jul 2022 15:46:56 +0200 Subject: [PATCH 02/33] arm64: dts: renesas: spider-cpu: Enable eMMC0 This enables the on-board eMMC on the Spider board. Switch SW3 has to be in the default (neutral) position. Other settings will not be supported upstream! Signed-off-by: Wolfram Sang Reviewed-by: Yoshihiro Shimoda Tested-by: Yoshihiro Shimoda Link: https://lore.kernel.org/r/20220711134656.277730-4-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven --- .../boot/dts/renesas/r8a779f0-spider-cpu.dtsi | 45 +++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi b/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi index 28fbf7bc1eb4..4a876d47f59b 100644 --- a/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi @@ -21,6 +21,24 @@ memory@480000000 { device_type = "memory"; reg = <0x4 0x80000000 0x0 0x80000000>; }; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; }; &extal_clk { @@ -46,6 +64,27 @@ eeprom@50 { }; }; +/* + * This board also has a microSD slot which we will not support upstream + * because we cannot directly switch voltages in software. + */ +&mmc0 { + pinctrl-0 = <&mmc_pins>; + pinctrl-1 = <&mmc_pins>; + pinctrl-names = "default", "state_uhs"; + + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_1p8v>; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + bus-width = <8>; + no-sd; + no-sdio; + non-removable; + full-pwr-cycle-in-suspend; + status = "okay"; +}; + &pfc { pinctrl-0 = <&scif_clk_pins>; pinctrl-names = "default"; @@ -55,6 +94,12 @@ i2c4_pins: i2c4 { function = "i2c4"; }; + mmc_pins: mmc { + groups = "mmc_data8", "mmc_ctrl", "mmc_ds"; + function = "mmc"; + power-source = <1800>; + }; + scif0_pins: scif0 { groups = "scif0_data", "scif0_ctrl"; function = "scif0"; From d227fcc390e3e995fb8b0cd1d63f8be0ad2b47d3 Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Wed, 13 Jul 2022 12:14:46 +0200 Subject: [PATCH 03/33] arm64: dts: renesas: r8a779f0: Add CMT support This patch adds CMT{0|1|2|3} device nodes for R-Car S4-8 (r8a779f0) SoC. Signed-off-by: Wolfram Sang Link: https://lore.kernel.org/r/20220713101447.3804-3-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a779f0.dtsi | 70 +++++++++++++++++++++++ 1 file changed, 70 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi index 0c59a93cbaaa..5aff5a23cf06 100644 --- a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi @@ -301,6 +301,76 @@ gpio3: gpio@e6051980 { #interrupt-cells = <2>; }; + cmt0: timer@e60f0000 { + compatible = "renesas,r8a779f0-cmt0", + "renesas,rcar-gen4-cmt0"; + reg = <0 0xe60f0000 0 0x1004>; + interrupts = , + ; + clocks = <&cpg CPG_MOD 910>; + clock-names = "fck"; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 910>; + status = "disabled"; + }; + + cmt1: timer@e6130000 { + compatible = "renesas,r8a779f0-cmt1", + "renesas,rcar-gen4-cmt1"; + reg = <0 0xe6130000 0 0x1004>; + interrupts = , + , + , + , + , + , + , + ; + clocks = <&cpg CPG_MOD 911>; + clock-names = "fck"; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 911>; + status = "disabled"; + }; + + cmt2: timer@e6140000 { + compatible = "renesas,r8a779f0-cmt1", + "renesas,rcar-gen4-cmt1"; + reg = <0 0xe6140000 0 0x1004>; + interrupts = , + , + , + , + , + , + , + ; + clocks = <&cpg CPG_MOD 912>; + clock-names = "fck"; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 912>; + status = "disabled"; + }; + + cmt3: timer@e6148000 { + compatible = "renesas,r8a779f0-cmt1", + "renesas,rcar-gen4-cmt1"; + reg = <0 0xe6148000 0 0x1004>; + interrupts = , + , + , + , + , + , + , + ; + clocks = <&cpg CPG_MOD 913>; + clock-names = "fck"; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 913>; + status = "disabled"; + }; + cpg: clock-controller@e6150000 { compatible = "renesas,r8a779f0-cpg-mssr"; reg = <0 0xe6150000 0 0x4000>; From 5edc51af5b304a91a957b862d150cd8a89c4aa97 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Mon, 18 Jul 2022 20:56:47 +0100 Subject: [PATCH 04/33] arm64: dts: renesas: r9a07g044: Add IRQC node Add IRQC node to R9A07G044 (RZ/G2L) SoC DTSI. Signed-off-by: Lad Prabhakar Link: https://lore.kernel.org/r/20220718195651.7711-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 55 ++++++++++++++++++++++ 1 file changed, 55 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi index 3652e511160f..46fb3d83592a 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi @@ -646,6 +646,61 @@ pinctrl: pinctrl@11030000 { <&cpg R9A07G044_GPIO_SPARE_RESETN>; }; + irqc: interrupt-controller@110a0000 { + compatible = "renesas,r9a07g044-irqc", + "renesas,rzg2l-irqc"; + #interrupt-cells = <2>; + #address-cells = <0>; + interrupt-controller; + reg = <0 0x110a0000 0 0x10000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + clocks = <&cpg CPG_MOD R9A07G044_IA55_CLK>, + <&cpg CPG_MOD R9A07G044_IA55_PCLK>; + clock-names = "clk", "pclk"; + power-domains = <&cpg>; + resets = <&cpg R9A07G044_IA55_RESETN>; + }; + dmac: dma-controller@11820000 { compatible = "renesas,r9a07g044-dmac", "renesas,rz-dmac"; From 989fd5a7fb7927da37a004cce5336e3940a842e1 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Mon, 18 Jul 2022 20:56:48 +0100 Subject: [PATCH 05/33] arm64: dts: renesas: r9a07g044: Update pinctrl node to handle GPIO interrupts Add required properties in pinctrl node to handle GPIO interrupts. Signed-off-by: Lad Prabhakar Link: https://lore.kernel.org/r/20220718195651.7711-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi index 46fb3d83592a..cfdcca1cf9c6 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi @@ -638,6 +638,10 @@ pinctrl: pinctrl@11030000 { reg = <0 0x11030000 0 0x10000>; gpio-controller; #gpio-cells = <2>; + #address-cells = <2>; + #interrupt-cells = <2>; + interrupt-parent = <&irqc>; + interrupt-controller; gpio-ranges = <&pinctrl 0 0 392>; clocks = <&cpg CPG_MOD R9A07G044_GPIO_HCLK>; power-domains = <&cpg>; From 379478ab09e0c25709e804b732ee7910d14a3972 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Mon, 18 Jul 2022 20:56:49 +0100 Subject: [PATCH 06/33] arm64: dts: renesas: r9a07g054: Add IRQC node Add IRQC node to R9A07G054 (RZ/V2L) SoC DTSI. Signed-off-by: Lad Prabhakar Link: https://lore.kernel.org/r/20220718195651.7711-4-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 55 ++++++++++++++++++++++ 1 file changed, 55 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi index 4d6b9d7684c9..4b8a09abfc7f 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi @@ -652,6 +652,61 @@ pinctrl: pinctrl@11030000 { <&cpg R9A07G054_GPIO_SPARE_RESETN>; }; + irqc: interrupt-controller@110a0000 { + compatible = "renesas,r9a07g054-irqc", + "renesas,rzg2l-irqc"; + #interrupt-cells = <2>; + #address-cells = <0>; + interrupt-controller; + reg = <0 0x110a0000 0 0x10000>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + clocks = <&cpg CPG_MOD R9A07G054_IA55_CLK>, + <&cpg CPG_MOD R9A07G054_IA55_PCLK>; + clock-names = "clk", "pclk"; + power-domains = <&cpg>; + resets = <&cpg R9A07G054_IA55_RESETN>; + }; + dmac: dma-controller@11820000 { compatible = "renesas,r9a07g054-dmac", "renesas,rz-dmac"; From b2c9af5f47522ae9a6665e98d5ff657972a4db97 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Mon, 18 Jul 2022 20:56:50 +0100 Subject: [PATCH 07/33] arm64: dts: renesas: r9a07g054: Update pinctrl node to handle GPIO interrupts Add required properties in pinctrl node to handle GPIO interrupts. Signed-off-by: Lad Prabhakar Link: https://lore.kernel.org/r/20220718195651.7711-5-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi index 4b8a09abfc7f..24611e4a7913 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi @@ -644,6 +644,10 @@ pinctrl: pinctrl@11030000 { reg = <0 0x11030000 0 0x10000>; gpio-controller; #gpio-cells = <2>; + #address-cells = <2>; + #interrupt-cells = <2>; + interrupt-parent = <&irqc>; + interrupt-controller; gpio-ranges = <&pinctrl 0 0 392>; clocks = <&cpg CPG_MOD R9A07G054_GPIO_HCLK>; power-domains = <&cpg>; From ee8898fd7a89d950965105731e1f933583cdfc2e Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 20 Jul 2022 10:08:04 +0200 Subject: [PATCH 08/33] arm64: dts: renesas: Add Renesas R8A779MB SoC support Add support for the Renesas R-Car H3Ne-1.7G (R8A779MB) SoC, which is a different grading of the R-Car H3-N (R8A77951) SoC. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/862a5eecc850cbb90af86a56513b644b638fb62b.1656072871.git.geert+renesas@glider.be --- arch/arm64/boot/dts/renesas/r8a779mb.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/r8a779mb.dtsi diff --git a/arch/arm64/boot/dts/renesas/r8a779mb.dtsi b/arch/arm64/boot/dts/renesas/r8a779mb.dtsi new file mode 100644 index 000000000000..40d1dce2f350 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a779mb.dtsi @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: (GPL-2.0 or MIT) +/* + * Device Tree Source for the R-Car H3Ne-1.7G (R8A779MB) SoC + * + * Copyright (C) 2022 Glider bv + */ + +#include "r8a77951.dtsi" + +/ { + compatible = "renesas,r8a779mb", "renesas,r8a7795"; +}; From 80c4ece67b4050559e4e2417e77bbfd57e8b3899 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Fri, 22 Jul 2022 16:11:53 +0100 Subject: [PATCH 09/33] dt-bindings: interrupt-controller: Add macros for NMI and IRQ0-7 interrupts present on RZ/G2L SoC Add macros for NMI and IRQ0-7 interrupts which map to SPI0-8 present on RZ/G2L (and alike) SoC's so that these can be used in the first cell of interrupt specifiers. Signed-off-by: Lad Prabhakar Acked-by: Rob Herring Link: https://lore.kernel.org/r/20220722151155.21100-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- .../interrupt-controller/irqc-rzg2l.h | 25 +++++++++++++++++++ 1 file changed, 25 insertions(+) create mode 100644 include/dt-bindings/interrupt-controller/irqc-rzg2l.h diff --git a/include/dt-bindings/interrupt-controller/irqc-rzg2l.h b/include/dt-bindings/interrupt-controller/irqc-rzg2l.h new file mode 100644 index 000000000000..34ce778885a1 --- /dev/null +++ b/include/dt-bindings/interrupt-controller/irqc-rzg2l.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * This header provides constants for Renesas RZ/G2L family IRQC bindings. + * + * Copyright (C) 2022 Renesas Electronics Corp. + * + */ + +#ifndef __DT_BINDINGS_IRQC_RZG2L_H +#define __DT_BINDINGS_IRQC_RZG2L_H + +/* NMI maps to SPI0 */ +#define RZG2L_NMI 0 + +/* IRQ0-7 map to SPI1-8 */ +#define RZG2L_IRQ0 1 +#define RZG2L_IRQ1 2 +#define RZG2L_IRQ2 3 +#define RZG2L_IRQ3 4 +#define RZG2L_IRQ4 5 +#define RZG2L_IRQ5 6 +#define RZG2L_IRQ6 7 +#define RZG2L_IRQ7 8 + +#endif /* __DT_BINDINGS_IRQC_RZG2L_H */ From ffd882417412ea7273ae14deec77711f6df54bbc Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Fri, 22 Jul 2022 16:11:55 +0100 Subject: [PATCH 10/33] arm64: dts: renesas: rzg2l-smarc-som: Add PHY interrupt support for ETH{0/1} The PHY interrupt (INT_N) pin is connected to IRQ2 and IRQ3 for ETH0 and ETH1 respectively. Signed-off-by: Lad Prabhakar Link: https://lore.kernel.org/r/20220722151155.21100-4-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi index 9410796c8ad6..c4faff092380 100644 --- a/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi @@ -6,6 +6,7 @@ */ #include +#include #include /* SW1[2] should be at position 2/OFF to enable 64 GB eMMC */ @@ -94,6 +95,8 @@ phy0: ethernet-phy@7 { compatible = "ethernet-phy-id0022.1640", "ethernet-phy-ieee802.3-c22"; reg = <7>; + interrupt-parent = <&irqc>; + interrupts = ; rxc-skew-psec = <2400>; txc-skew-psec = <2400>; rxdv-skew-psec = <0>; @@ -120,6 +123,8 @@ phy1: ethernet-phy@7 { compatible = "ethernet-phy-id0022.1640", "ethernet-phy-ieee802.3-c22"; reg = <7>; + interrupt-parent = <&irqc>; + interrupts = ; rxc-skew-psec = <2400>; txc-skew-psec = <2400>; rxdv-skew-psec = <0>; @@ -171,7 +176,8 @@ eth0_pins: eth0 { , /* ET0_RXD0 */ , /* ET0_RXD1 */ , /* ET0_RXD2 */ - ; /* ET0_RXD3 */ + , /* ET0_RXD3 */ + ; /* IRQ2 */ }; eth1_pins: eth1 { @@ -189,7 +195,8 @@ eth1_pins: eth1 { , /* ET1_RXD0 */ , /* ET1_RXD1 */ , /* ET1_RXD2 */ - ; /* ET1_RXD3 */ + , /* ET1_RXD3 */ + ; /* IRQ3 */ }; gpio-sd0-pwr-en-hog { From 7adc69f8ac35109eab2742e6bb7a747dd811d1f6 Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Tue, 26 Jul 2022 23:01:09 +0200 Subject: [PATCH 11/33] arm64: dts: renesas: r8a779f0: Add TMU nodes Signed-off-by: Wolfram Sang Link: https://lore.kernel.org/r/20220726210110.1444-3-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a779f0.dtsi | 65 +++++++++++++++++++++++ 1 file changed, 65 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi index 5aff5a23cf06..11c30e36a962 100644 --- a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi @@ -404,6 +404,71 @@ tsc: thermal@e6198000 { #thermal-sensor-cells = <1>; }; + tmu0: timer@e61e0000 { + compatible = "renesas,tmu-r8a779f0", "renesas,tmu"; + reg = <0 0xe61e0000 0 0x30>; + interrupts = , + , + ; + clocks = <&cpg CPG_MOD 713>; + clock-names = "fck"; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 713>; + status = "disabled"; + }; + + tmu1: timer@e6fc0000 { + compatible = "renesas,tmu-r8a779f0", "renesas,tmu"; + reg = <0 0xe6fc0000 0 0x30>; + interrupts = , + , + ; + clocks = <&cpg CPG_MOD 714>; + clock-names = "fck"; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 714>; + status = "disabled"; + }; + + tmu2: timer@e6fd0000 { + compatible = "renesas,tmu-r8a779f0", "renesas,tmu"; + reg = <0 0xe6fd0000 0 0x30>; + interrupts = , + , + ; + clocks = <&cpg CPG_MOD 715>; + clock-names = "fck"; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 715>; + status = "disabled"; + }; + + tmu3: timer@e6fe0000 { + compatible = "renesas,tmu-r8a779f0", "renesas,tmu"; + reg = <0 0xe6fe0000 0 0x30>; + interrupts = , + , + ; + clocks = <&cpg CPG_MOD 716>; + clock-names = "fck"; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 716>; + status = "disabled"; + }; + + tmu4: timer@ffc00000 { + compatible = "renesas,tmu-r8a779f0", "renesas,tmu"; + reg = <0 0xffc00000 0 0x30>; + interrupts = , + , + ; + clocks = <&cpg CPG_MOD 717>; + clock-names = "fck"; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 717>; + status = "disabled"; + }; + i2c0: i2c@e6500000 { compatible = "renesas,i2c-r8a779f0", "renesas,rcar-gen4-i2c"; From 200d8e0119fd8fef78fa1c6441ef9eb2c1570984 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Thu, 28 Jul 2022 13:23:10 +0100 Subject: [PATCH 12/33] arm64: dts: renesas: r9a07g043: Add DMA support to RSPI Add DMA properties to RSPI nodes to support DMA operation. Signed-off-by: Biju Das Link: https://lore.kernel.org/r/20220728122312.189766-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g043.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi index 40201a16d653..f61459a98c51 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi @@ -196,6 +196,8 @@ spi0: spi@1004ac00 { interrupt-names = "error", "rx", "tx"; clocks = <&cpg CPG_MOD R9A07G043_RSPI0_CLKB>; resets = <&cpg R9A07G043_RSPI0_RST>; + dmas = <&dmac 0x2e95>, <&dmac 0x2e96>; + dma-names = "tx", "rx"; power-domains = <&cpg>; num-cs = <1>; #address-cells = <1>; @@ -212,6 +214,8 @@ spi1: spi@1004b000 { interrupt-names = "error", "rx", "tx"; clocks = <&cpg CPG_MOD R9A07G043_RSPI1_CLKB>; resets = <&cpg R9A07G043_RSPI1_RST>; + dmas = <&dmac 0x2e99>, <&dmac 0x2e9a>; + dma-names = "tx", "rx"; power-domains = <&cpg>; num-cs = <1>; #address-cells = <1>; @@ -228,6 +232,8 @@ spi2: spi@1004b400 { interrupt-names = "error", "rx", "tx"; clocks = <&cpg CPG_MOD R9A07G043_RSPI2_CLKB>; resets = <&cpg R9A07G043_RSPI2_RST>; + dmas = <&dmac 0x2e9d>, <&dmac 0x2e9e>; + dma-names = "tx", "rx"; power-domains = <&cpg>; num-cs = <1>; #address-cells = <1>; From a43026b811700455f36bc788e480921f7d1d3e95 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Thu, 28 Jul 2022 13:23:11 +0100 Subject: [PATCH 13/33] arm64: dts: renesas: r9a07g044: Add DMA support to RSPI Add DMA properties to RSPI nodes to support DMA operation. Signed-off-by: Biju Das Link: https://lore.kernel.org/r/20220728122312.189766-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi index cfdcca1cf9c6..fa7419ba4d2a 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi @@ -261,6 +261,8 @@ spi0: spi@1004ac00 { interrupt-names = "error", "rx", "tx"; clocks = <&cpg CPG_MOD R9A07G044_RSPI0_CLKB>; resets = <&cpg R9A07G044_RSPI0_RST>; + dmas = <&dmac 0x2e95>, <&dmac 0x2e96>; + dma-names = "tx", "rx"; power-domains = <&cpg>; num-cs = <1>; #address-cells = <1>; @@ -277,6 +279,8 @@ spi1: spi@1004b000 { interrupt-names = "error", "rx", "tx"; clocks = <&cpg CPG_MOD R9A07G044_RSPI1_CLKB>; resets = <&cpg R9A07G044_RSPI1_RST>; + dmas = <&dmac 0x2e99>, <&dmac 0x2e9a>; + dma-names = "tx", "rx"; power-domains = <&cpg>; num-cs = <1>; #address-cells = <1>; @@ -293,6 +297,8 @@ spi2: spi@1004b400 { interrupt-names = "error", "rx", "tx"; clocks = <&cpg CPG_MOD R9A07G044_RSPI2_CLKB>; resets = <&cpg R9A07G044_RSPI2_RST>; + dmas = <&dmac 0x2e9d>, <&dmac 0x2e9e>; + dma-names = "tx", "rx"; power-domains = <&cpg>; num-cs = <1>; #address-cells = <1>; From 34fac90f361f14aad0d0bfeabba9211fd584a963 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Thu, 28 Jul 2022 13:23:12 +0100 Subject: [PATCH 14/33] arm64: dts: renesas: r9a07g054: Add DMA support to RSPI Add DMA properties to RSPI nodes to support DMA operation. Signed-off-by: Biju Das Link: https://lore.kernel.org/r/20220728122312.189766-4-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi index 24611e4a7913..215a033ade81 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi @@ -261,6 +261,8 @@ spi0: spi@1004ac00 { interrupt-names = "error", "rx", "tx"; clocks = <&cpg CPG_MOD R9A07G054_RSPI0_CLKB>; resets = <&cpg R9A07G054_RSPI0_RST>; + dmas = <&dmac 0x2e95>, <&dmac 0x2e96>; + dma-names = "tx", "rx"; power-domains = <&cpg>; num-cs = <1>; #address-cells = <1>; @@ -277,6 +279,8 @@ spi1: spi@1004b000 { interrupt-names = "error", "rx", "tx"; clocks = <&cpg CPG_MOD R9A07G054_RSPI1_CLKB>; resets = <&cpg R9A07G054_RSPI1_RST>; + dmas = <&dmac 0x2e99>, <&dmac 0x2e9a>; + dma-names = "tx", "rx"; power-domains = <&cpg>; num-cs = <1>; #address-cells = <1>; @@ -293,6 +297,8 @@ spi2: spi@1004b400 { interrupt-names = "error", "rx", "tx"; clocks = <&cpg CPG_MOD R9A07G054_RSPI2_CLKB>; resets = <&cpg R9A07G054_RSPI2_RST>; + dmas = <&dmac 0x2e9d>, <&dmac 0x2e9e>; + dma-names = "tx", "rx"; power-domains = <&cpg>; num-cs = <1>; #address-cells = <1>; From 56f0a373f0a8f9e4a783aa600c11f00ca33398e5 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Fri, 29 Jul 2022 09:45:27 +0100 Subject: [PATCH 15/33] arm64: dts: renesas: r9a07g043: Fix audio clk node names Replace the clk node names audio-clk{1,2} with audio{1,2}-clk as per the device tree specification. Signed-off-by: Biju Das Link: https://lore.kernel.org/r/20220729084527.388023-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g043.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi index f61459a98c51..d1b567d1b6e1 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi @@ -13,14 +13,14 @@ / { #address-cells = <2>; #size-cells = <2>; - audio_clk1: audio-clk1 { + audio_clk1: audio1-clk { compatible = "fixed-clock"; #clock-cells = <0>; /* This value must be overridden by boards that provide it */ clock-frequency = <0>; }; - audio_clk2: audio-clk2 { + audio_clk2: audio2-clk { compatible = "fixed-clock"; #clock-cells = <0>; /* This value must be overridden by boards that provide it */ From f3b7bc89c97b98aa6f157d5f296695af8940a5ac Mon Sep 17 00:00:00 2001 From: Biju Das Date: Tue, 2 Aug 2022 11:15:32 +0100 Subject: [PATCH 16/33] arm64: dts: renesas: r9a07g044: Fix SCI{Rx,Tx} interrupt types As per the latest RZ/G2L Hardware User's Manual (Rev.1.10 Apr, 2022), the interrupt type of SCI{Rx,Tx} is edge triggered. Signed-off-by: Biju Das Fixes: f9a2adcc9e908907 ("arm64: dts: renesas: r9a07g044: Add SCI[0-1] nodes") Link: https://lore.kernel.org/r/20220802101534.1401342-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g044.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi index fa7419ba4d2a..35e7255471b8 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g044.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g044.dtsi @@ -400,8 +400,8 @@ sci0: serial@1004d000 { compatible = "renesas,r9a07g044-sci", "renesas,sci"; reg = <0 0x1004d000 0 0x400>; interrupts = , - , - , + , + , ; interrupt-names = "eri", "rxi", "txi", "tei"; clocks = <&cpg CPG_MOD R9A07G044_SCI0_CLKP>; @@ -415,8 +415,8 @@ sci1: serial@1004d400 { compatible = "renesas,r9a07g044-sci", "renesas,sci"; reg = <0 0x1004d400 0 0x400>; interrupts = , - , - , + , + , ; interrupt-names = "eri", "rxi", "txi", "tei"; clocks = <&cpg CPG_MOD R9A07G044_SCI1_CLKP>; From 13dec051c7f139eef345c55a60941843e72128f1 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Tue, 2 Aug 2022 11:15:33 +0100 Subject: [PATCH 17/33] arm64: dts: renesas: r9a07g054: Fix SCI{Rx,Tx} interrupt types As per the RZ/V2L Hardware User's Manual (Rev.1.00 Nov, 2021), the interrupt type of SCI{Rx,Tx} is edge triggered. Signed-off-by: Biju Das Fixes: 7c2b8198f4f321df ("arm64: dts: renesas: Add initial DTSI for RZ/V2L SoC") Link: https://lore.kernel.org/r/20220802101534.1401342-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g054.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi index 215a033ade81..d27b6c388580 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g054.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g054.dtsi @@ -405,8 +405,8 @@ sci0: serial@1004d000 { compatible = "renesas,r9a07g054-sci", "renesas,sci"; reg = <0 0x1004d000 0 0x400>; interrupts = , - , - , + , + , ; interrupt-names = "eri", "rxi", "txi", "tei"; clocks = <&cpg CPG_MOD R9A07G054_SCI0_CLKP>; @@ -420,8 +420,8 @@ sci1: serial@1004d400 { compatible = "renesas,r9a07g054-sci", "renesas,sci"; reg = <0 0x1004d400 0 0x400>; interrupts = , - , - , + , + , ; interrupt-names = "eri", "rxi", "txi", "tei"; clocks = <&cpg CPG_MOD R9A07G054_SCI1_CLKP>; From 72a482dbaec4b9e4d54b81be6bdb8c016fd2f4bd Mon Sep 17 00:00:00 2001 From: Biju Das Date: Tue, 2 Aug 2022 11:15:34 +0100 Subject: [PATCH 18/33] arm64: dts: renesas: r9a07g043: Fix SCI{Rx,Tx} interrupt types As per the RZ/G2UL Hardware User's Manual (Rev.1.00 Apr, 2022), the interrupt type of SCI{Rx,Tx} is edge triggered. Signed-off-by: Biju Das Fixes: cf40c9689e5109bf ("arm64: dts: renesas: Add initial DTSI for RZ/G2UL SoC") Link: https://lore.kernel.org/r/20220802101534.1401342-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a07g043.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi index d1b567d1b6e1..ff6aab388eb7 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi @@ -340,8 +340,8 @@ sci0: serial@1004d000 { compatible = "renesas,r9a07g043-sci", "renesas,sci"; reg = <0 0x1004d000 0 0x400>; interrupts = , - , - , + , + , ; interrupt-names = "eri", "rxi", "txi", "tei"; clocks = <&cpg CPG_MOD R9A07G043_SCI0_CLKP>; @@ -355,8 +355,8 @@ sci1: serial@1004d400 { compatible = "renesas,r9a07g043-sci", "renesas,sci"; reg = <0 0x1004d400 0 0x400>; interrupts = , - , - , + , + , ; interrupt-names = "eri", "rxi", "txi", "tei"; clocks = <&cpg CPG_MOD R9A07G043_SCI1_CLKP>; From 73ca80daf7b37b260f01cc4ce7963f48d8b5183f Mon Sep 17 00:00:00 2001 From: Phil Edworthy Date: Thu, 4 Aug 2022 20:08:46 +0100 Subject: [PATCH 19/33] arm64: dts: renesas: r9a09g011: Add pinctrl node Signed-off-by: Phil Edworthy Reviewed-by: Lad Prabhakar Link: https://lore.kernel.org/r/20220804190846.128370-1-phil.edworthy@renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a09g011.dtsi | 50 ++++++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g011.dtsi b/arch/arm64/boot/dts/renesas/r9a09g011.dtsi index d4cc5459fbb7..44e1e288343c 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g011.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g011.dtsi @@ -132,6 +132,56 @@ uart0: serial@a4040000 { clock-names = "sclk", "pclk"; status = "disabled"; }; + + pinctrl: pinctrl@b6250000 { + compatible = "renesas,r9a09g011-pinctrl"; + reg = <0 0xb6250000 0 0x800>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 0 352>; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + clocks = <&cpg CPG_MOD R9A09G011_PFC_PCLK>; + power-domains = <&cpg>; + resets = <&cpg R9A09G011_PFC_PRESETN>; + }; }; timer { From 54ac6794df9db684d367662a7ea84b7f41cf9312 Mon Sep 17 00:00:00 2001 From: Phil Edworthy Date: Fri, 19 Aug 2022 20:39:43 +0100 Subject: [PATCH 20/33] arm64: dts: renesas: r9a09g011: Add i2c nodes Add device nodes for the I2C controllers that are not assigned to the ISP. Signed-off-by: Phil Edworthy Link: https://lore.kernel.org/r/20220819193944.337599-3-phil.edworthy@renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r9a09g011.dtsi | 28 ++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g011.dtsi b/arch/arm64/boot/dts/renesas/r9a09g011.dtsi index 44e1e288343c..fb1a97202c38 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g011.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a09g011.dtsi @@ -123,6 +123,34 @@ cpg: clock-controller@a3500000 { #power-domain-cells = <0>; }; + i2c0: i2c@a4030000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r9a09g011", "renesas,rzv2m-i2c"; + reg = <0 0xa4030000 0 0x80>; + interrupts = , + ; + interrupt-names = "tia", "tis"; + clocks = <&cpg CPG_MOD R9A09G011_IIC_PCLK0>; + resets = <&cpg R9A09G011_IIC_GPA_PRESETN>; + power-domains = <&cpg>; + status = "disabled"; + }; + + i2c2: i2c@a4030100 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r9a09g011", "renesas,rzv2m-i2c"; + reg = <0 0xa4030100 0 0x80>; + interrupts = , + ; + interrupt-names = "tia", "tis"; + clocks = <&cpg CPG_MOD R9A09G011_IIC_PCLK1>; + resets = <&cpg R9A09G011_IIC_GPB_PRESETN>; + power-domains = <&cpg>; + status = "disabled"; + }; + uart0: serial@a4040000 { compatible = "renesas,r9a09g011-uart", "renesas,em-uart"; reg = <0 0xa4040000 0 0x80>; From 39ffd3307fb85ec8a73a8b9d13b0ea923c48b72a Mon Sep 17 00:00:00 2001 From: Phil Edworthy Date: Fri, 19 Aug 2022 20:39:44 +0100 Subject: [PATCH 21/33] arm64: dts: renesas: rzv2m evk: Enable i2c Signed-off-by: Phil Edworthy Link: https://lore.kernel.org/r/20220819193944.337599-4-phil.edworthy@renesas.com Signed-off-by: Geert Uytterhoeven --- .../boot/dts/renesas/r9a09g011-v2mevk2.dts | 27 +++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a09g011-v2mevk2.dts b/arch/arm64/boot/dts/renesas/r9a09g011-v2mevk2.dts index c3a52fa0b16e..5c15d73d059f 100644 --- a/arch/arm64/boot/dts/renesas/r9a09g011-v2mevk2.dts +++ b/arch/arm64/boot/dts/renesas/r9a09g011-v2mevk2.dts @@ -7,6 +7,7 @@ /dts-v1/; #include "r9a09g011.dtsi" +#include / { model = "RZ/V2M Evaluation Kit 2.0"; @@ -53,6 +54,32 @@ &extal_clk { clock-frequency = <48000000>; }; +&i2c0 { + pinctrl-0 = <&i2c0_pins>; + pinctrl-names = "default"; + clock-frequency = <400000>; + status = "okay"; +}; + +&i2c2 { + pinctrl-0 = <&i2c2_pins>; + pinctrl-names = "default"; + clock-frequency = <100000>; + status = "okay"; +}; + +&pinctrl { + i2c0_pins: i2c0 { + pinmux = , /* SDA */ + ; /* SCL */ + }; + + i2c2_pins: i2c2 { + pinmux = , /* SDA */ + ; /* SCL */ + }; +}; + &uart0 { status = "okay"; }; From 59c148535324e1fc61a0cad6d04559196dde5ed1 Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Thu, 25 Aug 2022 09:10:17 +0200 Subject: [PATCH 22/33] arm64: dts: renesas: r8a779{51|60|65}: Put I2C aliases to board files I2C aliases are not a property of a SoC. They belong to board files where they are named accordingly in the schematics. Signed-off-by: Wolfram Sang Link: https://lore.kernel.org/r/20220825071022.7864-2-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a77951.dtsi | 11 ----------- arch/arm64/boot/dts/renesas/r8a77960.dtsi | 11 ----------- arch/arm64/boot/dts/renesas/r8a77965.dtsi | 11 ----------- arch/arm64/boot/dts/renesas/salvator-common.dtsi | 8 ++++++++ arch/arm64/boot/dts/renesas/ulcb.dtsi | 8 ++++++++ 5 files changed, 16 insertions(+), 33 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a77951.dtsi b/arch/arm64/boot/dts/renesas/r8a77951.dtsi index a297af22a195..07c8763c1e77 100644 --- a/arch/arm64/boot/dts/renesas/r8a77951.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77951.dtsi @@ -21,17 +21,6 @@ / { #address-cells = <2>; #size-cells = <2>; - aliases { - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - i2c5 = &i2c5; - i2c6 = &i2c6; - i2c7 = &i2c_dvfs; - }; - /* * The external audio clocks are configured as 0 Hz fixed frequency * clocks by default. diff --git a/arch/arm64/boot/dts/renesas/r8a77960.dtsi b/arch/arm64/boot/dts/renesas/r8a77960.dtsi index 4159c23d3874..1424d4ad941f 100644 --- a/arch/arm64/boot/dts/renesas/r8a77960.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77960.dtsi @@ -16,17 +16,6 @@ / { #address-cells = <2>; #size-cells = <2>; - aliases { - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - i2c5 = &i2c5; - i2c6 = &i2c6; - i2c7 = &i2c_dvfs; - }; - /* * The external audio clocks are configured as 0 Hz fixed frequency * clocks by default. diff --git a/arch/arm64/boot/dts/renesas/r8a77965.dtsi b/arch/arm64/boot/dts/renesas/r8a77965.dtsi index 21a5e1cdd9f1..997f29521f66 100644 --- a/arch/arm64/boot/dts/renesas/r8a77965.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77965.dtsi @@ -21,17 +21,6 @@ / { #address-cells = <2>; #size-cells = <2>; - aliases { - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - i2c5 = &i2c5; - i2c6 = &i2c6; - i2c7 = &i2c_dvfs; - }; - /* * The external audio clocks are configured as 0 Hz fixed frequency * clocks by default. diff --git a/arch/arm64/boot/dts/renesas/salvator-common.dtsi b/arch/arm64/boot/dts/renesas/salvator-common.dtsi index b7c7911858b2..d97473401819 100644 --- a/arch/arm64/boot/dts/renesas/salvator-common.dtsi +++ b/arch/arm64/boot/dts/renesas/salvator-common.dtsi @@ -33,6 +33,14 @@ / { aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; + i2c6 = &i2c6; + i2c7 = &i2c_dvfs; serial0 = &scif2; serial1 = &hscif1; ethernet0 = &avb; diff --git a/arch/arm64/boot/dts/renesas/ulcb.dtsi b/arch/arm64/boot/dts/renesas/ulcb.dtsi index 0772dfe4adff..29cedf4dc1a9 100644 --- a/arch/arm64/boot/dts/renesas/ulcb.dtsi +++ b/arch/arm64/boot/dts/renesas/ulcb.dtsi @@ -21,6 +21,14 @@ / { model = "Renesas R-Car Gen3 ULCB board"; aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; + i2c6 = &i2c6; + i2c7 = &i2c_dvfs; serial0 = &scif2; ethernet0 = &avb; mmc0 = &sdhi2; From 8cc5dcfabab8cfe9dd5a4386b64f0562399e3139 Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Thu, 25 Aug 2022 09:10:18 +0200 Subject: [PATCH 23/33] arm64: dts: renesas: r8a77970: Put I2C aliases to board files I2C aliases are not a property of a SoC. They belong to board files where they are named accordingly in the schematics. Signed-off-by: Wolfram Sang Link: https://lore.kernel.org/r/20220825071022.7864-3-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a77970-eagle.dts | 5 +++++ arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts | 5 +++++ arch/arm64/boot/dts/renesas/r8a77970.dtsi | 8 -------- 3 files changed, 10 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts b/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts index 49d1a929aef7..004a5eacd460 100644 --- a/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts +++ b/arch/arm64/boot/dts/renesas/r8a77970-eagle.dts @@ -15,6 +15,11 @@ / { compatible = "renesas,eagle", "renesas,r8a77970"; aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; serial0 = &scif0; ethernet0 = &avb; }; diff --git a/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts b/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts index 39f3e6cbba3d..c2b65f8de547 100644 --- a/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts +++ b/arch/arm64/boot/dts/renesas/r8a77970-v3msk.dts @@ -15,6 +15,11 @@ / { compatible = "renesas,v3msk", "renesas,r8a77970"; aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; serial0 = &scif0; }; diff --git a/arch/arm64/boot/dts/renesas/r8a77970.dtsi b/arch/arm64/boot/dts/renesas/r8a77970.dtsi index 2703ef3a38c2..1df02facb796 100644 --- a/arch/arm64/boot/dts/renesas/r8a77970.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77970.dtsi @@ -16,14 +16,6 @@ / { #address-cells = <2>; #size-cells = <2>; - aliases { - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - }; - /* External CAN clock - to be overridden by boards that provide it */ can_clk: can { compatible = "fixed-clock"; From efab8210e015f9078001099552058b3c38b123b0 Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Thu, 25 Aug 2022 09:10:19 +0200 Subject: [PATCH 24/33] arm64: dts: renesas: r8a77980: Put I2C aliases to board files I2C aliases are not a property of a SoC. They belong to board files where they are named accordingly in the schematics. Signed-off-by: Wolfram Sang Link: https://lore.kernel.org/r/20220825071022.7864-4-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a77980-condor.dts | 6 ++++++ arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts | 6 ++++++ arch/arm64/boot/dts/renesas/r8a77980.dtsi | 9 --------- 3 files changed, 12 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a77980-condor.dts b/arch/arm64/boot/dts/renesas/r8a77980-condor.dts index 43ed033eb512..981cf4db0e54 100644 --- a/arch/arm64/boot/dts/renesas/r8a77980-condor.dts +++ b/arch/arm64/boot/dts/renesas/r8a77980-condor.dts @@ -15,6 +15,12 @@ / { compatible = "renesas,condor", "renesas,r8a77980"; aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; serial0 = &scif0; ethernet0 = &gether; }; diff --git a/arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts b/arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts index 1d09d8867651..d168b0e7747d 100644 --- a/arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts +++ b/arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts @@ -15,6 +15,12 @@ / { compatible = "renesas,v3hsk", "renesas,r8a77980"; aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; serial0 = &scif0; ethernet0 = &gether; }; diff --git a/arch/arm64/boot/dts/renesas/r8a77980.dtsi b/arch/arm64/boot/dts/renesas/r8a77980.dtsi index 8594be72f221..a3af34191ca2 100644 --- a/arch/arm64/boot/dts/renesas/r8a77980.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77980.dtsi @@ -16,15 +16,6 @@ / { #address-cells = <2>; #size-cells = <2>; - aliases { - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - i2c5 = &i2c5; - }; - /* External CAN clock - to be overridden by boards that provide it */ can_clk: can { compatible = "fixed-clock"; From fb2a16097c3cc660788cddae96dc2c44cd4502b6 Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Thu, 25 Aug 2022 09:10:20 +0200 Subject: [PATCH 25/33] arm64: dts: renesas: r8a77990: Put I2C aliases to board files I2C aliases are not a property of a SoC. They belong to board files where they are named accordingly in the schematics. Signed-off-by: Wolfram Sang Link: https://lore.kernel.org/r/20220825071022.7864-5-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/ebisu.dtsi | 8 ++++++++ arch/arm64/boot/dts/renesas/r8a77990.dtsi | 11 ----------- 2 files changed, 8 insertions(+), 11 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/ebisu.dtsi b/arch/arm64/boot/dts/renesas/ebisu.dtsi index 8fc03491a11c..bbc29452d1be 100644 --- a/arch/arm64/boot/dts/renesas/ebisu.dtsi +++ b/arch/arm64/boot/dts/renesas/ebisu.dtsi @@ -13,6 +13,14 @@ / { compatible = "renesas,ebisu"; aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; + i2c6 = &i2c6; + i2c7 = &i2c7; serial0 = &scif2; ethernet0 = &avb; mmc0 = &sdhi3; diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi b/arch/arm64/boot/dts/renesas/r8a77990.dtsi index 565e9d85946e..3053b4b21497 100644 --- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi @@ -14,17 +14,6 @@ / { #address-cells = <2>; #size-cells = <2>; - aliases { - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - i2c5 = &i2c5; - i2c6 = &i2c6; - i2c7 = &i2c7; - }; - /* * The external audio clocks are configured as 0 Hz fixed frequency * clocks by default. From 1d35135672c9c5e883eabb3b0288822cac79ac1f Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Thu, 25 Aug 2022 09:10:21 +0200 Subject: [PATCH 26/33] arm64: dts: renesas: r8a779a0: Put I2C aliases to board files I2C aliases are not a property of a SoC. They belong to board files where they are named accordingly in the schematics. Signed-off-by: Wolfram Sang Link: https://lore.kernel.org/r/20220825071022.7864-6-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi | 7 +++++++ arch/arm64/boot/dts/renesas/r8a779a0.dtsi | 10 ---------- 2 files changed, 7 insertions(+), 10 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi index 53c4a26198e3..99b73e21c82c 100644 --- a/arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi @@ -16,6 +16,13 @@ / { compatible = "renesas,falcon-cpu", "renesas,r8a779a0"; aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; + i2c6 = &i2c6; serial0 = &scif0; }; diff --git a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi index 3d668709d8a8..3e1557a5b5e1 100644 --- a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi @@ -14,16 +14,6 @@ / { #address-cells = <2>; #size-cells = <2>; - aliases { - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - i2c5 = &i2c5; - i2c6 = &i2c6; - }; - /* External CAN clock - to be overridden by boards that provide it */ can_clk: can { compatible = "fixed-clock"; From 8d580c0f5371d2fef2ad6cb57325356cb0f5a626 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 26 Aug 2022 16:49:48 +0200 Subject: [PATCH 27/33] arm64: dts: renesas: r8a774e1: Rename i2c_dvfs to iic_pmic MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit As RZ/G2 SoCs do not support DVFS, the "iic-dvfs" module was renamed to "iic-pmic" in the RZ/G Series, 2nd Generation User’s Manual: Hardware Rev. 1.00. See also commit a636d8037ef6028a ("arm64: dts: renesas: rzg2: Rename i2c_dvfs to iic_pmic"), which apparently forgot to update RZ/G2H. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/7d60653d4d63904dc025a133297a53eb885fa064.1661525361.git.geert+renesas@glider.be --- arch/arm64/boot/dts/renesas/r8a774e1.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi index 8ec59094882b..3cb3b2e052c1 100644 --- a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi @@ -769,7 +769,7 @@ i2c6: i2c@e66e8000 { status = "disabled"; }; - i2c_dvfs: i2c@e60b0000 { + iic_pmic: i2c@e60b0000 { #address-cells = <1>; #size-cells = <0>; compatible = "renesas,iic-r8a774e1", From 13079557ec9775ce4208d3066c415a0ab7ca170e Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Thu, 25 Aug 2022 09:10:22 +0200 Subject: [PATCH 28/33] arm64: dts: renesas: r8a774a1: Put I2C aliases to board files I2C aliases are not a property of a SoC. They belong to board files where they are named accordingly in the schematics. Signed-off-by: Wolfram Sang Link: https://lore.kernel.org/r/20220825071022.7864-7-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/hihope-common.dtsi | 8 ++++++++ .../boot/dts/renesas/r8a774a1-beacon-rzg2m-kit.dts | 8 ++++++++ arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 11 ----------- 3 files changed, 16 insertions(+), 11 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/hihope-common.dtsi b/arch/arm64/boot/dts/renesas/hihope-common.dtsi index b062f41ee270..83104af2813e 100644 --- a/arch/arm64/boot/dts/renesas/hihope-common.dtsi +++ b/arch/arm64/boot/dts/renesas/hihope-common.dtsi @@ -10,6 +10,14 @@ / { aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; + i2c6 = &i2c6; + i2c7 = &iic_pmic; serial0 = &scif2; serial1 = &hscif0; mmc0 = &sdhi3; diff --git a/arch/arm64/boot/dts/renesas/r8a774a1-beacon-rzg2m-kit.dts b/arch/arm64/boot/dts/renesas/r8a774a1-beacon-rzg2m-kit.dts index 3cf2e076940f..9ae67263c0df 100644 --- a/arch/arm64/boot/dts/renesas/r8a774a1-beacon-rzg2m-kit.dts +++ b/arch/arm64/boot/dts/renesas/r8a774a1-beacon-rzg2m-kit.dts @@ -14,6 +14,14 @@ / { compatible = "beacon,beacon-rzg2m", "renesas,r8a774a1"; aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; + i2c6 = &i2c6; + i2c7 = &iic_pmic; serial0 = &scif2; serial1 = &hscif0; serial2 = &hscif1; diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi index e7d17776624d..aec62c93f9a3 100644 --- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi @@ -17,17 +17,6 @@ / { #address-cells = <2>; #size-cells = <2>; - aliases { - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - i2c5 = &i2c5; - i2c6 = &i2c6; - i2c7 = &iic_pmic; - }; - /* * The external audio clocks are configured as 0 Hz fixed frequency * clocks by default. From 1cc6987e501d9cb5b83c26da1f07f5e662db7c4c Mon Sep 17 00:00:00 2001 From: Duc Nguyen Date: Mon, 29 Aug 2022 14:41:30 +0200 Subject: [PATCH 29/33] arm64: dts: renesas: r8a779f0: Add MSIOF nodes Add MSIOF nodes for R-Car S4-8. Signed-off-by: Duc Nguyen [thanh: added DMA] Signed-off-by: Thanh Quan [wsa: removed mso clock from clocks-property] Signed-off-by: Wolfram Sang Link: https://lore.kernel.org/r/20220829124130.2412-1-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a779f0.dtsi | 64 +++++++++++++++++++++++ 1 file changed, 64 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi index 11c30e36a962..c2f152bcf10e 100644 --- a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi @@ -719,6 +719,70 @@ scif4: serial@e6c40000 { status = "disabled"; }; + msiof0: spi@e6e90000 { + compatible = "renesas,msiof-r8a779f0", + "renesas,rcar-gen4-msiof"; + reg = <0 0xe6e90000 0 0x0064>; + interrupts = ; + clocks = <&cpg CPG_MOD 618>; + dmas = <&dmac0 0x41>, <&dmac0 0x40>, + <&dmac1 0x41>, <&dmac1 0x40>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 618>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + msiof1: spi@e6ea0000 { + compatible = "renesas,msiof-r8a779f0", + "renesas,rcar-gen4-msiof"; + reg = <0 0xe6ea0000 0 0x0064>; + interrupts = ; + clocks = <&cpg CPG_MOD 619>; + dmas = <&dmac0 0x43>, <&dmac0 0x42>, + <&dmac1 0x43>, <&dmac1 0x42>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 619>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + msiof2: spi@e6c00000 { + compatible = "renesas,msiof-r8a779f0", + "renesas,rcar-gen4-msiof"; + reg = <0 0xe6c00000 0 0x0064>; + interrupts = ; + clocks = <&cpg CPG_MOD 620>; + dmas = <&dmac0 0x45>, <&dmac0 0x44>, + <&dmac1 0x45>, <&dmac1 0x44>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 620>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + msiof3: spi@e6c10000 { + compatible = "renesas,msiof-r8a779f0", + "renesas,rcar-gen4-msiof"; + reg = <0 0xe6c10000 0 0x0064>; + interrupts = ; + clocks = <&cpg CPG_MOD 621>; + dmas = <&dmac0 0x47>, <&dmac0 0x46>, + <&dmac1 0x47>, <&dmac1 0x46>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 621>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + dmac0: dma-controller@e7350000 { compatible = "renesas,dmac-r8a779f0", "renesas,rcar-gen4-dmac"; From c77543ae7b168eab0686579c7dc9e7bd21298de2 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Mon, 29 Aug 2022 22:51:28 +0100 Subject: [PATCH 30/33] arm64: dts: renesas: Drop clock-names property from RPC node With 'unevaluatedProperties' support implemented, there are a number of warnings when running dtbs_check: arch/arm64/boot/dts/renesas/r8a774b1-hihope-rzg2n-rev2-ex-idk-1110wr.dtb: spi@ee200000: Unevaluated properties are not allowed ('clock-names' was unexpected) From schema: Documentation/devicetree/bindings/memory-controllers/renesas,rpc-if.yaml The main problem is that the DT bindings do not allow clock-names. So just drop the clock-names properties from the SoC DTSI files. Signed-off-by: Lad Prabhakar Link: https://lore.kernel.org/r/20220829215128.5983-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a774a1.dtsi | 1 - arch/arm64/boot/dts/renesas/r8a774b1.dtsi | 1 - arch/arm64/boot/dts/renesas/r8a774c0.dtsi | 1 - arch/arm64/boot/dts/renesas/r8a774e1.dtsi | 1 - arch/arm64/boot/dts/renesas/r8a77970.dtsi | 1 - arch/arm64/boot/dts/renesas/r8a77980.dtsi | 1 - arch/arm64/boot/dts/renesas/r8a779a0.dtsi | 1 - 7 files changed, 7 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi index aec62c93f9a3..7e643243c3be 100644 --- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi @@ -2323,7 +2323,6 @@ rpc: spi@ee200000 { reg-names = "regs", "dirmap", "wbuf"; interrupts = ; clocks = <&cpg CPG_MOD 917>; - clock-names = "rpc"; power-domains = <&sysc R8A774A1_PD_ALWAYS_ON>; resets = <&cpg 917>; #address-cells = <1>; diff --git a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi index f62d95760e82..d541b48c7e38 100644 --- a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi @@ -2191,7 +2191,6 @@ rpc: spi@ee200000 { reg-names = "regs", "dirmap", "wbuf"; interrupts = ; clocks = <&cpg CPG_MOD 917>; - clock-names = "rpc"; power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; resets = <&cpg 917>; #address-cells = <1>; diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi index c563d26a7a71..151e32ac0368 100644 --- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi @@ -1671,7 +1671,6 @@ rpc: spi@ee200000 { reg-names = "regs", "dirmap", "wbuf"; interrupts = ; clocks = <&cpg CPG_MOD 917>; - clock-names = "rpc"; power-domains = <&sysc R8A774C0_PD_ALWAYS_ON>; resets = <&cpg 917>; #address-cells = <1>; diff --git a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi index 3cb3b2e052c1..c5a0e7866b2f 100644 --- a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi @@ -2423,7 +2423,6 @@ rpc: spi@ee200000 { reg-names = "regs", "dirmap", "wbuf"; interrupts = ; clocks = <&cpg CPG_MOD 917>; - clock-names = "rpc"; power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; resets = <&cpg 917>; #address-cells = <1>; diff --git a/arch/arm64/boot/dts/renesas/r8a77970.dtsi b/arch/arm64/boot/dts/renesas/r8a77970.dtsi index 1df02facb796..ed6e2e47c604 100644 --- a/arch/arm64/boot/dts/renesas/r8a77970.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77970.dtsi @@ -1045,7 +1045,6 @@ rpc: spi@ee200000 { reg-names = "regs", "dirmap", "wbuf"; interrupts = ; clocks = <&cpg CPG_MOD 917>; - clock-names = "rpc"; power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; resets = <&cpg 917>; #address-cells = <1>; diff --git a/arch/arm64/boot/dts/renesas/r8a77980.dtsi b/arch/arm64/boot/dts/renesas/r8a77980.dtsi index a3af34191ca2..c4ac28a0f716 100644 --- a/arch/arm64/boot/dts/renesas/r8a77980.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77980.dtsi @@ -1350,7 +1350,6 @@ rpc: spi@ee200000 { reg-names = "regs", "dirmap", "wbuf"; interrupts = ; clocks = <&cpg CPG_MOD 917>; - clock-names = "rpc"; power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; resets = <&cpg 917>; #address-cells = <1>; diff --git a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi index 3e1557a5b5e1..8539013f5870 100644 --- a/arch/arm64/boot/dts/renesas/r8a779a0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779a0.dtsi @@ -2086,7 +2086,6 @@ rpc: spi@ee200000 { reg-names = "regs", "dirmap", "wbuf"; interrupts = ; clocks = <&cpg CPG_MOD 629>; - clock-names = "rpc"; power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; resets = <&cpg 629>; #address-cells = <1>; From 33eef075290215989b0c5430d8f696e21af29e0f Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Mon, 29 Aug 2022 23:49:41 +0000 Subject: [PATCH 31/33] arm64: dts: renesas: Add condor-common.dtsi We have V3H Condor board, and will have V3H2 Condor-I board. This patch adds condor-common.dtsi to share the common settings between these boards. Signed-off-by: Kuninori Morimoto Link: https://lore.kernel.org/r/871qsy625m.wl-kuninori.morimoto.gx@renesas.com Signed-off-by: Geert Uytterhoeven --- .../arm64/boot/dts/renesas/condor-common.dtsi | 548 ++++++++++++++++++ .../boot/dts/renesas/r8a77980-condor.dts | 540 +---------------- 2 files changed, 549 insertions(+), 539 deletions(-) create mode 100644 arch/arm64/boot/dts/renesas/condor-common.dtsi diff --git a/arch/arm64/boot/dts/renesas/condor-common.dtsi b/arch/arm64/boot/dts/renesas/condor-common.dtsi new file mode 100644 index 000000000000..dfbe35bf46e0 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/condor-common.dtsi @@ -0,0 +1,548 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the Condor board with R-Car V3H + * + * Copyright (C) 2018 Renesas Electronics Corp. + * Copyright (C) 2018 Cogent Embedded, Inc. + */ +#include + +/ { + aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; + serial0 = &scif0; + ethernet0 = &gether; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + d1_8v: regulator-2 { + compatible = "regulator-fixed"; + regulator-name = "D1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + d3_3v: regulator-0 { + compatible = "regulator-fixed"; + regulator-name = "D3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + hdmi-out { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con: endpoint { + remote-endpoint = <&adv7511_out>; + }; + }; + }; + + lvds-decoder { + compatible = "thine,thc63lvd1024"; + vcc-supply = <&d3_3v>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + thc63lvd1024_in: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + + port@2 { + reg = <2>; + thc63lvd1024_out: endpoint { + remote-endpoint = <&adv7511_in>; + }; + }; + }; + }; + + memory@48000000 { + device_type = "memory"; + /* first 128MB is reserved for secure area. */ + reg = <0 0x48000000 0 0x78000000>; + }; + + vddq_vin01: regulator-1 { + compatible = "regulator-fixed"; + regulator-name = "VDDQ_VIN01"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + x1_clk: x1-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <148500000>; + }; +}; + +&canfd { + pinctrl-0 = <&canfd0_pins>; + pinctrl-names = "default"; + status = "okay"; + + channel0 { + status = "okay"; + }; +}; + +&csi40 { + status = "okay"; + + ports { + port@0 { + csi40_in: endpoint { + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + remote-endpoint = <&max9286_out0>; + }; + }; + }; +}; + +&csi41 { + status = "okay"; + + ports { + port@0 { + csi41_in: endpoint { + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + remote-endpoint = <&max9286_out1>; + }; + }; + }; +}; + +&du { + clocks = <&cpg CPG_MOD 724>, + <&x1_clk>; + clock-names = "du.0", "dclkin.0"; + status = "okay"; +}; + +&extal_clk { + clock-frequency = <16666666>; +}; + +&extalr_clk { + clock-frequency = <32768>; +}; + +&gether { + pinctrl-0 = <&gether_pins>; + pinctrl-names = "default"; + + phy-mode = "rgmii-id"; + phy-handle = <&phy0>; + renesas,no-ether-link; + status = "okay"; + + phy0: ethernet-phy@0 { + compatible = "ethernet-phy-id0022.1622", + "ethernet-phy-ieee802.3-c22"; + rxc-skew-ps = <1500>; + reg = <0>; + interrupt-parent = <&gpio4>; + interrupts = <23 IRQ_TYPE_LEVEL_LOW>; + reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; + }; +}; + +&i2c0 { + pinctrl-0 = <&i2c0_pins>; + pinctrl-names = "default"; + + status = "okay"; + clock-frequency = <400000>; + + io_expander0: gpio@20 { + compatible = "onnn,pca9654"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + }; + + io_expander1: gpio@21 { + compatible = "onnn,pca9654"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + }; + + hdmi@39 { + compatible = "adi,adv7511w"; + reg = <0x39>; + interrupt-parent = <&gpio1>; + interrupts = <20 IRQ_TYPE_LEVEL_LOW>; + avdd-supply = <&d1_8v>; + dvdd-supply = <&d1_8v>; + pvdd-supply = <&d1_8v>; + bgvdd-supply = <&d1_8v>; + dvdd-3v-supply = <&d3_3v>; + + adi,input-depth = <8>; + adi,input-colorspace = "rgb"; + adi,input-clock = "1x"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + adv7511_in: endpoint { + remote-endpoint = <&thc63lvd1024_out>; + }; + }; + + port@1 { + reg = <1>; + adv7511_out: endpoint { + remote-endpoint = <&hdmi_con>; + }; + }; + }; + }; +}; + +&i2c1 { + pinctrl-0 = <&i2c1_pins>; + pinctrl-names = "default"; + + status = "okay"; + clock-frequency = <400000>; + + gmsl0: gmsl-deserializer@48 { + compatible = "maxim,max9286"; + reg = <0x48>; + + maxim,gpio-poc = <0 GPIO_ACTIVE_LOW>; + enable-gpios = <&io_expander0 0 GPIO_ACTIVE_HIGH>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + }; + + port@1 { + reg = <1>; + }; + + port@2 { + reg = <2>; + }; + + port@3 { + reg = <3>; + }; + + port@4 { + reg = <4>; + max9286_out0: endpoint { + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + remote-endpoint = <&csi40_in>; + }; + }; + }; + + i2c-mux { + #address-cells = <1>; + #size-cells = <0>; + + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + status = "disabled"; + }; + + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + status = "disabled"; + }; + + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + + status = "disabled"; + }; + + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + + status = "disabled"; + }; + }; + }; + + gmsl1: gmsl-deserializer@4a { + compatible = "maxim,max9286"; + reg = <0x4a>; + + maxim,gpio-poc = <0 GPIO_ACTIVE_LOW>; + enable-gpios = <&io_expander1 0 GPIO_ACTIVE_HIGH>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + }; + + port@1 { + reg = <1>; + }; + + port@2 { + reg = <2>; + }; + + port@3 { + reg = <3>; + }; + + port@4 { + reg = <4>; + max9286_out1: endpoint { + clock-lanes = <0>; + data-lanes = <1 2 3 4>; + remote-endpoint = <&csi41_in>; + }; + }; + }; + + i2c-mux { + #address-cells = <1>; + #size-cells = <0>; + + i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + status = "disabled"; + }; + + i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + status = "disabled"; + }; + + i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + + status = "disabled"; + }; + + i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + + status = "disabled"; + }; + }; + }; +}; + +&lvds0 { + status = "okay"; + + ports { + port@1 { + lvds0_out: endpoint { + remote-endpoint = <&thc63lvd1024_in>; + }; + }; + }; +}; + +&mmc0 { + pinctrl-0 = <&mmc_pins>; + pinctrl-1 = <&mmc_pins>; + pinctrl-names = "default", "state_uhs"; + + vmmc-supply = <&d3_3v>; + vqmmc-supply = <&vddq_vin01>; + mmc-hs200-1_8v; + bus-width = <8>; + no-sd; + no-sdio; + non-removable; + status = "okay"; +}; + +&pciec { + status = "okay"; +}; + +&pcie_bus_clk { + clock-frequency = <100000000>; +}; + +&pcie_phy { + status = "okay"; +}; + +&pfc { + canfd0_pins: canfd0 { + groups = "canfd0_data_a"; + function = "canfd0"; + }; + + gether_pins: gether { + groups = "gether_mdio_a", "gether_rgmii", + "gether_txcrefclk", "gether_txcrefclk_mega"; + function = "gether"; + }; + + i2c0_pins: i2c0 { + groups = "i2c0"; + function = "i2c0"; + }; + + i2c1_pins: i2c1 { + groups = "i2c1"; + function = "i2c1"; + }; + + mmc_pins: mmc { + groups = "mmc_data8", "mmc_ctrl", "mmc_ds"; + function = "mmc"; + power-source = <1800>; + }; + + qspi0_pins: qspi0 { + groups = "qspi0_ctrl", "qspi0_data4"; + function = "qspi0"; + }; + + scif0_pins: scif0 { + groups = "scif0_data"; + function = "scif0"; + }; + + scif_clk_pins: scif_clk { + groups = "scif_clk_b"; + function = "scif_clk"; + }; +}; + +&rpc { + pinctrl-0 = <&qspi0_pins>; + pinctrl-names = "default"; + + status = "okay"; + + flash@0 { + compatible = "spansion,s25fs512s", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <50000000>; + spi-rx-bus-width = <4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + bootparam@0 { + reg = <0x00000000 0x040000>; + read-only; + }; + cr7@40000 { + reg = <0x00040000 0x080000>; + read-only; + }; + cert_header_sa3@c0000 { + reg = <0x000c0000 0x080000>; + read-only; + }; + bl2@140000 { + reg = <0x00140000 0x040000>; + read-only; + }; + cert_header_sa6@180000 { + reg = <0x00180000 0x040000>; + read-only; + }; + bl31@1c0000 { + reg = <0x001c0000 0x460000>; + read-only; + }; + uboot@640000 { + reg = <0x00640000 0x0c0000>; + read-only; + }; + uboot-env@700000 { + reg = <0x00700000 0x040000>; + read-only; + }; + dtb@740000 { + reg = <0x00740000 0x080000>; + }; + kernel@7c0000 { + reg = <0x007c0000 0x1400000>; + }; + user@1bc0000 { + reg = <0x01bc0000 0x2440000>; + }; + }; + }; +}; + +&rwdt { + timeout-sec = <60>; + status = "okay"; +}; + +&scif0 { + pinctrl-0 = <&scif0_pins>, <&scif_clk_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&scif_clk { + clock-frequency = <14745600>; +}; diff --git a/arch/arm64/boot/dts/renesas/r8a77980-condor.dts b/arch/arm64/boot/dts/renesas/r8a77980-condor.dts index 981cf4db0e54..1d326552e2fa 100644 --- a/arch/arm64/boot/dts/renesas/r8a77980-condor.dts +++ b/arch/arm64/boot/dts/renesas/r8a77980-condor.dts @@ -8,547 +8,9 @@ /dts-v1/; #include "r8a77980.dtsi" -#include +#include "condor-common.dtsi" / { model = "Renesas Condor board based on r8a77980"; compatible = "renesas,condor", "renesas,r8a77980"; - - aliases { - i2c0 = &i2c0; - i2c1 = &i2c1; - i2c2 = &i2c2; - i2c3 = &i2c3; - i2c4 = &i2c4; - i2c5 = &i2c5; - serial0 = &scif0; - ethernet0 = &gether; - }; - - chosen { - stdout-path = "serial0:115200n8"; - }; - - d1_8v: regulator-2 { - compatible = "regulator-fixed"; - regulator-name = "D1.8V"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - d3_3v: regulator-0 { - compatible = "regulator-fixed"; - regulator-name = "D3.3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-boot-on; - regulator-always-on; - }; - - hdmi-out { - compatible = "hdmi-connector"; - type = "a"; - - port { - hdmi_con: endpoint { - remote-endpoint = <&adv7511_out>; - }; - }; - }; - - lvds-decoder { - compatible = "thine,thc63lvd1024"; - vcc-supply = <&d3_3v>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - thc63lvd1024_in: endpoint { - remote-endpoint = <&lvds0_out>; - }; - }; - - port@2 { - reg = <2>; - thc63lvd1024_out: endpoint { - remote-endpoint = <&adv7511_in>; - }; - }; - }; - }; - - memory@48000000 { - device_type = "memory"; - /* first 128MB is reserved for secure area. */ - reg = <0 0x48000000 0 0x78000000>; - }; - - vddq_vin01: regulator-1 { - compatible = "regulator-fixed"; - regulator-name = "VDDQ_VIN01"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-boot-on; - regulator-always-on; - }; - - x1_clk: x1-clock { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <148500000>; - }; -}; - -&canfd { - pinctrl-0 = <&canfd0_pins>; - pinctrl-names = "default"; - status = "okay"; - - channel0 { - status = "okay"; - }; -}; - -&csi40 { - status = "okay"; - - ports { - port@0 { - csi40_in: endpoint { - clock-lanes = <0>; - data-lanes = <1 2 3 4>; - remote-endpoint = <&max9286_out0>; - }; - }; - }; -}; - -&csi41 { - status = "okay"; - - ports { - port@0 { - csi41_in: endpoint { - clock-lanes = <0>; - data-lanes = <1 2 3 4>; - remote-endpoint = <&max9286_out1>; - }; - }; - }; -}; - -&du { - clocks = <&cpg CPG_MOD 724>, - <&x1_clk>; - clock-names = "du.0", "dclkin.0"; - status = "okay"; -}; - -&extal_clk { - clock-frequency = <16666666>; -}; - -&extalr_clk { - clock-frequency = <32768>; -}; - -&gether { - pinctrl-0 = <&gether_pins>; - pinctrl-names = "default"; - - phy-mode = "rgmii-id"; - phy-handle = <&phy0>; - renesas,no-ether-link; - status = "okay"; - - phy0: ethernet-phy@0 { - compatible = "ethernet-phy-id0022.1622", - "ethernet-phy-ieee802.3-c22"; - rxc-skew-ps = <1500>; - reg = <0>; - interrupt-parent = <&gpio4>; - interrupts = <23 IRQ_TYPE_LEVEL_LOW>; - reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; - }; -}; - -&i2c0 { - pinctrl-0 = <&i2c0_pins>; - pinctrl-names = "default"; - - status = "okay"; - clock-frequency = <400000>; - - io_expander0: gpio@20 { - compatible = "onnn,pca9654"; - reg = <0x20>; - gpio-controller; - #gpio-cells = <2>; - }; - - io_expander1: gpio@21 { - compatible = "onnn,pca9654"; - reg = <0x21>; - gpio-controller; - #gpio-cells = <2>; - }; - - hdmi@39 { - compatible = "adi,adv7511w"; - reg = <0x39>; - interrupt-parent = <&gpio1>; - interrupts = <20 IRQ_TYPE_LEVEL_LOW>; - avdd-supply = <&d1_8v>; - dvdd-supply = <&d1_8v>; - pvdd-supply = <&d1_8v>; - bgvdd-supply = <&d1_8v>; - dvdd-3v-supply = <&d3_3v>; - - adi,input-depth = <8>; - adi,input-colorspace = "rgb"; - adi,input-clock = "1x"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - adv7511_in: endpoint { - remote-endpoint = <&thc63lvd1024_out>; - }; - }; - - port@1 { - reg = <1>; - adv7511_out: endpoint { - remote-endpoint = <&hdmi_con>; - }; - }; - }; - }; -}; - -&i2c1 { - pinctrl-0 = <&i2c1_pins>; - pinctrl-names = "default"; - - status = "okay"; - clock-frequency = <400000>; - - gmsl0: gmsl-deserializer@48 { - compatible = "maxim,max9286"; - reg = <0x48>; - - maxim,gpio-poc = <0 GPIO_ACTIVE_LOW>; - enable-gpios = <&io_expander0 0 GPIO_ACTIVE_HIGH>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - }; - - port@1 { - reg = <1>; - }; - - port@2 { - reg = <2>; - }; - - port@3 { - reg = <3>; - }; - - port@4 { - reg = <4>; - max9286_out0: endpoint { - clock-lanes = <0>; - data-lanes = <1 2 3 4>; - remote-endpoint = <&csi40_in>; - }; - }; - }; - - i2c-mux { - #address-cells = <1>; - #size-cells = <0>; - - i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - status = "disabled"; - }; - - i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - status = "disabled"; - }; - - i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - - status = "disabled"; - }; - - i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - - status = "disabled"; - }; - }; - }; - - gmsl1: gmsl-deserializer@4a { - compatible = "maxim,max9286"; - reg = <0x4a>; - - maxim,gpio-poc = <0 GPIO_ACTIVE_LOW>; - enable-gpios = <&io_expander1 0 GPIO_ACTIVE_HIGH>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - }; - - port@1 { - reg = <1>; - }; - - port@2 { - reg = <2>; - }; - - port@3 { - reg = <3>; - }; - - port@4 { - reg = <4>; - max9286_out1: endpoint { - clock-lanes = <0>; - data-lanes = <1 2 3 4>; - remote-endpoint = <&csi41_in>; - }; - }; - }; - - i2c-mux { - #address-cells = <1>; - #size-cells = <0>; - - i2c@0 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - status = "disabled"; - }; - - i2c@1 { - #address-cells = <1>; - #size-cells = <0>; - reg = <1>; - - status = "disabled"; - }; - - i2c@2 { - #address-cells = <1>; - #size-cells = <0>; - reg = <2>; - - status = "disabled"; - }; - - i2c@3 { - #address-cells = <1>; - #size-cells = <0>; - reg = <3>; - - status = "disabled"; - }; - }; - }; -}; - -&lvds0 { - status = "okay"; - - ports { - port@1 { - lvds0_out: endpoint { - remote-endpoint = <&thc63lvd1024_in>; - }; - }; - }; -}; - -&mmc0 { - pinctrl-0 = <&mmc_pins>; - pinctrl-1 = <&mmc_pins>; - pinctrl-names = "default", "state_uhs"; - - vmmc-supply = <&d3_3v>; - vqmmc-supply = <&vddq_vin01>; - mmc-hs200-1_8v; - bus-width = <8>; - no-sd; - no-sdio; - non-removable; - status = "okay"; -}; - -&pciec { - status = "okay"; -}; - -&pcie_bus_clk { - clock-frequency = <100000000>; -}; - -&pcie_phy { - status = "okay"; -}; - -&pfc { - canfd0_pins: canfd0 { - groups = "canfd0_data_a"; - function = "canfd0"; - }; - - gether_pins: gether { - groups = "gether_mdio_a", "gether_rgmii", - "gether_txcrefclk", "gether_txcrefclk_mega"; - function = "gether"; - }; - - i2c0_pins: i2c0 { - groups = "i2c0"; - function = "i2c0"; - }; - - i2c1_pins: i2c1 { - groups = "i2c1"; - function = "i2c1"; - }; - - mmc_pins: mmc { - groups = "mmc_data8", "mmc_ctrl", "mmc_ds"; - function = "mmc"; - power-source = <1800>; - }; - - qspi0_pins: qspi0 { - groups = "qspi0_ctrl", "qspi0_data4"; - function = "qspi0"; - }; - - scif0_pins: scif0 { - groups = "scif0_data"; - function = "scif0"; - }; - - scif_clk_pins: scif_clk { - groups = "scif_clk_b"; - function = "scif_clk"; - }; -}; - -&rpc { - pinctrl-0 = <&qspi0_pins>; - pinctrl-names = "default"; - - status = "okay"; - - flash@0 { - compatible = "spansion,s25fs512s", "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <50000000>; - spi-rx-bus-width = <4>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - bootparam@0 { - reg = <0x00000000 0x040000>; - read-only; - }; - cr7@40000 { - reg = <0x00040000 0x080000>; - read-only; - }; - cert_header_sa3@c0000 { - reg = <0x000c0000 0x080000>; - read-only; - }; - bl2@140000 { - reg = <0x00140000 0x040000>; - read-only; - }; - cert_header_sa6@180000 { - reg = <0x00180000 0x040000>; - read-only; - }; - bl31@1c0000 { - reg = <0x001c0000 0x460000>; - read-only; - }; - uboot@640000 { - reg = <0x00640000 0x0c0000>; - read-only; - }; - uboot-env@700000 { - reg = <0x00700000 0x040000>; - read-only; - }; - dtb@740000 { - reg = <0x00740000 0x080000>; - }; - kernel@7c0000 { - reg = <0x007c0000 0x1400000>; - }; - user@1bc0000 { - reg = <0x01bc0000 0x2440000>; - }; - }; - }; -}; - -&rwdt { - timeout-sec = <60>; - status = "okay"; -}; - -&scif0 { - pinctrl-0 = <&scif0_pins>, <&scif_clk_pins>; - pinctrl-names = "default"; - - status = "okay"; -}; - -&scif_clk { - clock-frequency = <14745600>; }; From 6f06a74d7d8913288771839e86c3f7f3542768cf Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Mon, 29 Aug 2022 23:49:52 +0000 Subject: [PATCH 32/33] arm64: dts: renesas: Add r8a77980a.dtsi This patch adds r8a77980A V3H2 (= r8a77980 ES2) basic SoC support. It is using r8a77980 (= V3H) setting as-is for now. Signed-off-by: Kuninori Morimoto Link: https://lore.kernel.org/r/87zgfm4nkw.wl-kuninori.morimoto.gx@renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/r8a77980a.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/r8a77980a.dtsi diff --git a/arch/arm64/boot/dts/renesas/r8a77980a.dtsi b/arch/arm64/boot/dts/renesas/r8a77980a.dtsi new file mode 100644 index 000000000000..25b2d27b6167 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a77980a.dtsi @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: (GPL-2.0 or MIT) +/* + * Device Tree Source for the R-Car V3H2 (R8A77980A) SoC + * + * Copyright (C) 2022 Renesas Electronics Corp. + */ +#include "r8a77980.dtsi" + +/ { + compatible = "renesas,r8a77980a", "renesas,r8a77980"; +}; From 6f67580ca9edb33a95897d8c0056b961cbd2aeac Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Mon, 29 Aug 2022 23:49:59 +0000 Subject: [PATCH 33/33] arm64: dts: renesas: Add V3H2 Condor-I board support This patch adds r8a77980A V3H2 (= r8a77980 ES2) Condor-I board basic support. Signed-off-by: Andrey Dolnikov Signed-off-by: Valentine Barshak Signed-off-by: Koji Matsuoka Signed-off-by: Kuninori Morimoto Link: https://lore.kernel.org/r/87y1v64nko.wl-kuninori.morimoto.gx@renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/Makefile | 1 + .../arm64/boot/dts/renesas/r8a77980a-condor-i.dts | 15 +++++++++++++++ 2 files changed, 16 insertions(+) create mode 100644 arch/arm64/boot/dts/renesas/r8a77980a-condor-i.dts diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile index 7a647860ef35..0699b51c1247 100644 --- a/arch/arm64/boot/dts/renesas/Makefile +++ b/arch/arm64/boot/dts/renesas/Makefile @@ -56,6 +56,7 @@ dtb-$(CONFIG_ARCH_R8A77970) += r8a77970-v3msk.dtb dtb-$(CONFIG_ARCH_R8A77980) += r8a77980-condor.dtb dtb-$(CONFIG_ARCH_R8A77980) += r8a77980-v3hsk.dtb +dtb-$(CONFIG_ARCH_R8A77980) += r8a77980a-condor-i.dtb dtb-$(CONFIG_ARCH_R8A77990) += r8a77990-ebisu.dtb diff --git a/arch/arm64/boot/dts/renesas/r8a77980a-condor-i.dts b/arch/arm64/boot/dts/renesas/r8a77980a-condor-i.dts new file mode 100644 index 000000000000..9f488dea0f34 --- /dev/null +++ b/arch/arm64/boot/dts/renesas/r8a77980a-condor-i.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Device Tree Source for the Condor-I board on r8a77980A (ES2.0) + * + * Copyright (C) 2022 Renesas Electronics Corp. + */ + +/dts-v1/; +#include "r8a77980a.dtsi" +#include "condor-common.dtsi" + +/ { + model = "Renesas Condor-I board based on r8a77980A (ES2.0)"; + compatible = "renesas,condor-i", "renesas,r8a77980a", "renesas,r8a77980"; +};