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riscv: sophgo: dts: Add spi controller for SG2042

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Add spi controllers for SG2042.

SG2042 uses the upstreamed Synopsys DW SPI IP.

Signed-off-by: Zixian Zeng <sycamoremoon376@gmail.com>
Link: https://lore.kernel.org/r/20250425-sfg-spi-v6-3-2dbe7bb46013@gmail.com
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>
This commit is contained in:
Zixian Zeng
2025-04-25 10:28:14 +08:00
committed by Inochi Amaoto
parent 1cb666ec5a
commit 73ab31a8f3
1 changed files with 26 additions and 0 deletions
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26
arch/riscv/boot/dts/sophgo/sg2042.dtsi
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@@ -543,6 +543,32 @@ uart0: serial@7040000000 {
status = "disabled";
};
spi0: spi@7040004000 {
compatible = "sophgo,sg2042-spi", "snps,dw-apb-ssi";
reg = <0x70 0x40004000 0x00 0x1000>;
clocks = <&clkgen GATE_CLK_APB_SPI>;
interrupt-parent = <&intc>;
interrupts = <110 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
num-cs = <2>;
resets = <&rstgen RST_SPI0>;
status = "disabled";
};
spi1: spi@7040005000 {
compatible = "sophgo,sg2042-spi", "snps,dw-apb-ssi";
reg = <0x70 0x40005000 0x00 0x1000>;
clocks = <&clkgen GATE_CLK_APB_SPI>;
interrupt-parent = <&intc>;
interrupts = <111 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
num-cs = <2>;
resets = <&rstgen RST_SPI1>;
status = "disabled";
};
emmc: mmc@704002a000 {
compatible = "sophgo,sg2042-dwcmshc";
reg = <0x70 0x4002a000 0x0 0x1000>;