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synced 2026-08-30 11:03:07 -04:00
pinctrl: airoha: an7581: fix mux/conf of pcie_reset pins
In the an7581 case
* gpio47 and pcie_reset0 shares pin 60,
* gpio48 and pcie_reset1 shares pin 61,
* gpio49 and pcie_reset2 shares pin 62.
but current driver treat them as pins 61--63. This is wrong.
Also current an7581 pinmux implementation have following issues:
* current pcie_reset pin function actually sets corresponding
pins as gpios.
* there is no proper way to set pcie_reset pins as gpios.
* there is no way to set pcie_reset pins as pwm.
This patch fixes above issues.
WARNING:
There is a contradiction in the Airoha documentation. AN7581 programming
guide claims:
- gpio44 and pcie_reset0 shares the same pin
- gpio45 and pcie_reset1 shares the same pin
- gpio46 and pcie_reset2 shares the same pin
While AN7581 datasheet claims:
- gpio47 and pcie_reset0 shares the same pin
- gpio48 and pcie_reset1 shares the same pin
- gpio49 and pcie_reset2 shares the same pin
The datasheet should be considered as a more reliable source.
Thanks to Benjamin Larsson for clarification.
Fixes: 1c8ace2d07 ("pinctrl: airoha: Add support for EN7581 SoC")
Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>
Signed-off-by: Linus Walleij <linusw@kernel.org>
This commit is contained in:
Mikhail Kshevetskiy
committed by
Linus Walleij
Linus Walleij
parent
fdce588071
commit
739bc85aed
@@ -470,9 +470,9 @@ static struct pinctrl_pin_desc en7581_pinctrl_pins[] = {
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PINCTRL_PIN(57, "gpio44"),
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PINCTRL_PIN(58, "gpio45"),
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PINCTRL_PIN(59, "gpio46"),
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PINCTRL_PIN(61, "pcie_reset0"),
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PINCTRL_PIN(62, "pcie_reset1"),
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PINCTRL_PIN(63, "pcie_reset2"),
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PINCTRL_PIN(60, "pcie_reset0"),
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PINCTRL_PIN(61, "pcie_reset1"),
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PINCTRL_PIN(62, "pcie_reset2"),
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};
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static const int en7581_pon_pins[] = { 49, 50, 51, 52, 53, 54 };
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@@ -555,9 +555,12 @@ static const int en7581_gpio43_pins[] = { 56 };
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static const int en7581_gpio44_pins[] = { 57 };
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static const int en7581_gpio45_pins[] = { 58 };
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static const int en7581_gpio46_pins[] = { 59 };
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static const int en7581_pcie_reset0_pins[] = { 61 };
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static const int en7581_pcie_reset1_pins[] = { 62 };
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static const int en7581_pcie_reset2_pins[] = { 63 };
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static const int en7581_gpio47_pins[] = { 60 };
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static const int en7581_gpio48_pins[] = { 61 };
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static const int en7581_gpio49_pins[] = { 62 };
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static const int en7581_pcie_reset0_pins[] = { 60 };
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static const int en7581_pcie_reset1_pins[] = { 61 };
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static const int en7581_pcie_reset2_pins[] = { 62 };
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static const struct pingroup en7581_pinctrl_groups[] = {
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PINCTRL_PIN_GROUP("pon", en7581_pon),
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@@ -640,6 +643,9 @@ static const struct pingroup en7581_pinctrl_groups[] = {
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PINCTRL_PIN_GROUP("gpio44", en7581_gpio44),
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PINCTRL_PIN_GROUP("gpio45", en7581_gpio45),
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PINCTRL_PIN_GROUP("gpio46", en7581_gpio46),
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PINCTRL_PIN_GROUP("gpio47", en7581_gpio47),
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PINCTRL_PIN_GROUP("gpio48", en7581_gpio48),
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PINCTRL_PIN_GROUP("gpio49", en7581_gpio49),
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PINCTRL_PIN_GROUP("pcie_reset0", en7581_pcie_reset0),
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PINCTRL_PIN_GROUP("pcie_reset1", en7581_pcie_reset1),
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PINCTRL_PIN_GROUP("pcie_reset2", en7581_pcie_reset2),
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@@ -883,6 +889,7 @@ static const char *const an7583_pcm_spi_groups[] = { "pcm_spi",
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static const char *const i2s_groups[] = { "i2s" };
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static const char *const emmc_groups[] = { "emmc" };
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static const char *const pnand_groups[] = { "pnand" };
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static const char *const gpio_groups[] = { "gpio47", "gpio48", "gpio49" };
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static const char *const pcie_reset_groups[] = { "pcie_reset0", "pcie_reset1",
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"pcie_reset2" };
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static const char *const an7583_pcie_reset_groups[] = { "pcie_reset0", "pcie_reset1" };
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@@ -907,7 +914,8 @@ static const char *const pwm_groups[] = { "gpio0", "gpio1",
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"gpio40", "gpio41",
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"gpio42", "gpio43",
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"gpio44", "gpio45",
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"gpio46" };
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"gpio46", "gpio47",
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"gpio48", "gpio49" };
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static const char *const an7583_pwm_groups[] = { "gpio0", "gpio1",
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"gpio2", "gpio3",
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"gpio4", "gpio5",
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@@ -1406,6 +1414,45 @@ static const struct airoha_pinctrl_func_group pnand_func_group[] = {
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},
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};
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#define AIROHA_PINCTRL_GPIO(gpio, mux_val) \
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{ \
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.name = (gpio), \
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.regmap[0] = { \
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AIROHA_FUNC_MUX, \
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REG_GPIO_PON_MODE, \
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(mux_val), \
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(mux_val) \
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}, \
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.regmap_size = 1, \
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}
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#define AIROHA_PINCTRL_GPIO_EXT(gpio, mux_val, smux_val) \
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{ \
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.name = (gpio), \
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.regmap[0] = { \
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AIROHA_FUNC_PWM_EXT_MUX, \
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REG_GPIO_FLASH_MODE_CFG_EXT, \
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(mux_val), \
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0 \
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}, \
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.regmap[1] = { \
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AIROHA_FUNC_MUX, \
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REG_GPIO_PON_MODE, \
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(smux_val), \
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(smux_val) \
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}, \
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.regmap_size = 2, \
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}
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static const struct airoha_pinctrl_func_group gpio_func_group[] = {
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AIROHA_PINCTRL_GPIO_EXT("gpio47", GPIO47_FLASH_MODE_CFG,
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GPIO_PCIE_RESET0_MASK),
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AIROHA_PINCTRL_GPIO_EXT("gpio48", GPIO48_FLASH_MODE_CFG,
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GPIO_PCIE_RESET1_MASK),
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AIROHA_PINCTRL_GPIO_EXT("gpio49", GPIO49_FLASH_MODE_CFG,
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GPIO_PCIE_RESET2_MASK),
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};
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static const struct airoha_pinctrl_func_group pcie_reset_func_group[] = {
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{
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.name = "pcie_reset0",
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@@ -1413,7 +1460,7 @@ static const struct airoha_pinctrl_func_group pcie_reset_func_group[] = {
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AIROHA_FUNC_MUX,
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REG_GPIO_PON_MODE,
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GPIO_PCIE_RESET0_MASK,
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GPIO_PCIE_RESET0_MASK
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0
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},
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.regmap_size = 1,
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}, {
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@@ -1422,7 +1469,7 @@ static const struct airoha_pinctrl_func_group pcie_reset_func_group[] = {
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AIROHA_FUNC_MUX,
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REG_GPIO_PON_MODE,
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GPIO_PCIE_RESET1_MASK,
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GPIO_PCIE_RESET1_MASK
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0
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},
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.regmap_size = 1,
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}, {
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@@ -1431,7 +1478,7 @@ static const struct airoha_pinctrl_func_group pcie_reset_func_group[] = {
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AIROHA_FUNC_MUX,
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REG_GPIO_PON_MODE,
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GPIO_PCIE_RESET2_MASK,
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GPIO_PCIE_RESET2_MASK
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0
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},
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.regmap_size = 1,
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},
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@@ -1484,6 +1531,24 @@ static const struct airoha_pinctrl_func_group an7583_pcie_reset_func_group[] = {
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.regmap_size = 1, \
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} \
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#define AIROHA_PINCTRL_PWM_EXT_SEC(gpio, mux_val, smux_val) \
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{ \
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.name = (gpio), \
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.regmap[0] = { \
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AIROHA_FUNC_PWM_EXT_MUX, \
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REG_GPIO_FLASH_MODE_CFG_EXT, \
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(mux_val), \
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(mux_val) \
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}, \
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.regmap[1] = { \
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AIROHA_FUNC_MUX, \
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REG_GPIO_PON_MODE, \
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(smux_val), \
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(smux_val) \
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}, \
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.regmap_size = 2, \
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}
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static const struct airoha_pinctrl_func_group pwm_func_group[] = {
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AIROHA_PINCTRL_PWM("gpio0", GPIO0_FLASH_MODE_CFG),
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AIROHA_PINCTRL_PWM("gpio1", GPIO1_FLASH_MODE_CFG),
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@@ -1528,6 +1593,12 @@ static const struct airoha_pinctrl_func_group pwm_func_group[] = {
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AIROHA_PINCTRL_PWM_EXT("gpio44", GPIO44_FLASH_MODE_CFG),
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AIROHA_PINCTRL_PWM_EXT("gpio45", GPIO45_FLASH_MODE_CFG),
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AIROHA_PINCTRL_PWM_EXT("gpio46", GPIO46_FLASH_MODE_CFG),
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AIROHA_PINCTRL_PWM_EXT_SEC("gpio47", GPIO47_FLASH_MODE_CFG,
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GPIO_PCIE_RESET0_MASK),
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AIROHA_PINCTRL_PWM_EXT_SEC("gpio48", GPIO48_FLASH_MODE_CFG,
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GPIO_PCIE_RESET1_MASK),
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AIROHA_PINCTRL_PWM_EXT_SEC("gpio49", GPIO49_FLASH_MODE_CFG,
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GPIO_PCIE_RESET2_MASK),
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};
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static const struct airoha_pinctrl_func_group an7583_pwm_func_group[] = {
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@@ -1804,6 +1875,7 @@ static const struct airoha_pinctrl_func en7581_pinctrl_funcs[] = {
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PINCTRL_FUNC_DESC("i2s", i2s),
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PINCTRL_FUNC_DESC("emmc", emmc),
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PINCTRL_FUNC_DESC("pnand", pnand),
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PINCTRL_FUNC_DESC("gpio", gpio),
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PINCTRL_FUNC_DESC("pcie_reset", pcie_reset),
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PINCTRL_FUNC_DESC("pwm", pwm),
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PINCTRL_FUNC_DESC("phy1_led0", phy1_led0),
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@@ -1897,9 +1969,9 @@ static const struct airoha_pinctrl_conf en7581_pinctrl_pullup_conf[] = {
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PINCTRL_CONF_DESC(57, REG_GPIO_H_PU, BIT(12)),
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PINCTRL_CONF_DESC(58, REG_GPIO_H_PU, BIT(13)),
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PINCTRL_CONF_DESC(59, REG_GPIO_H_PU, BIT(14)),
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PINCTRL_CONF_DESC(61, REG_I2C_SDA_PU, PCIE0_RESET_PU_MASK),
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PINCTRL_CONF_DESC(62, REG_I2C_SDA_PU, PCIE1_RESET_PU_MASK),
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PINCTRL_CONF_DESC(63, REG_I2C_SDA_PU, PCIE2_RESET_PU_MASK),
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PINCTRL_CONF_DESC(60, REG_I2C_SDA_PU, PCIE0_RESET_PU_MASK),
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PINCTRL_CONF_DESC(61, REG_I2C_SDA_PU, PCIE1_RESET_PU_MASK),
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PINCTRL_CONF_DESC(62, REG_I2C_SDA_PU, PCIE2_RESET_PU_MASK),
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};
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static const struct airoha_pinctrl_conf an7583_pinctrl_pullup_conf[] = {
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@@ -2014,9 +2086,9 @@ static const struct airoha_pinctrl_conf en7581_pinctrl_pulldown_conf[] = {
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PINCTRL_CONF_DESC(57, REG_GPIO_H_PD, BIT(12)),
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PINCTRL_CONF_DESC(58, REG_GPIO_H_PD, BIT(13)),
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PINCTRL_CONF_DESC(59, REG_GPIO_H_PD, BIT(14)),
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PINCTRL_CONF_DESC(61, REG_I2C_SDA_PD, PCIE0_RESET_PD_MASK),
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PINCTRL_CONF_DESC(62, REG_I2C_SDA_PD, PCIE1_RESET_PD_MASK),
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PINCTRL_CONF_DESC(63, REG_I2C_SDA_PD, PCIE2_RESET_PD_MASK),
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PINCTRL_CONF_DESC(60, REG_I2C_SDA_PD, PCIE0_RESET_PD_MASK),
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PINCTRL_CONF_DESC(61, REG_I2C_SDA_PD, PCIE1_RESET_PD_MASK),
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PINCTRL_CONF_DESC(62, REG_I2C_SDA_PD, PCIE2_RESET_PD_MASK),
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};
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static const struct airoha_pinctrl_conf an7583_pinctrl_pulldown_conf[] = {
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@@ -2131,9 +2203,9 @@ static const struct airoha_pinctrl_conf en7581_pinctrl_drive_e2_conf[] = {
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PINCTRL_CONF_DESC(57, REG_GPIO_H_E2, BIT(12)),
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PINCTRL_CONF_DESC(58, REG_GPIO_H_E2, BIT(13)),
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PINCTRL_CONF_DESC(59, REG_GPIO_H_E2, BIT(14)),
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PINCTRL_CONF_DESC(61, REG_I2C_SDA_E2, PCIE0_RESET_E2_MASK),
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PINCTRL_CONF_DESC(62, REG_I2C_SDA_E2, PCIE1_RESET_E2_MASK),
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PINCTRL_CONF_DESC(63, REG_I2C_SDA_E2, PCIE2_RESET_E2_MASK),
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PINCTRL_CONF_DESC(60, REG_I2C_SDA_E2, PCIE0_RESET_E2_MASK),
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PINCTRL_CONF_DESC(61, REG_I2C_SDA_E2, PCIE1_RESET_E2_MASK),
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PINCTRL_CONF_DESC(62, REG_I2C_SDA_E2, PCIE2_RESET_E2_MASK),
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};
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static const struct airoha_pinctrl_conf an7583_pinctrl_drive_e2_conf[] = {
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@@ -2248,9 +2320,9 @@ static const struct airoha_pinctrl_conf en7581_pinctrl_drive_e4_conf[] = {
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PINCTRL_CONF_DESC(57, REG_GPIO_H_E4, BIT(12)),
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PINCTRL_CONF_DESC(58, REG_GPIO_H_E4, BIT(13)),
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PINCTRL_CONF_DESC(59, REG_GPIO_H_E4, BIT(14)),
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PINCTRL_CONF_DESC(61, REG_I2C_SDA_E4, PCIE0_RESET_E4_MASK),
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PINCTRL_CONF_DESC(62, REG_I2C_SDA_E4, PCIE1_RESET_E4_MASK),
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PINCTRL_CONF_DESC(63, REG_I2C_SDA_E4, PCIE2_RESET_E4_MASK),
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PINCTRL_CONF_DESC(60, REG_I2C_SDA_E4, PCIE0_RESET_E4_MASK),
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PINCTRL_CONF_DESC(61, REG_I2C_SDA_E4, PCIE1_RESET_E4_MASK),
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PINCTRL_CONF_DESC(62, REG_I2C_SDA_E4, PCIE2_RESET_E4_MASK),
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};
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static const struct airoha_pinctrl_conf an7583_pinctrl_drive_e4_conf[] = {
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@@ -2310,9 +2382,9 @@ static const struct airoha_pinctrl_conf an7583_pinctrl_drive_e4_conf[] = {
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};
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static const struct airoha_pinctrl_conf en7581_pinctrl_pcie_rst_od_conf[] = {
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PINCTRL_CONF_DESC(61, REG_PCIE_RESET_OD, PCIE0_RESET_OD_MASK),
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PINCTRL_CONF_DESC(62, REG_PCIE_RESET_OD, PCIE1_RESET_OD_MASK),
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PINCTRL_CONF_DESC(63, REG_PCIE_RESET_OD, PCIE2_RESET_OD_MASK),
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PINCTRL_CONF_DESC(60, REG_PCIE_RESET_OD, PCIE0_RESET_OD_MASK),
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PINCTRL_CONF_DESC(61, REG_PCIE_RESET_OD, PCIE1_RESET_OD_MASK),
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PINCTRL_CONF_DESC(62, REG_PCIE_RESET_OD, PCIE2_RESET_OD_MASK),
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};
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static const struct airoha_pinctrl_conf an7583_pinctrl_pcie_rst_od_conf[] = {
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