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riscv: dts: starfive: jh7110: Add watchdog node

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Add the watchdog node for the Starfive JH7110 SoC.

Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Reviewed-by: Walker Chen <walker.chen@starfivetech.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
This commit is contained in:
Xingyu Wu
2023-05-09 23:17:23 +08:00
committed by Conor Dooley
parent 435ac3fbfb
commit 6361b7de26
1 changed files with 10 additions and 0 deletions
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10
arch/riscv/boot/dts/starfive/jh7110.dtsi
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@@ -469,6 +469,16 @@ sysgpio: pinctrl@13040000 {
#gpio-cells = <2>;
};
watchdog@13070000 {
compatible = "starfive,jh7110-wdt";
reg = <0x0 0x13070000 0x0 0x10000>;
clocks = <&syscrg JH7110_SYSCLK_WDT_APB>,
<&syscrg JH7110_SYSCLK_WDT_CORE>;
clock-names = "apb", "core";
resets = <&syscrg JH7110_SYSRST_WDT_APB>,
<&syscrg JH7110_SYSRST_WDT_CORE>;
};
aoncrg: clock-controller@17000000 {
compatible = "starfive,jh7110-aoncrg";
reg = <0x0 0x17000000 0x0 0x10000>;