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riscv: dts: starfive: jh7100: Add watchdog node

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Add watchdog node for the StarFive JH7100 RISC-V SoC.

Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
This commit is contained in:
Xingyu Wu
2023-05-09 23:17:22 +08:00
committed by Conor Dooley
parent 6a887bcc41
commit 435ac3fbfb
1 changed files with 10 additions and 0 deletions
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10
arch/riscv/boot/dts/starfive/jh7100.dtsi
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@@ -238,5 +238,15 @@ i2c3: i2c@12460000 {
#size-cells = <0>;
status = "disabled";
};
watchdog@12480000 {
compatible = "starfive,jh7100-wdt";
reg = <0x0 0x12480000 0x0 0x10000>;
clocks = <&clkgen JH7100_CLK_WDTIMER_APB>,
<&clkgen JH7100_CLK_WDT_CORE>;
clock-names = "apb", "core";
resets = <&rstgen JH7100_RSTN_WDTIMER_APB>,
<&rstgen JH7100_RSTN_WDT>;
};
};
};