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arm64: dts: mediatek: mt8192: Add mfg_ref_sel clock to MFG0 domain

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The mfg_ref_sel clock is a mux used to switch between different "safe"
(and slower) clock sources for the GPU: this is used during MFGPLL
reconfiguration and eventually during idling at very low frequencies.

This clock getting turned off means that the GPU will occasionally be
unclocked, producing obvious consequences such as system crash or
unpredictable behavior: assigning it to the top level MFG power domain
will make sure that this stays on at all times during any operation on
the MFG domain (only GPU-related transactions).

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Tested-by: Chen-Yu Tsai <wenst@chromium.org>
Link: https://lore.kernel.org/r/20230301095523.428461-9-angelogioacchino.delregno@collabora.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
This commit is contained in:
AngeloGioacchino Del Regno
2023-03-01 10:55:12 +01:00
committed by Matthias Brugger
parent e12333451e
commit 61348fe9e7
1 changed files with 3 additions and 2 deletions
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5
arch/arm64/boot/dts/mediatek/mt8192.dtsi
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@@ -499,8 +499,9 @@ power-domain@MT8192_POWER_DOMAIN_CONN {
power-domain@MT8192_POWER_DOMAIN_MFG0 {
reg = <MT8192_POWER_DOMAIN_MFG0>;
clocks = <&topckgen CLK_TOP_MFG_PLL_SEL>;
clock-names = "mfg";
clocks = <&topckgen CLK_TOP_MFG_PLL_SEL>,
<&topckgen CLK_TOP_MFG_REF_SEL>;
clock-names = "mfg", "alt";
#address-cells = <1>;
#size-cells = <0>;
#power-domain-cells = <1>;