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drm/amd/display: Block ABM in case of eDP ODM

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[Why]
enable ODM on eDP panel with ABM will result in color difference
on the panel due to only one ABM module to set one pipe.

[How]
Block ABM in case of ODM enabled on eDP.

Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: Eric Yang <eric.yang2@amd.com>
Acked-by: Eryk Brol <eryk.brol@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Yongqiang Sun
2020-09-18 16:33:55 -04:00
committed by Alex Deucher
parent 7c4ed1df0a
commit 54e8094a76
6 changed files with 24 additions and 0 deletions
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1
drivers/gpu/drm/amd/display/dc/dc_stream.h
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@@ -45,6 +45,7 @@ struct dc_stream_status {
int audio_inst;
struct timing_sync_info timing_sync_info;
struct dc_plane_state *plane_states[MAX_SURFACE_NUM];
bool is_abm_supported;
};
// TODO: References to this needs to be removed..

15
drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hwseq.c
View File

@@ -223,3 +223,18 @@ bool dcn21_set_backlight_level(struct pipe_ctx *pipe_ctx,
return true;
}
bool dcn21_is_abm_supported(struct dc *dc,
struct dc_state *context, struct dc_stream_state *stream)
{
int i;
for (i = 0; i < dc->res_pool->pipe_count; i++) {
struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
if (pipe_ctx->stream == stream &&
(pipe_ctx->prev_odm_pipe == NULL && pipe_ctx->next_odm_pipe == NULL))
return true;
}
return false;
}

2
drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hwseq.h
View File

@@ -52,5 +52,7 @@ void dcn21_set_abm_immediate_disable(struct pipe_ctx *pipe_ctx);
bool dcn21_set_backlight_level(struct pipe_ctx *pipe_ctx,
uint32_t backlight_pwm_u16_16,
uint32_t frame_ramp);
bool dcn21_is_abm_supported(struct dc *dc,
struct dc_state *context, struct dc_stream_state *stream);
#endif /* __DC_HWSS_DCN21_H__ */

1
drivers/gpu/drm/amd/display/dc/dcn21/dcn21_init.c
View File

@@ -98,6 +98,7 @@ static const struct hw_sequencer_funcs dcn21_funcs = {
#ifndef TRIM_FSFT
.optimize_timing_for_fsft = dcn20_optimize_timing_for_fsft,
#endif
.is_abm_supported = dcn21_is_abm_supported,
};
static const struct hwseq_private_funcs dcn21_private_funcs = {

3
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hwseq.c
View File

@@ -617,6 +617,9 @@ void dcn30_init_hw(struct dc *dc)
if (hws->funcs.enable_power_gating_plane)
hws->funcs.enable_power_gating_plane(dc->hwseq, true);
if (!dcb->funcs->is_accelerated_mode(dcb) && dc->res_pool->hubbub->funcs->init_watermarks)
dc->res_pool->hubbub->funcs->init_watermarks(dc->res_pool->hubbub);
if (dc->clk_mgr->funcs->notify_wm_ranges)
dc->clk_mgr->funcs->notify_wm_ranges(dc->clk_mgr);

2
drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
View File

@@ -223,6 +223,8 @@ struct hw_sequencer_funcs {
bool (*apply_idle_power_optimizations)(struct dc *dc, bool enable);
#endif
bool (*is_abm_supported)(struct dc *dc,
struct dc_state *context, struct dc_stream_state *stream);
};
void color_space_to_black_color(