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drm/amd/display: Copy WM values from set A to other sets in hw_init

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[Why]
When we transfer the WM range table to SMU, they can perform a watermark
switch right away. This can be a problem if we're in not in accelerated mode
during hw_init as SMU may initiate a dummy p-state change before the rest
of the watermarks are programmed. Watermark set A is defined to be
sufficient for all cases, so we can copy the values from set A to all other
sets, avoiding any issues from SMU doing WM switches.

[How]
 - new hubbub func init_watermarks
 - copy register values from set A to all other sets
 - call init_watermarks before calling notify_wm_ranges

Signed-off-by: Joshua Aberback <joshua.aberback@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Eryk Brol <eryk.brol@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Joshua Aberback
2020-09-23 15:12:39 -04:00
committed by Alex Deucher
parent 3e19095534
commit 7c4ed1df0a
3 changed files with 47 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

43
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hubbub.c
View File

@@ -394,6 +394,48 @@ void hubbub3_force_pstate_change_control(struct hubbub *hubbub,
DCHUBBUB_ARB_ALLOW_PSTATE_CHANGE_FORCE_ENABLE, force);
}
/* Copy values from WM set A to all other sets */
void hubbub3_init_watermarks(struct hubbub *hubbub)
{
struct dcn20_hubbub *hubbub1 = TO_DCN20_HUBBUB(hubbub);
uint32_t reg;
reg = REG_READ(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A);
REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B, reg);
REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C, reg);
REG_WRITE(DCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D, reg);
reg = REG_READ(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A);
REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_B, reg);
REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_C, reg);
REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_FLIP_D, reg);
reg = REG_READ(DCHUBBUB_ARB_FRAC_URG_BW_NOM_A);
REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_NOM_B, reg);
REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_NOM_C, reg);
REG_WRITE(DCHUBBUB_ARB_FRAC_URG_BW_NOM_D, reg);
reg = REG_READ(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_A);
REG_WRITE(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_B, reg);
REG_WRITE(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_C, reg);
REG_WRITE(DCHUBBUB_ARB_REFCYC_PER_TRIP_TO_MEMORY_D, reg);
reg = REG_READ(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A);
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B, reg);
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C, reg);
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D, reg);
reg = REG_READ(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A);
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B, reg);
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C, reg);
REG_WRITE(DCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D, reg);
reg = REG_READ(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A);
REG_WRITE(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B, reg);
REG_WRITE(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C, reg);
REG_WRITE(DCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D, reg);
}
static const struct hubbub_funcs hubbub30_funcs = {
.update_dchub = hubbub2_update_dchub,
.init_dchub_sys_ctx = hubbub3_init_dchub_sys_ctx,
@@ -408,6 +450,7 @@ static const struct hubbub_funcs hubbub30_funcs = {
.is_allow_self_refresh_enabled = hubbub1_is_allow_self_refresh_enabled,
.force_wm_propagate_to_pipes = hubbub3_force_wm_propagate_to_pipes,
.force_pstate_change_control = hubbub3_force_pstate_change_control,
.init_watermarks = hubbub3_init_watermarks,
};
void hubbub3_construct(struct dcn20_hubbub *hubbub3,

2
drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hubbub.h
View File

@@ -119,4 +119,6 @@ bool hubbub3_program_watermarks(
void hubbub3_force_pstate_change_control(struct hubbub *hubbub,
bool force, bool allow);
void hubbub3_init_watermarks(struct hubbub *hubbub);
#endif

2
drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h
View File

@@ -155,6 +155,8 @@ struct hubbub_funcs {
#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
void (*force_pstate_change_control)(struct hubbub *hubbub, bool force, bool allow);
void (*init_watermarks)(struct hubbub *hubbub);
#endif
};