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Merge tag 'riscv-sophgo-dt-for-v6.13' of https://github.com/sophgo/linux into soc/dt

Browse Source 
RISC-V Devicetrees for v6.13

Sophgo:
Add pinctrl support for CV1800B & CV1812H.
Add SARADC support for CV1800B.
Add initial LicheeRV-Nano/SG2002.
Add emmc/sdio support for Huashan-Pi/CV1812H.
Add power-key support for PioneerBox/SG2042.

Signed-off-by: Chen Wang <unicorn_wang@outlook.com>

* tag 'riscv-sophgo-dt-for-v6.13' of https://github.com/sophgo/linux:
  riscv: dts: sophgo: Add emmc support for Huashan Pi
  riscv: dts: sophgo: Add sdio configuration for Huashan Pi
  riscv: dts: sophgo: fix pinctrl base-address
  riscv: sophgo: dts: add power key for pioneer box
  riscv: dts: sophgo: Add SARADC description for Sophgo CV1800B
  riscv: dts: sophgo: Add LicheeRV Nano board device tree
  riscv: dts: sophgo: Add initial SG2002 SoC device tree
  riscv: dts: sophgo: cv1812h: add pinctrl support
  riscv: dts: sophgo: cv1800b: add pinctrl support

Link: https://lore.kernel.org/r/MA0P287MB2822DC23E1EE47A5C7D41476FE532@MA0P287MB2822.INDP287.PROD.OUTLOOK.COM
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
2024-11-12 22:48:14 +01:00
parent bdcbb3f8ab b5cf65cc0f
commit 44533285bd
10 changed files with 300 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
arch/riscv/boot/dts/sophgo/Makefile
View File

@@ -1,4 +1,5 @@
# SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_ARCH_SOPHGO) += cv1800b-milkv-duo.dtb
dtb-$(CONFIG_ARCH_SOPHGO) += cv1812h-huashan-pi.dtb
dtb-$(CONFIG_ARCH_SOPHGO) += sg2002-licheerv-nano-b.dtb
dtb-$(CONFIG_ARCH_SOPHGO) += sg2042-milkv-pioneer.dtb

49
arch/riscv/boot/dts/sophgo/cv1800b-milkv-duo.dts
View File

@@ -39,7 +39,54 @@ &osc {
clock-frequency = <25000000>;
};
&pinctrl {
uart0_cfg: uart0-cfg {
uart0-pins {
pinmux = <PINMUX(PIN_UART0_TX, 0)>,
<PINMUX(PIN_UART0_RX, 0)>;
bias-pull-up;
drive-strength-microamp = <10800>;
power-source = <3300>;
};
};
sdhci0_cfg: sdhci0-cfg {
sdhci0-clk-pins {
pinmux = <PINMUX(PIN_SD0_CLK, 0)>;
bias-pull-up;
drive-strength-microamp = <16100>;
power-source = <3300>;
};
sdhci0-cmd-pins {
pinmux = <PINMUX(PIN_SD0_CMD, 0)>;
bias-pull-up;
drive-strength-microamp = <10800>;
power-source = <3300>;
};
sdhci0-data-pins {
pinmux = <PINMUX(PIN_SD0_D0, 0)>,
<PINMUX(PIN_SD0_D1, 0)>,
<PINMUX(PIN_SD0_D2, 0)>,
<PINMUX(PIN_SD0_D3, 0)>;
bias-pull-up;
drive-strength-microamp = <10800>;
power-source = <3300>;
};
sdhci0-cd-pins {
pinmux = <PINMUX(PIN_SD0_CD, 0)>;
bias-pull-up;
drive-strength-microamp = <10800>;
power-source = <3300>;
};
};
};
&sdhci0 {
pinctrl-0 = <&sdhci0_cfg>;
pinctrl-names = "default";
status = "okay";
bus-width = <4>;
no-1-8-v;
@@ -49,5 +96,7 @@ &sdhci0 {
};
&uart0 {
pinctrl-0 = <&uart0_cfg>;
pinctrl-names = "default";
status = "okay";
};

10
arch/riscv/boot/dts/sophgo/cv1800b.dtsi
View File

@@ -3,6 +3,7 @@
* Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
*/
#include <dt-bindings/pinctrl/pinctrl-cv1800b.h>
#include "cv18xx.dtsi"
/ {
@@ -12,6 +13,15 @@ memory@80000000 {
device_type = "memory";
reg = <0x80000000 0x4000000>;
};
soc {
pinctrl: pinctrl@3001000 {
compatible = "sophgo,cv1800b-pinctrl";
reg = <0x03001000 0x1000>,
<0x05027000 0x1000>;
reg-names = "sys", "rtc";
};
};
};
&plic {

23
arch/riscv/boot/dts/sophgo/cv1812h-huashan-pi.dts
View File

@@ -43,6 +43,18 @@ &osc {
clock-frequency = <25000000>;
};
&emmc {
status = "okay";
bus-width = <4>;
max-frequency = <200000000>;
mmc-ddr-1_8v;
mmc-ddr-3_3v;
mmc-hs200-1_8v;
no-sd;
no-sdio;
non-removable;
};
&sdhci0 {
status = "okay";
bus-width = <4>;
@@ -52,6 +64,17 @@ &sdhci0 {
disable-wp;
};
&sdhci1 {
status = "okay";
bus-width = <4>;
cap-sdio-irq;
max-frequency = <50000000>;
no-mmc;
no-sd;
disable-wp;
non-removable;
};
&uart0 {
status = "okay";
};

11
arch/riscv/boot/dts/sophgo/cv1812h.dtsi
View File

@@ -4,7 +4,9 @@
*/
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pinctrl/pinctrl-cv1812h.h>
#include "cv18xx.dtsi"
#include "cv181x.dtsi"
/ {
compatible = "sophgo,cv1812h";
@@ -13,6 +15,15 @@ memory@80000000 {
device_type = "memory";
reg = <0x80000000 0x10000000>;
};
soc {
pinctrl: pinctrl@3001000 {
compatible = "sophgo,cv1812h-pinctrl";
reg = <0x03001000 0x1000>,
<0x05027000 0x1000>;
reg-names = "sys", "rtc";
};
};
};
&plic {

21
arch/riscv/boot/dts/sophgo/cv181x.dtsi Normal file
View File

@@ -0,0 +1,21 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (C) 2024 Inochi Amaoto <inochiama@outlook.com>
*/
#include <dt-bindings/clock/sophgo,cv1800.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
soc {
emmc: mmc@4300000 {
compatible = "sophgo,cv1800b-dwcmshc";
reg = <0x4300000 0x1000>;
interrupts = <34 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk CLK_AXI4_EMMC>,
<&clk CLK_EMMC>;
clock-names = "core", "bus";
status = "disabled";
};
};
};

32
arch/riscv/boot/dts/sophgo/cv18xx.dtsi
View File

@@ -133,6 +133,28 @@ portd: gpio-controller@0 {
};
};
saradc: adc@30f0000 {
compatible = "sophgo,cv1800b-saradc";
reg = <0x030f0000 0x1000>;
clocks = <&clk CLK_SARADC>;
interrupts = <100 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
channel@0 {
reg = <0>;
};
channel@1 {
reg = <1>;
};
channel@2 {
reg = <2>;
};
};
i2c0: i2c@4000000 {
compatible = "snps,designware-i2c";
reg = <0x04000000 0x10000>;
@@ -297,6 +319,16 @@ sdhci0: mmc@4310000 {
status = "disabled";
};
sdhci1: mmc@4320000 {
compatible = "sophgo,cv1800b-dwcmshc";
reg = <0x4320000 0x1000>;
interrupts = <38 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk CLK_AXI4_SD1>,
<&clk CLK_SD1>;
clock-names = "core", "bus";
status = "disabled";
};
dmac: dma-controller@4330000 {
compatible = "snps,axi-dma-1.01a";
reg = <0x04330000 0x1000>;

95
arch/riscv/boot/dts/sophgo/sg2002-licheerv-nano-b.dts Normal file
View File

@@ -0,0 +1,95 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (C) 2024 Thomas Bonnefille <thomas.bonnefille@bootlin.com>
*/
/dts-v1/;
#include "sg2002.dtsi"
/ {
model = "LicheeRV Nano B";
compatible = "sipeed,licheerv-nano-b", "sipeed,licheerv-nano", "sophgo,sg2002";
aliases {
gpio0 = &gpio0;
gpio1 = &gpio1;
gpio2 = &gpio2;
gpio3 = &gpio3;
serial0 = &uart0;
serial1 = &uart1;
serial2 = &uart2;
serial3 = &uart3;
serial4 = &uart4;
};
chosen {
stdout-path = "serial0:115200n8";
};
};
&osc {
clock-frequency = <25000000>;
};
&pinctrl {
uart0_cfg: uart0-cfg {
uart0-pins {
pinmux = <PINMUX(PIN_UART0_TX, 0)>,
<PINMUX(PIN_UART0_RX, 0)>;
bias-pull-up;
drive-strength-microamp = <10800>;
power-source = <3300>;
};
};
sdhci0_cfg: sdhci0-cfg {
sdhci0-clk-pins {
pinmux = <PINMUX(PIN_SD0_CLK, 0)>;
bias-pull-up;
drive-strength-microamp = <16100>;
power-source = <3300>;
};
sdhci0-cmd-pins {
pinmux = <PINMUX(PIN_SD0_CMD, 0)>;
bias-pull-up;
drive-strength-microamp = <10800>;
power-source = <3300>;
};
sdhci0-data-pins {
pinmux = <PINMUX(PIN_SD0_D0, 0)>,
<PINMUX(PIN_SD0_D1, 0)>,
<PINMUX(PIN_SD0_D2, 0)>,
<PINMUX(PIN_SD0_D3, 0)>;
bias-pull-up;
drive-strength-microamp = <10800>;
power-source = <3300>;
};
sdhci0-cd-pins {
pinmux = <PINMUX(PIN_SD0_CD, 0)>;
bias-pull-up;
drive-strength-microamp = <10800>;
power-source = <3300>;
};
};
};
&sdhci0 {
pinctrl-0 = <&sdhci0_cfg>;
pinctrl-names = "default";
status = "okay";
bus-width = <4>;
no-1-8-v;
no-mmc;
no-sdio;
disable-wp;
};
&uart0 {
pinctrl-0 = <&uart0_cfg>;
pinctrl-names = "default";
status = "okay";
};

43
arch/riscv/boot/dts/sophgo/sg2002.dtsi Normal file
View File

@@ -0,0 +1,43 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright (C) 2024 Thomas Bonnefille <thomas.bonnefille@bootlin.com>
*/
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/pinctrl/pinctrl-sg2002.h>
#include "cv18xx.dtsi"
#include "cv181x.dtsi"
/ {
compatible = "sophgo,sg2002";
memory@80000000 {
device_type = "memory";
reg = <0x80000000 0x10000000>;
};
soc {
pinctrl: pinctrl@3001000 {
compatible = "sophgo,sg2002-pinctrl";
reg = <0x03001000 0x1000>,
<0x05027000 0x1000>;
reg-names = "sys", "rtc";
};
};
};
&plic {
compatible = "sophgo,sg2002-plic", "thead,c900-plic";
};
&clint {
compatible = "sophgo,sg2002-clint", "thead,c900-clint";
};
&clk {
compatible = "sophgo,sg2000-clk";
};
&sdhci0 {
compatible = "sophgo,sg2002-dwcmshc";
};

15
arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts
View File

@@ -5,6 +5,9 @@
#include "sg2042.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
/ {
model = "Milk-V Pioneer";
compatible = "milkv,pioneer", "sophgo,sg2042";
@@ -12,6 +15,18 @@ / {
chosen {
stdout-path = "serial0";
};
gpio-power {
compatible = "gpio-keys";
key-power {
label = "Power Key";
linux,code = <KEY_POWER>;
gpios = <&port0a 22 GPIO_ACTIVE_HIGH>;
linux,input-type = <EV_KEY>;
debounce-interval = <100>;
};
};
};
&cgi_main {