From 23c7816dddd3d28817ad49cefd3f504f44163655 Mon Sep 17 00:00:00 2001 From: Inochi Amaoto Date: Tue, 10 Sep 2024 06:35:10 +0800 Subject: [PATCH 1/9] riscv: dts: sophgo: cv1800b: add pinctrl support Add pinctrl node and related pin configuration for CV1800B SoC. Link: https://lore.kernel.org/r/IA1PR20MB49535E7F28242174CA318317BB992@IA1PR20MB4953.namprd20.prod.outlook.com Signed-off-by: Inochi Amaoto Signed-off-by: Chen Wang --- .../boot/dts/sophgo/cv1800b-milkv-duo.dts | 49 +++++++++++++++++++ arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 10 ++++ 2 files changed, 59 insertions(+) diff --git a/arch/riscv/boot/dts/sophgo/cv1800b-milkv-duo.dts b/arch/riscv/boot/dts/sophgo/cv1800b-milkv-duo.dts index 375ff2661b6e..9feb520eaec4 100644 --- a/arch/riscv/boot/dts/sophgo/cv1800b-milkv-duo.dts +++ b/arch/riscv/boot/dts/sophgo/cv1800b-milkv-duo.dts @@ -39,7 +39,54 @@ &osc { clock-frequency = <25000000>; }; +&pinctrl { + uart0_cfg: uart0-cfg { + uart0-pins { + pinmux = , + ; + bias-pull-up; + drive-strength-microamp = <10800>; + power-source = <3300>; + }; + }; + + sdhci0_cfg: sdhci0-cfg { + sdhci0-clk-pins { + pinmux = ; + bias-pull-up; + drive-strength-microamp = <16100>; + power-source = <3300>; + }; + + sdhci0-cmd-pins { + pinmux = ; + bias-pull-up; + drive-strength-microamp = <10800>; + power-source = <3300>; + }; + + sdhci0-data-pins { + pinmux = , + , + , + ; + bias-pull-up; + drive-strength-microamp = <10800>; + power-source = <3300>; + }; + + sdhci0-cd-pins { + pinmux = ; + bias-pull-up; + drive-strength-microamp = <10800>; + power-source = <3300>; + }; + }; +}; + &sdhci0 { + pinctrl-0 = <&sdhci0_cfg>; + pinctrl-names = "default"; status = "okay"; bus-width = <4>; no-1-8-v; @@ -49,5 +96,7 @@ &sdhci0 { }; &uart0 { + pinctrl-0 = <&uart0_cfg>; + pinctrl-names = "default"; status = "okay"; }; diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi index ec9530972ae2..aa1f5df100f0 100644 --- a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi +++ b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi @@ -3,6 +3,7 @@ * Copyright (C) 2023 Jisheng Zhang */ +#include #include "cv18xx.dtsi" / { @@ -12,6 +13,15 @@ memory@80000000 { device_type = "memory"; reg = <0x80000000 0x4000000>; }; + + soc { + pinctrl: pinctrl@3001000 { + compatible = "sophgo,cv1800b-pinctrl"; + reg = <0x03001000 0x1000>, + <0x05027000 0x1000>; + reg-names = "sys", "rtc"; + }; + }; }; &plic { From 30003e3f802ec4e353cecae3fc2a4c3cd25b63fe Mon Sep 17 00:00:00 2001 From: Inochi Amaoto Date: Tue, 10 Sep 2024 06:35:11 +0800 Subject: [PATCH 2/9] riscv: dts: sophgo: cv1812h: add pinctrl support Add pinctrl node for CV1812H SoC. Link: https://lore.kernel.org/r/IA1PR20MB49533DB3D0C1861938185015BB992@IA1PR20MB4953.namprd20.prod.outlook.com Signed-off-by: Inochi Amaoto Signed-off-by: Chen Wang --- arch/riscv/boot/dts/sophgo/cv1812h.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/riscv/boot/dts/sophgo/cv1812h.dtsi b/arch/riscv/boot/dts/sophgo/cv1812h.dtsi index 7fa4c1e2d1da..815114db54ed 100644 --- a/arch/riscv/boot/dts/sophgo/cv1812h.dtsi +++ b/arch/riscv/boot/dts/sophgo/cv1812h.dtsi @@ -4,6 +4,7 @@ */ #include +#include #include "cv18xx.dtsi" / { @@ -13,6 +14,15 @@ memory@80000000 { device_type = "memory"; reg = <0x80000000 0x10000000>; }; + + soc { + pinctrl: pinctrl@3001000 { + compatible = "sophgo,cv1812h-pinctrl"; + reg = <0x03001000 0x1000>, + <0x05027000 0x1000>; + reg-names = "sys", "rtc"; + }; + }; }; &plic { From 93b61555f5095a44fe00df27399270867fbf278a Mon Sep 17 00:00:00 2001 From: Thomas Bonnefille Date: Thu, 10 Oct 2024 17:07:06 +0200 Subject: [PATCH 3/9] riscv: dts: sophgo: Add initial SG2002 SoC device tree Add initial device tree for the SG2002 RISC-V SoC by SOPHGO. Signed-off-by: Thomas Bonnefille Reviewed-by: Inochi Amaoto Link: https://lore.kernel.org/r/20241010-sg2002-v5-1-a0f2e582b932@bootlin.com Signed-off-by: Inochi Amaoto Signed-off-by: Chen Wang --- arch/riscv/boot/dts/sophgo/sg2002.dtsi | 42 ++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) create mode 100644 arch/riscv/boot/dts/sophgo/sg2002.dtsi diff --git a/arch/riscv/boot/dts/sophgo/sg2002.dtsi b/arch/riscv/boot/dts/sophgo/sg2002.dtsi new file mode 100644 index 000000000000..242fde84443f --- /dev/null +++ b/arch/riscv/boot/dts/sophgo/sg2002.dtsi @@ -0,0 +1,42 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2024 Thomas Bonnefille + */ + +#include +#include +#include "cv18xx.dtsi" + +/ { + compatible = "sophgo,sg2002"; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x10000000>; + }; + + soc { + pinctrl: pinctrl@3008000 { + compatible = "sophgo,sg2002-pinctrl"; + reg = <0x03001000 0x1000>, + <0x05027000 0x1000>; + reg-names = "sys", "rtc"; + }; + }; +}; + +&plic { + compatible = "sophgo,sg2002-plic", "thead,c900-plic"; +}; + +&clint { + compatible = "sophgo,sg2002-clint", "thead,c900-clint"; +}; + +&clk { + compatible = "sophgo,sg2000-clk"; +}; + +&sdhci0 { + compatible = "sophgo,sg2002-dwcmshc"; +}; From d32552307b6c526aa75a9f9a0ea29a4a7f1746b9 Mon Sep 17 00:00:00 2001 From: Thomas Bonnefille Date: Thu, 10 Oct 2024 17:07:07 +0200 Subject: [PATCH 4/9] riscv: dts: sophgo: Add LicheeRV Nano board device tree LicheeRV Nano B [1] is an embedded development platform based on the SOPHGO SG2002 chip, the B(ase) version is deprived of Wifi/Bluetooth and Ethernet. Add only support for UART and SDHCI. Link: https://wiki.sipeed.com/hardware/en/lichee/RV_Nano/1_intro.html [1] Signed-off-by: Thomas Bonnefille Reviewed-by: Inochi Amaoto Link: https://lore.kernel.org/r/20241010-sg2002-v5-2-a0f2e582b932@bootlin.com Signed-off-by: Inochi Amaoto Signed-off-by: Chen Wang --- arch/riscv/boot/dts/sophgo/Makefile | 1 + .../dts/sophgo/sg2002-licheerv-nano-b.dts | 95 +++++++++++++++++++ 2 files changed, 96 insertions(+) create mode 100644 arch/riscv/boot/dts/sophgo/sg2002-licheerv-nano-b.dts diff --git a/arch/riscv/boot/dts/sophgo/Makefile b/arch/riscv/boot/dts/sophgo/Makefile index 57ad82a61ea6..47d4243a8f35 100644 --- a/arch/riscv/boot/dts/sophgo/Makefile +++ b/arch/riscv/boot/dts/sophgo/Makefile @@ -1,4 +1,5 @@ # SPDX-License-Identifier: GPL-2.0 dtb-$(CONFIG_ARCH_SOPHGO) += cv1800b-milkv-duo.dtb dtb-$(CONFIG_ARCH_SOPHGO) += cv1812h-huashan-pi.dtb +dtb-$(CONFIG_ARCH_SOPHGO) += sg2002-licheerv-nano-b.dtb dtb-$(CONFIG_ARCH_SOPHGO) += sg2042-milkv-pioneer.dtb diff --git a/arch/riscv/boot/dts/sophgo/sg2002-licheerv-nano-b.dts b/arch/riscv/boot/dts/sophgo/sg2002-licheerv-nano-b.dts new file mode 100644 index 000000000000..86a712b953a5 --- /dev/null +++ b/arch/riscv/boot/dts/sophgo/sg2002-licheerv-nano-b.dts @@ -0,0 +1,95 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2024 Thomas Bonnefille + */ + +/dts-v1/; + +#include "sg2002.dtsi" + +/ { + model = "LicheeRV Nano B"; + compatible = "sipeed,licheerv-nano-b", "sipeed,licheerv-nano", "sophgo,sg2002"; + + aliases { + gpio0 = &gpio0; + gpio1 = &gpio1; + gpio2 = &gpio2; + gpio3 = &gpio3; + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + serial4 = &uart4; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&osc { + clock-frequency = <25000000>; +}; + +&pinctrl { + uart0_cfg: uart0-cfg { + uart0-pins { + pinmux = , + ; + bias-pull-up; + drive-strength-microamp = <10800>; + power-source = <3300>; + }; + }; + + sdhci0_cfg: sdhci0-cfg { + sdhci0-clk-pins { + pinmux = ; + bias-pull-up; + drive-strength-microamp = <16100>; + power-source = <3300>; + }; + + sdhci0-cmd-pins { + pinmux = ; + bias-pull-up; + drive-strength-microamp = <10800>; + power-source = <3300>; + }; + + sdhci0-data-pins { + pinmux = , + , + , + ; + bias-pull-up; + drive-strength-microamp = <10800>; + power-source = <3300>; + }; + + sdhci0-cd-pins { + pinmux = ; + bias-pull-up; + drive-strength-microamp = <10800>; + power-source = <3300>; + }; + }; +}; + +&sdhci0 { + pinctrl-0 = <&sdhci0_cfg>; + pinctrl-names = "default"; + status = "okay"; + bus-width = <4>; + no-1-8-v; + no-mmc; + no-sdio; + disable-wp; +}; + +&uart0 { + pinctrl-0 = <&uart0_cfg>; + pinctrl-names = "default"; + status = "okay"; +}; From 45a544a62ef7cac9ecc69585a90da72ca68af898 Mon Sep 17 00:00:00 2001 From: Thomas Bonnefille Date: Thu, 29 Aug 2024 14:31:52 +0200 Subject: [PATCH 5/9] riscv: dts: sophgo: Add SARADC description for Sophgo CV1800B Add SARADC node for the Successive Approximation Analog to Digital Converter used in Sophgo CV1800B SoC. This patch only adds the active domain controller. Signed-off-by: Thomas Bonnefille Reviewed-by: Inochi Amaoto Link: https://lore.kernel.org/r/20240829-sg2002-adc-v5-3-aacb381e869b@bootlin.com Signed-off-by: Inochi Amaoto Signed-off-by: Chen Wang --- arch/riscv/boot/dts/sophgo/cv18xx.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi index b724fb6d9689..bef89979df78 100644 --- a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi +++ b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi @@ -133,6 +133,28 @@ portd: gpio-controller@0 { }; }; + saradc: adc@30f0000 { + compatible = "sophgo,cv1800b-saradc"; + reg = <0x030f0000 0x1000>; + clocks = <&clk CLK_SARADC>; + interrupts = <100 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + channel@0 { + reg = <0>; + }; + + channel@1 { + reg = <1>; + }; + + channel@2 { + reg = <2>; + }; + }; + i2c0: i2c@4000000 { compatible = "snps,designware-i2c"; reg = <0x04000000 0x10000>; From 128bded4bc5253b94c66acd63bef03f16148ae4f Mon Sep 17 00:00:00 2001 From: Chen Wang Date: Tue, 8 Oct 2024 09:43:52 +0800 Subject: [PATCH 6/9] riscv: sophgo: dts: add power key for pioneer box There is a power button on the front panel of the pioneer box. Short pressing the button will trigger the onboard MCU to notify SG2042 through GPIO22 to enter the power-off process. Signed-off-by: Chen Wang Link: https://lore.kernel.org/r/12e65a99f1b52c52b7372e900a203063b30c74b5.1728350655.git.unicorn_wang@outlook.com Signed-off-by: Inochi Amaoto --- .../boot/dts/sophgo/sg2042-milkv-pioneer.dts | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts b/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts index a3f9d6f22566..be596d01ff8d 100644 --- a/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts +++ b/arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts @@ -5,6 +5,9 @@ #include "sg2042.dtsi" +#include +#include + / { model = "Milk-V Pioneer"; compatible = "milkv,pioneer", "sophgo,sg2042"; @@ -12,6 +15,18 @@ / { chosen { stdout-path = "serial0"; }; + + gpio-power { + compatible = "gpio-keys"; + + key-power { + label = "Power Key"; + linux,code = ; + gpios = <&port0a 22 GPIO_ACTIVE_HIGH>; + linux,input-type = ; + debounce-interval = <100>; + }; + }; }; &cgi_main { From 44196383a26fcacbd6dcf5a1ab2dd8bf8e4132c0 Mon Sep 17 00:00:00 2001 From: Thomas Bonnefille Date: Mon, 28 Oct 2024 11:43:24 +0100 Subject: [PATCH 7/9] riscv: dts: sophgo: fix pinctrl base-address Fix the base-address of the pinctrl controller to match its register address. Signed-off-by: Thomas Bonnefille Reviewed-by: Inochi Amaoto Fixes: 93b61555f509 ("riscv: dts: sophgo: Add initial SG2002 SoC device tree") Link: https://lore.kernel.org/r/20241028-fix-address-v1-1-dcbe21e59ccf@bootlin.com Signed-off-by: Inochi Amaoto Signed-off-by: Chen Wang --- arch/riscv/boot/dts/sophgo/sg2002.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/boot/dts/sophgo/sg2002.dtsi b/arch/riscv/boot/dts/sophgo/sg2002.dtsi index 242fde84443f..6616f578d190 100644 --- a/arch/riscv/boot/dts/sophgo/sg2002.dtsi +++ b/arch/riscv/boot/dts/sophgo/sg2002.dtsi @@ -16,7 +16,7 @@ memory@80000000 { }; soc { - pinctrl: pinctrl@3008000 { + pinctrl: pinctrl@3001000 { compatible = "sophgo,sg2002-pinctrl"; reg = <0x03001000 0x1000>, <0x05027000 0x1000>; From 06133f48a87144de40bbd3934fcaad449ecc1b93 Mon Sep 17 00:00:00 2001 From: Inochi Amaoto Date: Fri, 25 Oct 2024 19:28:59 +0800 Subject: [PATCH 8/9] riscv: dts: sophgo: Add sdio configuration for Huashan Pi Add configuration for sdio for Huashan Pi to support sdio wifi. Link: https://lore.kernel.org/r/20241025112902.1200716-2-inochiama@gmail.com Signed-off-by: Inochi Amaoto Signed-off-by: Chen Wang --- arch/riscv/boot/dts/sophgo/cv1812h-huashan-pi.dts | 11 +++++++++++ arch/riscv/boot/dts/sophgo/cv18xx.dtsi | 10 ++++++++++ 2 files changed, 21 insertions(+) diff --git a/arch/riscv/boot/dts/sophgo/cv1812h-huashan-pi.dts b/arch/riscv/boot/dts/sophgo/cv1812h-huashan-pi.dts index 7b5f57853690..4ea27cd357dc 100644 --- a/arch/riscv/boot/dts/sophgo/cv1812h-huashan-pi.dts +++ b/arch/riscv/boot/dts/sophgo/cv1812h-huashan-pi.dts @@ -52,6 +52,17 @@ &sdhci0 { disable-wp; }; +&sdhci1 { + status = "okay"; + bus-width = <4>; + cap-sdio-irq; + max-frequency = <50000000>; + no-mmc; + no-sd; + disable-wp; + non-removable; +}; + &uart0 { status = "okay"; }; diff --git a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi index bef89979df78..c18822ec849f 100644 --- a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi +++ b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi @@ -319,6 +319,16 @@ sdhci0: mmc@4310000 { status = "disabled"; }; + sdhci1: mmc@4320000 { + compatible = "sophgo,cv1800b-dwcmshc"; + reg = <0x4320000 0x1000>; + interrupts = <38 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk CLK_AXI4_SD1>, + <&clk CLK_SD1>; + clock-names = "core", "bus"; + status = "disabled"; + }; + dmac: dma-controller@4330000 { compatible = "snps,axi-dma-1.01a"; reg = <0x04330000 0x1000>; From b5cf65cc0fd00aa30ff218ec8170dd48e3cbe78d Mon Sep 17 00:00:00 2001 From: Inochi Amaoto Date: Fri, 25 Oct 2024 19:29:00 +0800 Subject: [PATCH 9/9] riscv: dts: sophgo: Add emmc support for Huashan Pi Add emmc node configuration for Huashan Pi. Link: https://lore.kernel.org/r/20241025112902.1200716-3-inochiama@gmail.com Signed-off-by: Inochi Amaoto Signed-off-by: Chen Wang --- .../boot/dts/sophgo/cv1812h-huashan-pi.dts | 12 +++++++++++ arch/riscv/boot/dts/sophgo/cv1812h.dtsi | 1 + arch/riscv/boot/dts/sophgo/cv181x.dtsi | 21 +++++++++++++++++++ arch/riscv/boot/dts/sophgo/sg2002.dtsi | 1 + 4 files changed, 35 insertions(+) create mode 100644 arch/riscv/boot/dts/sophgo/cv181x.dtsi diff --git a/arch/riscv/boot/dts/sophgo/cv1812h-huashan-pi.dts b/arch/riscv/boot/dts/sophgo/cv1812h-huashan-pi.dts index 4ea27cd357dc..26b57e15adc1 100644 --- a/arch/riscv/boot/dts/sophgo/cv1812h-huashan-pi.dts +++ b/arch/riscv/boot/dts/sophgo/cv1812h-huashan-pi.dts @@ -43,6 +43,18 @@ &osc { clock-frequency = <25000000>; }; +&emmc { + status = "okay"; + bus-width = <4>; + max-frequency = <200000000>; + mmc-ddr-1_8v; + mmc-ddr-3_3v; + mmc-hs200-1_8v; + no-sd; + no-sdio; + non-removable; +}; + &sdhci0 { status = "okay"; bus-width = <4>; diff --git a/arch/riscv/boot/dts/sophgo/cv1812h.dtsi b/arch/riscv/boot/dts/sophgo/cv1812h.dtsi index 815114db54ed..8a1b95c5116b 100644 --- a/arch/riscv/boot/dts/sophgo/cv1812h.dtsi +++ b/arch/riscv/boot/dts/sophgo/cv1812h.dtsi @@ -6,6 +6,7 @@ #include #include #include "cv18xx.dtsi" +#include "cv181x.dtsi" / { compatible = "sophgo,cv1812h"; diff --git a/arch/riscv/boot/dts/sophgo/cv181x.dtsi b/arch/riscv/boot/dts/sophgo/cv181x.dtsi new file mode 100644 index 000000000000..5fd14dd1b14f --- /dev/null +++ b/arch/riscv/boot/dts/sophgo/cv181x.dtsi @@ -0,0 +1,21 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2024 Inochi Amaoto + */ + +#include +#include + +/ { + soc { + emmc: mmc@4300000 { + compatible = "sophgo,cv1800b-dwcmshc"; + reg = <0x4300000 0x1000>; + interrupts = <34 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk CLK_AXI4_EMMC>, + <&clk CLK_EMMC>; + clock-names = "core", "bus"; + status = "disabled"; + }; + }; +}; diff --git a/arch/riscv/boot/dts/sophgo/sg2002.dtsi b/arch/riscv/boot/dts/sophgo/sg2002.dtsi index 6616f578d190..7f79de33163c 100644 --- a/arch/riscv/boot/dts/sophgo/sg2002.dtsi +++ b/arch/riscv/boot/dts/sophgo/sg2002.dtsi @@ -6,6 +6,7 @@ #include #include #include "cv18xx.dtsi" +#include "cv181x.dtsi" / { compatible = "sophgo,sg2002";