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Merge tag 'riscv-sophgo-dt-for-v6.15' of https://github.com/sophgo/linux into soc/dt
RISC-V Devicetrees for v6.15 Sophgo: Add pwm controller support for SG2042. Add pwm-fan & cooling maps for Milk-V Pioneer. Updated MAINTAINERS info for SOPHGO DEVICETREES and DRIVERS. Signed-off-by: Chen Wang <unicorn_wang@outlook.com> * tag 'riscv-sophgo-dt-for-v6.15' of https://github.com/sophgo/linux: riscv: sophgo: dts: add cooling maps for Milk-V Pioneer riscv: sophgo: dts: add pwm-fan for Milk-V Pioneer MAINTAINERS: update info for SOPHGO DEVICETREES and DRIVERS riscv: sophgo: dts: add pwm controller for SG2042 SoC Link: https://lore.kernel.org/r/PN0PR01MB10393CEC71B623E0A779E7393FEDF2@PN0PR01MB10393.INDPRD01.PROD.OUTLOOK.COM Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
@@ -22152,7 +22152,9 @@ F: include/linux/sony-laptop.h
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SOPHGO DEVICETREES and DRIVERS
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M: Chen Wang <unicorn_wang@outlook.com>
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M: Inochi Amaoto <inochiama@outlook.com>
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M: Inochi Amaoto <inochiama@gmail.com>
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L: sophgo@lists.linux.dev
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W: https://github.com/sophgo/linux/wiki
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T: git https://github.com/sophgo/linux.git
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S: Maintained
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N: sophgo
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@@ -73,6 +73,13 @@ &uart0 {
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};
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/ {
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pwmfan: pwm-fan {
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compatible = "pwm-fan";
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cooling-levels = <103 128 179 230 255>;
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pwms = <&pwm 0 40000 0>;
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#cooling-cells = <2>;
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};
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thermal-zones {
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soc-thermal {
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polling-delay-passive = <1000>;
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@@ -104,6 +111,28 @@ soc_hot: soc-hot {
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type = "hot";
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};
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};
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cooling-maps {
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map0 {
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trip = <&soc_active1>;
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cooling-device = <&pwmfan 0 1>;
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};
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map1 {
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trip = <&soc_active2>;
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cooling-device = <&pwmfan 1 2>;
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};
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map2 {
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trip = <&soc_active3>;
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cooling-device = <&pwmfan 2 3>;
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};
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map3 {
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trip = <&soc_hot>;
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cooling-device = <&pwmfan 3 4>;
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};
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};
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};
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board-thermal {
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@@ -118,6 +147,13 @@ board_active: board-active {
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type = "active";
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};
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};
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cooling-maps {
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map4 {
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trip = <&board_active>;
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cooling-device = <&pwmfan 3 4>;
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};
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};
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};
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};
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};
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@@ -165,6 +165,15 @@ port2a: gpio-controller@0 {
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};
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};
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pwm: pwm@703000c000 {
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compatible = "sophgo,sg2042-pwm";
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reg = <0x70 0x3000c000 0x0 0x20>;
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#pwm-cells = <3>;
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clocks = <&clkgen GATE_CLK_APB_PWM>;
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clock-names = "apb";
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resets = <&rstgen RST_PWM>;
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};
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pllclk: clock-controller@70300100c0 {
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compatible = "sophgo,sg2042-pll";
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reg = <0x70 0x300100c0 0x0 0x40>;
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