mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
synced 2026-02-24 05:25:18 -05:00
Merge tag 'mvebu-dt64-6.15-1' of https://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu into soc/dt
mvebu dt64 for 6.15 (part 1) device tree clean-up fomr DT maintainers * tag 'mvebu-dt64-6.15-1' of https://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu: arm64: dts: marvell: Use preferred node names for "simple-bus" arm64: dts: marvell: Drop unused CP11X_TYPE define arm64: dts: marvell: Move arch timer and pmu nodes to top-level ARM: dts: marvell: armada: Align GPIO hog name with bindings ARM: dts: marvell: kirkwood-openrd: Align GPIO hog name with bindings arm64: dts: marvell: armada-8040: Align GPIO hog name with bindings arm64: dts: marvell: Add missing board compatible for IEI-Puzzle-M801 arm64: dts: marvell: Fix missing/incorrect "marvell,armada3710" compatible arm64: dts: marvell: Drop incomplete root compatible/model properties dt-bindings: marvell: armada-7k-8k: Add missing 7040 and 8040 board compatibles dt-bindings: marvell: armada-7k-8k: Move Armada 8KPlus to schema dt-bindings: marvell: armada-37xx: Add glinet,gl-mv1000 compatible Link: https://lore.kernel.org/r/87wmco99xv.fsf@BLaptop.bootlin.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
@@ -18,6 +18,7 @@ properties:
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||||
items:
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- enum:
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- cznic,turris-mox
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- glinet,gl-mv1000
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- globalscale,espressobin
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- marvell,armada-3720-db
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- methode,edpu
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@@ -23,6 +23,9 @@ properties:
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||||
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- description: Armada 7040 SoC
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items:
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- enum:
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- globalscale,mochabin
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- marvell,armada7040-db
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- const: marvell,armada7040
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- const: marvell,armada-ap806-quad
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- const: marvell,armada-ap806
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@@ -35,10 +38,32 @@ properties:
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- description: Armada 8040 SoC
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items:
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- enum:
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- iei,puzzle-m801
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- marvell,armada8040-db
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- solidrun,clearfog-gt-8k
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- const: marvell,armada8040
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- const: marvell,armada-ap806-quad
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- const: marvell,armada-ap806
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- description: Armada 8040 SoC MACCHIATOBin Boards
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items:
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- enum:
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- marvell,armada8040-mcbin-doubleshot
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- marvell,armada8040-mcbin-singleshot
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- const: marvell,armada8040-mcbin
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- const: marvell,armada8040
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- const: marvell,armada-ap806-quad
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- const: marvell,armada-ap806
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- description: Armada 8080 SoC
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items:
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- enum:
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- marvell,armada-8080-db
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- const: marvell,armada-8080
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- const: marvell,armada-ap810-octa
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- const: marvell,armada-ap810
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- description: Armada CN9130 SoC with no external CP
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items:
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- const: marvell,cn9130
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@@ -1,15 +0,0 @@
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Marvell Armada 8KPlus Platforms Device Tree Bindings
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----------------------------------------------------
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Boards using a SoC of the Marvell Armada 8KP families must carry
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the following root node property:
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- compatible, with one of the following values:
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- "marvell,armada-8080", "marvell,armada-ap810-octa", "marvell,armada-ap810"
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when the SoC being used is the Armada 8080
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Example:
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compatible = "marvell,armada-8080-db", "marvell,armada-8080",
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"marvell,armada-ap810-octa", "marvell,armada-ap810"
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@@ -453,7 +453,7 @@ &gpio0 {
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pinctrl-0 = <&cf_gtr_fan_pwm &cf_gtr_wifi_disable_pins>;
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pinctrl-names = "default";
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wifi-disable {
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wifi-disable-hog {
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gpio-hog;
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gpios = <30 GPIO_ACTIVE_LOW>, <31 GPIO_ACTIVE_LOW>;
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output-low;
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@@ -465,7 +465,7 @@ &gpio1 {
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pinctrl-0 = <&cf_gtr_isolation_pins &cf_gtr_poe_reset_pins &cf_gtr_lte_disable_pins>;
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pinctrl-names = "default";
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lte-disable {
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lte-disable-hog {
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gpio-hog;
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gpios = <2 GPIO_ACTIVE_LOW>;
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output-low;
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@@ -476,14 +476,14 @@ lte-disable {
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* This signal, when asserted, isolates Armada 38x sample at reset pins
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* from control of external devices. Should be de-asserted after reset.
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*/
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sar-isolation {
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sar-isolation-hog {
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gpio-hog;
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gpios = <15 GPIO_ACTIVE_LOW>;
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output-low;
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line-name = "sar-isolation";
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};
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poe-reset {
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poe-reset-hog {
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gpio-hog;
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gpios = <16 GPIO_ACTIVE_LOW>;
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output-low;
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@@ -34,7 +34,7 @@ ð1 {
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};
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&gpio0 {
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phy1_reset {
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phy1-reset-hog {
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gpio-hog;
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gpios = <19 GPIO_ACTIVE_LOW>;
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output-low;
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@@ -53,7 +53,7 @@ mvsdio@90000 {
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cd-gpios = <&gpio0 29 9>;
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};
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gpio@10100 {
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p28 {
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p28-hog {
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gpio-hog;
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gpios = <28 GPIO_ACTIVE_HIGH>;
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/*
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@@ -71,7 +71,7 @@ p28 {
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};
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};
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gpio@10140 {
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p2 {
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p2-hog {
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gpio-hog;
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gpios = <2 GPIO_ACTIVE_HIGH>;
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/*
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@@ -78,7 +78,7 @@ soc {
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#size-cells = <2>;
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ranges;
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internal-regs@7f000000 {
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bus@7f000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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@@ -1,17 +0,0 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Device Tree Include file for Marvell Armada 371x family of SoCs
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* (also named 88F3710)
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*
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* Copyright (C) 2016 Marvell
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*
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* Gregory CLEMENT <gregory.clement@free-electrons.com>
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*
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*/
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#include "armada-37xx.dtsi"
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/ {
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model = "Marvell Armada 3710 SoC";
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compatible = "marvell,armada3710", "marvell,armada3700";
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};
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@@ -18,7 +18,7 @@
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/ {
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model = "Marvell Armada 3720 Development Board DB-88F3720-DDR3";
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compatible = "marvell,armada-3720-db", "marvell,armada3720", "marvell,armada3700";
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compatible = "marvell,armada-3720-db", "marvell,armada3720", "marvell,armada3710";
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chosen {
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stdout-path = "serial0:115200n8";
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@@ -18,7 +18,7 @@
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/ {
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model = "Globalscale Marvell ESPRESSOBin Board (eMMC)";
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compatible = "globalscale,espressobin-emmc", "globalscale,espressobin",
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"marvell,armada3720", "marvell,armada3700";
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"marvell,armada3720", "marvell,armada3710";
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};
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&sdhci0 {
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@@ -13,7 +13,7 @@
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/ {
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model = "Globalscale Marvell ESPRESSOBin Ultra Board";
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compatible = "globalscale,espressobin-ultra", "globalscale,espressobin",
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"marvell,armada3720", "marvell,armada3700";
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"marvell,armada3720", "marvell,armada3710";
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aliases {
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/* ethernet1 is WAN port */
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@@ -19,7 +19,7 @@ / {
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model = "Globalscale Marvell ESPRESSOBin Board V7 (eMMC)";
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compatible = "globalscale,espressobin-v7-emmc", "globalscale,espressobin-v7",
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"globalscale,espressobin", "marvell,armada3720",
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"marvell,armada3700";
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"marvell,armada3710";
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aliases {
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/* ethernet1 is wan port */
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@@ -18,7 +18,7 @@
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/ {
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model = "Globalscale Marvell ESPRESSOBin Board V7";
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compatible = "globalscale,espressobin-v7", "globalscale,espressobin",
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"marvell,armada3720", "marvell,armada3700";
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"marvell,armada3720", "marvell,armada3710";
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||||
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aliases {
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||||
/* ethernet1 is wan port */
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||||
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@@ -16,5 +16,5 @@
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||||
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||||
/ {
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model = "Globalscale Marvell ESPRESSOBin Board";
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compatible = "globalscale,espressobin", "marvell,armada3720", "marvell,armada3700";
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compatible = "globalscale,espressobin", "marvell,armada3720", "marvell,armada3710";
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};
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@@ -7,7 +7,7 @@
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/ {
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model = "GL.iNet GL-MV1000";
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compatible = "glinet,gl-mv1000", "marvell,armada3720";
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compatible = "glinet,gl-mv1000", "marvell,armada3720", "marvell,armada3710";
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aliases {
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led-boot = &led_power;
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@@ -14,7 +14,7 @@
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/ {
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model = "CZ.NIC Turris Mox Board";
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compatible = "cznic,turris-mox", "marvell,armada3720",
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"marvell,armada3700";
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"marvell,armada3710";
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aliases {
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spi0 = &spi0;
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@@ -12,9 +12,6 @@
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#include "armada-37xx.dtsi"
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/ {
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model = "Marvell Armada 3720 SoC";
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compatible = "marvell,armada3720", "marvell,armada3700";
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cpus {
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cpu1: cpu@1 {
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device_type = "cpu";
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@@ -11,8 +11,6 @@
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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model = "Marvell Armada 37xx SoC";
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compatible = "marvell,armada3700";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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@@ -78,7 +76,7 @@ soc {
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#size-cells = <2>;
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ranges;
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internal-regs@d0000000 {
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bus@d0000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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@@ -8,9 +8,3 @@
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#include "armada-ap806-dual.dtsi"
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#include "armada-70x0.dtsi"
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/ {
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model = "Marvell Armada 7020";
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compatible = "marvell,armada7020", "marvell,armada-ap806-dual",
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"marvell,armada-ap806";
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};
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@@ -9,12 +9,6 @@
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#include "armada-ap806-quad.dtsi"
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#include "armada-70x0.dtsi"
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/ {
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model = "Marvell Armada 7040";
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compatible = "marvell,armada7040", "marvell,armada-ap806-quad",
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"marvell,armada-ap806";
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};
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&cp0_pcie0 {
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iommu-map =
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<0x0 &smmu 0x480 0x20>,
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@@ -9,12 +9,6 @@
|
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#include "armada-ap806-dual.dtsi"
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#include "armada-80x0.dtsi"
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/ {
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model = "Marvell Armada 8020";
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compatible = "marvell,armada8020", "marvell,armada-ap806-dual",
|
||||
"marvell,armada-ap806";
|
||||
};
|
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|
||||
/* The RTC requires external oscillator. But on Aramda 80x0, the RTC clock
|
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* in CP master is not connected (by package) to the oscillator. So
|
||||
* disable it. However, the RTC clock in CP slave is connected to the
|
||||
|
||||
@@ -371,25 +371,25 @@ &cp0_pcie0 {
|
||||
};
|
||||
|
||||
&cp0_gpio2 {
|
||||
sata_reset {
|
||||
sata-reset-hog {
|
||||
gpio-hog;
|
||||
gpios = <1 GPIO_ACTIVE_HIGH>;
|
||||
output-high;
|
||||
};
|
||||
|
||||
lte_reset {
|
||||
lte-reset-hog {
|
||||
gpio-hog;
|
||||
gpios = <2 GPIO_ACTIVE_LOW>;
|
||||
output-low;
|
||||
};
|
||||
|
||||
wlan_disable {
|
||||
wlan_disable-hog {
|
||||
gpio-hog;
|
||||
gpios = <19 GPIO_ACTIVE_LOW>;
|
||||
output-low;
|
||||
};
|
||||
|
||||
lte_disable {
|
||||
lte-disable-hog {
|
||||
gpio-hog;
|
||||
gpios = <21 GPIO_ACTIVE_LOW>;
|
||||
output-low;
|
||||
|
||||
@@ -13,7 +13,7 @@
|
||||
|
||||
/ {
|
||||
model = "IEI-Puzzle-M801";
|
||||
compatible = "marvell,armada8040", "marvell,armada-ap806-quad", "marvell,armada-ap806";
|
||||
compatible = "iei,puzzle-m801", "marvell,armada8040", "marvell,armada-ap806-quad", "marvell,armada-ap806";
|
||||
|
||||
aliases {
|
||||
ethernet0 = &cp0_eth0;
|
||||
|
||||
@@ -9,12 +9,6 @@
|
||||
#include "armada-ap806-quad.dtsi"
|
||||
#include "armada-80x0.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Marvell Armada 8040";
|
||||
compatible = "marvell,armada8040", "marvell,armada-ap806-quad",
|
||||
"marvell,armada-ap806";
|
||||
};
|
||||
|
||||
&cp0_pcie0 {
|
||||
iommu-map =
|
||||
<0x0 &smmu 0x480 0x20>,
|
||||
|
||||
@@ -6,9 +6,3 @@
|
||||
*/
|
||||
|
||||
#include "armada-ap810-ap0-octa-core.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Marvell 8080 board";
|
||||
compatible = "marvell,armada-8080", "marvell,armada-ap810-octa",
|
||||
"marvell,armada-ap810";
|
||||
};
|
||||
|
||||
@@ -8,9 +8,6 @@
|
||||
#include "armada-ap806.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Marvell Armada AP806 Dual";
|
||||
compatible = "marvell,armada-ap806-dual", "marvell,armada-ap806";
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
@@ -8,9 +8,6 @@
|
||||
#include "armada-ap806.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Marvell Armada AP806 Quad";
|
||||
compatible = "marvell,armada-ap806-quad", "marvell,armada-ap806";
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
@@ -5,14 +5,8 @@
|
||||
* Device Tree file for Marvell Armada AP806.
|
||||
*/
|
||||
|
||||
#define AP_NAME ap806
|
||||
#include "armada-ap80x.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Marvell Armada AP806";
|
||||
compatible = "marvell,armada-ap806";
|
||||
};
|
||||
|
||||
&ap_syscon0 {
|
||||
ap_clk: clock {
|
||||
compatible = "marvell,ap806-clock";
|
||||
|
||||
@@ -8,9 +8,6 @@
|
||||
#include "armada-ap807.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Marvell Armada AP807 Quad";
|
||||
compatible = "marvell,armada-ap807-quad", "marvell,armada-ap807";
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
@@ -5,14 +5,8 @@
|
||||
* Copyright (C) 2019 Marvell Technology Group Ltd.
|
||||
*/
|
||||
|
||||
#define AP_NAME ap807
|
||||
#include "armada-ap80x.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Marvell Armada AP807";
|
||||
compatible = "marvell,armada-ap807";
|
||||
};
|
||||
|
||||
&ap_syscon0 {
|
||||
ap_clk: clock {
|
||||
compatible = "marvell,ap807-clock";
|
||||
|
||||
@@ -48,14 +48,29 @@ tee@4400000 {
|
||||
};
|
||||
};
|
||||
|
||||
AP_NAME {
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
|
||||
};
|
||||
|
||||
pmu {
|
||||
compatible = "arm,cortex-a72-pmu";
|
||||
interrupt-parent = <&pic>;
|
||||
interrupts = <17>;
|
||||
};
|
||||
|
||||
soc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
compatible = "simple-bus";
|
||||
interrupt-parent = <&gic>;
|
||||
ranges;
|
||||
|
||||
config-space@f0000000 {
|
||||
bus@f0000000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "simple-bus";
|
||||
@@ -122,20 +137,6 @@ gic_v2m3: v2m@2b0000 {
|
||||
};
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
|
||||
};
|
||||
|
||||
pmu {
|
||||
compatible = "arm,cortex-a72-pmu";
|
||||
interrupt-parent = <&pic>;
|
||||
interrupts = <17>;
|
||||
};
|
||||
|
||||
odmi: odmi@300000 {
|
||||
compatible = "marvell,odmi-controller";
|
||||
msi-controller;
|
||||
|
||||
@@ -11,7 +11,6 @@ / {
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "marvell,armada-ap810-octa";
|
||||
|
||||
cpu0: cpu@0 {
|
||||
device_type = "cpu";
|
||||
|
||||
@@ -10,10 +10,9 @@
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
model = "Marvell Armada AP810";
|
||||
compatible = "marvell,armada-ap810";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
interrupt-parent = <&gic>;
|
||||
|
||||
aliases {
|
||||
serial0 = &uart0_ap0;
|
||||
@@ -25,14 +24,21 @@ psci {
|
||||
method = "smc";
|
||||
};
|
||||
|
||||
ap810-ap0 {
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
|
||||
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
|
||||
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
|
||||
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
|
||||
};
|
||||
|
||||
soc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
compatible = "simple-bus";
|
||||
interrupt-parent = <&gic>;
|
||||
ranges;
|
||||
|
||||
config-space@e8000000 {
|
||||
bus@e8000000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "simple-bus";
|
||||
@@ -62,14 +68,6 @@ gic_its_ap0: msi-controller@3040000 {
|
||||
};
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
|
||||
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
|
||||
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
|
||||
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
|
||||
};
|
||||
|
||||
xor@400000 {
|
||||
compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
|
||||
reg = <0x400000 0x1000>,
|
||||
|
||||
@@ -5,8 +5,4 @@
|
||||
* Device Tree file for Marvell Armada CP110.
|
||||
*/
|
||||
|
||||
#define CP11X_TYPE cp110
|
||||
|
||||
#include "armada-cp11x.dtsi"
|
||||
|
||||
#undef CP11X_TYPE
|
||||
|
||||
@@ -5,8 +5,4 @@
|
||||
* Device Tree file for Marvell Armada CP115.
|
||||
*/
|
||||
|
||||
#define CP11X_TYPE cp115
|
||||
|
||||
#include "armada-cp11x.dtsi"
|
||||
|
||||
#undef CP11X_TYPE
|
||||
|
||||
@@ -17,7 +17,7 @@ / {
|
||||
* The contents of the node are defined below, in order to
|
||||
* save one indentation level
|
||||
*/
|
||||
CP11X_NAME: CP11X_NAME { };
|
||||
CP11X_NAME: CP11X_NODE_NAME(bus) { };
|
||||
|
||||
/*
|
||||
* CPs only have one sensor in the thermal IC.
|
||||
@@ -51,7 +51,7 @@ &CP11X_NAME {
|
||||
interrupt-parent = <&CP11X_LABEL(icu_nsr)>;
|
||||
ranges;
|
||||
|
||||
config-space@CP11X_BASE {
|
||||
bus@CP11X_BASE {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "simple-bus";
|
||||
|
||||
@@ -7,9 +7,6 @@
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
/ {
|
||||
model = "SolidRun CN9130 SoM";
|
||||
compatible = "solidrun,cn9130-sr-som", "marvell,cn9130";
|
||||
|
||||
aliases {
|
||||
ethernet0 = &cp0_eth0;
|
||||
ethernet1 = &cp0_eth1;
|
||||
|
||||
Reference in New Issue
Block a user