mirrors/linux
2
0
Fork 0
mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git synced 2026-05-10 00:59:55 -04:00
Code Issues Packages Projects Releases Wiki Activity

drm/nouveau: add support for GB20x

Browse Source 
This commit adds support for the GB20x GPUs found on GeForce RTX 50xx
series boards.

Beyond a few miscellaneous register moves and HW class ID plumbing,
this reuses most of the code added to support GH100/GB10x.

Signed-off-by: Ben Skeggs <bskeggs@nvidia.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Timur Tabi <ttabi@nvidia.com>
Tested-by: Timur Tabi <ttabi@nvidia.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
Ben Skeggs
2025-02-04 08:54:57 +10:00
committed by Dave Airlie
parent 56c36f590a
commit 284ad706ad
32 changed files with 393 additions and 4 deletions
Download Patch File Download Diff File Expand all files Collapse all files

18
drivers/gpu/drm/nouveau/include/nvhw/ref/gb10b/dev_fbhub.h Normal file
View File

@@ -0,0 +1,18 @@
/* SPDX-License-Identifier: MIT
*
* Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved.
*/
#ifndef __gb10b_dev_fb_h__
#define __gb10b_dev_fb_h__
#define NV_PFB_FBHUB0_PCIE_FLUSH_SYSMEM_ADDR_LO 0x008a1d58 /* RW-4R */
#define NV_PFB_FBHUB0_PCIE_FLUSH_SYSMEM_ADDR_LO_ADR 31:0 /* RWIVF */
#define NV_PFB_FBHUB0_PCIE_FLUSH_SYSMEM_ADDR_LO_ADR_INIT 0x00000000 /* RWI-V */
#define NV_PFB_FBHUB0_PCIE_FLUSH_SYSMEM_ADDR_LO_ADR_MASK 0xffffff00 /* RW--V */
#define NV_PFB_FBHUB0_PCIE_FLUSH_SYSMEM_ADDR_HI 0x008a1d5c /* RW-4R */
#define NV_PFB_FBHUB0_PCIE_FLUSH_SYSMEM_ADDR_HI_ADR 31:0 /* RWIVF */
#define NV_PFB_FBHUB0_PCIE_FLUSH_SYSMEM_ADDR_HI_ADR_INIT 0x00000000 /* RWI-V */
#define NV_PFB_FBHUB0_PCIE_FLUSH_SYSMEM_ADDR_HI_ADR_MASK 0x000fffff /* RW--V */
#endif // __gb10b_dev_fb_h__

12
drivers/gpu/drm/nouveau/include/nvhw/ref/gb202/dev_ce.h Normal file
View File

@@ -0,0 +1,12 @@
/* SPDX-License-Identifier: MIT
*
* Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved.
*/
#ifndef __gb202_dev_ce_h__
#define __gb202_dev_ce_h__
#define NV_CE_GRCE_MASK 0x001040d8 /* C--4R */
#define NV_CE_GRCE_MASK_VALUE 9:0 /* C--VF */
#define NV_CE_GRCE_MASK_VALUE_INIT 0x00f /* C---V */
#endif // __gb202_dev_ce_h__

17
drivers/gpu/drm/nouveau/include/nvhw/ref/gb202/dev_therm.h Normal file
View File

@@ -0,0 +1,17 @@
/* SPDX-License-Identifier: MIT
*
* Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved.
*/
#ifndef __gb202_dev_therm_h__
#define __gb202_dev_therm_h__
#define NV_THERM_I2CS_SCRATCH 0x00ad00bc /* RW-4R */
#define NV_THERM_I2CS_SCRATCH_DATA 31:0 /* RWIVF */
#define NV_THERM_I2CS_SCRATCH_DATA_INIT 0x00000000 /* RWI-V */
#define NV_THERM_I2CS_SCRATCH_FSP_BOOT_COMPLETE NV_THERM_I2CS_SCRATCH
#define NV_THERM_I2CS_SCRATCH_FSP_BOOT_COMPLETE_STATUS 31:0
#define NV_THERM_I2CS_SCRATCH_FSP_BOOT_COMPLETE_STATUS_SUCCESS 0x000000FF
#define NV_THERM_I2CS_SCRATCH_FSP_BOOT_COMPLETE_STATUS_FAILED 0x00000000
#endif // __gb202_dev_therm_h__

15
drivers/gpu/drm/nouveau/include/nvif/class.h
View File

@@ -65,6 +65,7 @@
#define TURING_USERMODE_A 0x0000c461
#define AMPERE_USERMODE_A 0x0000c561
#define HOPPER_USERMODE_A 0x0000c661
#define BLACKWELL_USERMODE_A 0x0000c761
#define MAXWELL_FAULT_BUFFER_A /* clb069.h */ 0x0000b069
#define VOLTA_FAULT_BUFFER_A /* clb069.h */ 0x0000c369
@@ -89,6 +90,7 @@
#define AMPERE_CHANNEL_GPFIFO_B /* if0020.h */ 0x0000c76f
#define HOPPER_CHANNEL_GPFIFO_A 0x0000c86f
#define BLACKWELL_CHANNEL_GPFIFO_A 0x0000c96f
#define BLACKWELL_CHANNEL_GPFIFO_B 0x0000ca6f
#define NV50_DISP /* if0010.h */ 0x00005070
#define G82_DISP /* if0010.h */ 0x00008270
@@ -106,8 +108,10 @@
#define TU102_DISP /* if0010.h */ 0x0000c570
#define GA102_DISP /* if0010.h */ 0x0000c670
#define AD102_DISP /* if0010.h */ 0x0000c770
#define GB202_DISP 0x0000ca70
#define GV100_DISP_CAPS 0x0000c373
#define GB202_DISP_CAPS 0x0000ca73
#define NV31_MPEG 0x00003174
#define G82_MPEG 0x00008274
@@ -122,6 +126,7 @@
#define GV100_DISP_CURSOR /* if0014.h */ 0x0000c37a
#define TU102_DISP_CURSOR /* if0014.h */ 0x0000c57a
#define GA102_DISP_CURSOR /* if0014.h */ 0x0000c67a
#define GB202_DISP_CURSOR 0x0000ca7a
#define NV50_DISP_OVERLAY /* if0014.h */ 0x0000507b
#define G82_DISP_OVERLAY /* if0014.h */ 0x0000827b
@@ -132,6 +137,7 @@
#define GV100_DISP_WINDOW_IMM_CHANNEL_DMA /* if0014.h */ 0x0000c37b
#define TU102_DISP_WINDOW_IMM_CHANNEL_DMA /* if0014.h */ 0x0000c57b
#define GA102_DISP_WINDOW_IMM_CHANNEL_DMA /* if0014.h */ 0x0000c67b
#define GB202_DISP_WINDOW_IMM_CHANNEL_DMA 0x0000ca7b
#define NV50_DISP_BASE_CHANNEL_DMA /* if0014.h */ 0x0000507c
#define G82_DISP_BASE_CHANNEL_DMA /* if0014.h */ 0x0000827c
@@ -157,6 +163,7 @@
#define TU102_DISP_CORE_CHANNEL_DMA /* if0014.h */ 0x0000c57d
#define GA102_DISP_CORE_CHANNEL_DMA /* if0014.h */ 0x0000c67d
#define AD102_DISP_CORE_CHANNEL_DMA /* if0014.h */ 0x0000c77d
#define GB202_DISP_CORE_CHANNEL_DMA 0x0000ca7d
#define NV50_DISP_OVERLAY_CHANNEL_DMA /* if0014.h */ 0x0000507e
#define G82_DISP_OVERLAY_CHANNEL_DMA /* if0014.h */ 0x0000827e
@@ -168,6 +175,7 @@
#define GV100_DISP_WINDOW_CHANNEL_DMA /* if0014.h */ 0x0000c37e
#define TU102_DISP_WINDOW_CHANNEL_DMA /* if0014.h */ 0x0000c57e
#define GA102_DISP_WINDOW_CHANNEL_DMA /* if0014.h */ 0x0000c67e
#define GB202_DISP_WINDOW_CHANNEL_DMA 0x0000ca7e
#define NV50_TESLA 0x00005097
#define G82_TESLA 0x00008297
@@ -201,6 +209,7 @@
#define HOPPER_A 0x0000cb97
#define BLACKWELL_A 0x0000cd97
#define BLACKWELL_B 0x0000ce97
#define NV74_BSP 0x000074b0
@@ -210,6 +219,7 @@
#define NVC7B0_VIDEO_DECODER 0x0000c7b0
#define NVC9B0_VIDEO_DECODER 0x0000c9b0
#define NVCDB0_VIDEO_DECODER 0x0000cdb0
#define NVCFB0_VIDEO_DECODER 0x0000cfb0
#define GT212_MSVLD 0x000085b1
#define IGT21A_MSVLD 0x000086b1
@@ -240,10 +250,12 @@
#define AMPERE_DMA_COPY_B 0x0000c7b5
#define HOPPER_DMA_COPY_A 0x0000c8b5
#define BLACKWELL_DMA_COPY_A 0x0000c9b5
#define BLACKWELL_DMA_COPY_B 0x0000cab5
#define NVC4B7_VIDEO_ENCODER 0x0000c4b7
#define NVC7B7_VIDEO_ENCODER 0x0000c7b7
#define NVC9B7_VIDEO_ENCODER 0x0000c9b7
#define NVCFB7_VIDEO_ENCODER 0x0000cfb7
#define FERMI_DECOMPRESS 0x000090b8
@@ -264,6 +276,7 @@
#define ADA_COMPUTE_A 0x0000c9c0
#define HOPPER_COMPUTE_A 0x0000cbc0
#define BLACKWELL_COMPUTE_A 0x0000cdc0
#define BLACKWELL_COMPUTE_B 0x0000cec0
#define NV74_CIPHER 0x000074c1
@@ -271,10 +284,12 @@
#define NVC4D1_VIDEO_NVJPG 0x0000c4d1
#define NVC9D1_VIDEO_NVJPG 0x0000c9d1
#define NVCDD1_VIDEO_NVJPG 0x0000cdd1
#define NVCFD1_VIDEO_NVJPG 0x0000cfd1
#define NVB8FA_VIDEO_OFA 0x0000b8fa
#define NVC6FA_VIDEO_OFA 0x0000c6fa
#define NVC7FA_VIDEO_OFA 0x0000c7fa
#define NVC9FA_VIDEO_OFA 0x0000c9fa
#define NVCDFA_VIDEO_OFA 0x0000cdfa
#define NVCFFA_VIDEO_OFA 0x0000cffa
#endif

1
drivers/gpu/drm/nouveau/include/nvkm/core/device.h
View File

@@ -49,6 +49,7 @@ struct nvkm_device {
GH100 = 0x180,
AD100 = 0x190,
GB10x = 0x1a0,
GB20x = 0x1b0,
} card_type;
u32 chipset;
u8 chiprev;

1
drivers/gpu/drm/nouveau/include/nvkm/subdev/fb.h
View File

@@ -104,6 +104,7 @@ int ga100_fb_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct n
int ga102_fb_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fb **);
int gh100_fb_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fb **);
int gb100_fb_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fb **);
int gb202_fb_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fb **);
#include <subdev/bios.h>
#include <subdev/bios/ramcfg.h>

1
drivers/gpu/drm/nouveau/include/nvkm/subdev/fsp.h
View File

@@ -20,4 +20,5 @@ int nvkm_fsp_boot_gsp_fmc(struct nvkm_fsp *, u64 args_addr, u32 rsvd_size, bool
int gh100_fsp_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fsp **);
int gb100_fsp_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fsp **);
int gb202_fsp_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_fsp **);
#endif

1
drivers/gpu/drm/nouveau/include/nvkm/subdev/gsp.h
View File

@@ -493,4 +493,5 @@ int ga102_gsp_new(struct nvkm_device *, enum nvkm_subdev_type, int, struct nvkm_
int gh100_gsp_new(struct nvkm_device *, enum nvkm_subdev_type, int, struct nvkm_gsp **);
int ad102_gsp_new(struct nvkm_device *, enum nvkm_subdev_type, int, struct nvkm_gsp **);
int gb100_gsp_new(struct nvkm_device *, enum nvkm_subdev_type, int, struct nvkm_gsp **);
int gb202_gsp_new(struct nvkm_device *, enum nvkm_subdev_type, int, struct nvkm_gsp **);
#endif

1
drivers/gpu/drm/nouveau/nouveau_bo.c
View File

@@ -1000,6 +1000,7 @@ nouveau_bo_move_init(struct nouveau_drm *drm)
struct ttm_resource *, struct ttm_resource *);
int (*init)(struct nouveau_channel *, u32 handle);
} _methods[] = {
{ "COPY", 4, 0xcab5, nve0_bo_move_copy, nve0_bo_move_init },
{ "COPY", 4, 0xc9b5, nve0_bo_move_copy, nve0_bo_move_init },
{ "COPY", 4, 0xc8b5, nve0_bo_move_copy, nve0_bo_move_init },
{ "COPY", 4, 0xc7b5, nve0_bo_move_copy, nve0_bo_move_init },

1
drivers/gpu/drm/nouveau/nouveau_chan.c
View File

@@ -249,6 +249,7 @@ nouveau_channel_ctor(struct nouveau_cli *cli, bool priv, u64 runm,
struct nouveau_channel **pchan)
{
const struct nvif_mclass hosts[] = {
{ BLACKWELL_CHANNEL_GPFIFO_B, 0 },
{ BLACKWELL_CHANNEL_GPFIFO_A, 0 },
{ HOPPER_CHANNEL_GPFIFO_A, 0 },
{ AMPERE_CHANNEL_GPFIFO_B, 0 },

1
drivers/gpu/drm/nouveau/nouveau_drm.c
View File

@@ -511,6 +511,7 @@ nouveau_accel_init(struct nouveau_drm *drm)
case AMPERE_CHANNEL_GPFIFO_B:
case HOPPER_CHANNEL_GPFIFO_A:
case BLACKWELL_CHANNEL_GPFIFO_A:
case BLACKWELL_CHANNEL_GPFIFO_B:
ret = gv100_fence_create(drm);
break;
default:

9
drivers/gpu/drm/nouveau/nvif/user.c
View File

@@ -41,10 +41,11 @@ nvif_user_ctor(struct nvif_device *device, const char *name)
int version;
const struct nvif_user_func *func;
} users[] = {
{ HOPPER_USERMODE_A, -1, &nvif_userc361 },
{ AMPERE_USERMODE_A, -1, &nvif_userc361 },
{ TURING_USERMODE_A, -1, &nvif_userc361 },
{ VOLTA_USERMODE_A, -1, &nvif_userc361 },
{ BLACKWELL_USERMODE_A, -1, &nvif_userc361 },
{ HOPPER_USERMODE_A, -1, &nvif_userc361 },
{ AMPERE_USERMODE_A, -1, &nvif_userc361 },
{ TURING_USERMODE_A, -1, &nvif_userc361 },
{ VOLTA_USERMODE_A, -1, &nvif_userc361 },
{}
};
int cid, ret;

1
drivers/gpu/drm/nouveau/nvkm/engine/ce/Kbuild
View File

@@ -10,3 +10,4 @@ nvkm-y += nvkm/engine/ce/gv100.o
nvkm-y += nvkm/engine/ce/tu102.o
nvkm-y += nvkm/engine/ce/ga100.o
nvkm-y += nvkm/engine/ce/ga102.o
nvkm-y += nvkm/engine/ce/gb202.o

16
drivers/gpu/drm/nouveau/nvkm/engine/ce/gb202.c Normal file
View File

@@ -0,0 +1,16 @@
/* SPDX-License-Identifier: MIT
*
* Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved.
*/
#include "priv.h"
#include <nvhw/drf.h>
#include <nvhw/ref/gb202/dev_ce.h>
u32
gb202_ce_grce_mask(struct nvkm_device *device)
{
u32 data = nvkm_rd32(device, NV_CE_GRCE_MASK);
return NVVAL_GET(data, NV_CE, GRCE_MASK, VALUE);
}

2
drivers/gpu/drm/nouveau/nvkm/engine/ce/priv.h
View File

@@ -16,4 +16,6 @@ int ga100_ce_oneinit(struct nvkm_engine *);
int ga100_ce_init(struct nvkm_engine *);
int ga100_ce_fini(struct nvkm_engine *, bool);
int ga100_ce_nonstall(struct nvkm_engine *);
u32 gb202_ce_grce_mask(struct nvkm_device *);
#endif

86
drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
View File

@@ -2832,6 +2832,86 @@ nv1a2_chipset = {
.fifo = { 0x00000001, ga102_fifo_new },
};
static const struct nvkm_device_chip
nv1b2_chipset = {
.name = "GB202",
.bar = { 0x00000001, tu102_bar_new },
.fb = { 0x00000001, gb202_fb_new },
.fsp = { 0x00000001, gb202_fsp_new },
.gsp = { 0x00000001, gb202_gsp_new },
.imem = { 0x00000001, gh100_instmem_new },
.mmu = { 0x00000001, gh100_mmu_new },
.pci = { 0x00000001, gh100_pci_new },
.timer = { 0x00000001, gk20a_timer_new },
.vfn = { 0x00000001, ga100_vfn_new },
.disp = { 0x00000001, ga102_disp_new },
.fifo = { 0x00000001, ga102_fifo_new },
};
static const struct nvkm_device_chip
nv1b3_chipset = {
.name = "GB203",
.bar = { 0x00000001, tu102_bar_new },
.fb = { 0x00000001, gb202_fb_new },
.fsp = { 0x00000001, gb202_fsp_new },
.gsp = { 0x00000001, gb202_gsp_new },
.imem = { 0x00000001, gh100_instmem_new },
.mmu = { 0x00000001, gh100_mmu_new },
.pci = { 0x00000001, gh100_pci_new },
.timer = { 0x00000001, gk20a_timer_new },
.vfn = { 0x00000001, ga100_vfn_new },
.disp = { 0x00000001, ga102_disp_new },
.fifo = { 0x00000001, ga102_fifo_new },
};
static const struct nvkm_device_chip
nv1b5_chipset = {
.name = "GB205",
.bar = { 0x00000001, tu102_bar_new },
.fb = { 0x00000001, gb202_fb_new },
.fsp = { 0x00000001, gb202_fsp_new },
.gsp = { 0x00000001, gb202_gsp_new },
.imem = { 0x00000001, gh100_instmem_new },
.mmu = { 0x00000001, gh100_mmu_new },
.pci = { 0x00000001, gh100_pci_new },
.timer = { 0x00000001, gk20a_timer_new },
.vfn = { 0x00000001, ga100_vfn_new },
.disp = { 0x00000001, ga102_disp_new },
.fifo = { 0x00000001, ga102_fifo_new },
};
static const struct nvkm_device_chip
nv1b6_chipset = {
.name = "GB206",
.bar = { 0x00000001, tu102_bar_new },
.fb = { 0x00000001, gb202_fb_new },
.fsp = { 0x00000001, gb202_fsp_new },
.gsp = { 0x00000001, gb202_gsp_new },
.imem = { 0x00000001, gh100_instmem_new },
.mmu = { 0x00000001, gh100_mmu_new },
.pci = { 0x00000001, gh100_pci_new },
.timer = { 0x00000001, gk20a_timer_new },
.vfn = { 0x00000001, ga100_vfn_new },
.disp = { 0x00000001, ga102_disp_new },
.fifo = { 0x00000001, ga102_fifo_new },
};
static const struct nvkm_device_chip
nv1b7_chipset = {
.name = "GB207",
.bar = { 0x00000001, tu102_bar_new },
.fb = { 0x00000001, gb202_fb_new },
.fsp = { 0x00000001, gb202_fsp_new },
.gsp = { 0x00000001, gb202_gsp_new },
.imem = { 0x00000001, gh100_instmem_new },
.mmu = { 0x00000001, gh100_mmu_new },
.pci = { 0x00000001, gh100_pci_new },
.timer = { 0x00000001, gk20a_timer_new },
.vfn = { 0x00000001, ga100_vfn_new },
.disp = { 0x00000001, ga102_disp_new },
.fifo = { 0x00000001, ga102_fifo_new },
};
struct nvkm_subdev *
nvkm_device_subdev(struct nvkm_device *device, int type, int inst)
{
@@ -3150,6 +3230,7 @@ nvkm_device_ctor(const struct nvkm_device_func *func,
case 0x180: device->card_type = GH100; break;
case 0x190: device->card_type = AD100; break;
case 0x1a0: device->card_type = GB10x; break;
case 0x1b0: device->card_type = GB20x; break;
default:
break;
}
@@ -3260,6 +3341,11 @@ nvkm_device_ctor(const struct nvkm_device_func *func,
case 0x197: device->chip = &nv197_chipset; break;
case 0x1a0: device->chip = &nv1a0_chipset; break;
case 0x1a2: device->chip = &nv1a2_chipset; break;
case 0x1b2: device->chip = &nv1b2_chipset; break;
case 0x1b3: device->chip = &nv1b3_chipset; break;
case 0x1b5: device->chip = &nv1b5_chipset; break;
case 0x1b6: device->chip = &nv1b6_chipset; break;
case 0x1b7: device->chip = &nv1b7_chipset; break;
default:
if (nvkm_boolopt(device->cfgopt, "NvEnableUnsupportedChipsets", false)) {
switch (device->chipset) {

1
drivers/gpu/drm/nouveau/nvkm/engine/device/user.c
View File

@@ -150,6 +150,7 @@ nvkm_udevice_info(struct nvkm_udevice *udev, void *data, u32 size)
case AD100: args->v0.family = NV_DEVICE_INFO_V0_ADA; break;
case GH100: args->v0.family = NV_DEVICE_INFO_V0_HOPPER; break;
case GB10x: args->v0.family = NV_DEVICE_INFO_V0_BLACKWELL; break;
case GB20x: args->v0.family = NV_DEVICE_INFO_V0_BLACKWELL; break;
default:
args->v0.family = 0;
break;

1
drivers/gpu/drm/nouveau/nvkm/engine/fifo/Kbuild
View File

@@ -25,6 +25,7 @@ nvkm-y += nvkm/engine/fifo/gv100.o
nvkm-y += nvkm/engine/fifo/tu102.o
nvkm-y += nvkm/engine/fifo/ga100.o
nvkm-y += nvkm/engine/fifo/ga102.o
nvkm-y += nvkm/engine/fifo/gb202.o
nvkm-y += nvkm/engine/fifo/ucgrp.o
nvkm-y += nvkm/engine/fifo/uchan.o

14
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gb202.c Normal file
View File

@@ -0,0 +1,14 @@
/* SPDX-License-Identifier: MIT
*
* Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved.
*/
#include "priv.h"
#include "cgrp.h"
#include "chan.h"
#include "runl.h"
u32
gb202_chan_doorbell_handle(struct nvkm_chan *chan)
{
return BIT(30) | (chan->cgrp->runl->id << 16) | chan->id;
}

2
drivers/gpu/drm/nouveau/nvkm/engine/fifo/priv.h
View File

@@ -208,6 +208,8 @@ extern const struct nvkm_engn_func ga100_engn_ce;
extern const struct nvkm_cgrp_func ga100_cgrp;
extern const struct nvkm_chan_func ga100_chan;
u32 gb202_chan_doorbell_handle(struct nvkm_chan *);
int nvkm_uchan_new(struct nvkm_fifo *, struct nvkm_cgrp *, const struct nvkm_oclass *,
void *argv, u32 argc, struct nvkm_object **);
int nvkm_ucgrp_new(struct nvkm_fifo *, const struct nvkm_oclass *, void *argv, u32 argc,

1
drivers/gpu/drm/nouveau/nvkm/subdev/fb/Kbuild
View File

@@ -37,6 +37,7 @@ nvkm-y += nvkm/subdev/fb/ga100.o
nvkm-y += nvkm/subdev/fb/ga102.o
nvkm-y += nvkm/subdev/fb/gh100.o
nvkm-y += nvkm/subdev/fb/gb100.o
nvkm-y += nvkm/subdev/fb/gb202.o
nvkm-y += nvkm/subdev/fb/r535.o

30
drivers/gpu/drm/nouveau/nvkm/subdev/fb/gb202.c Normal file
View File

@@ -0,0 +1,30 @@
/* SPDX-License-Identifier: MIT
*
* Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved.
*/
#include "priv.h"
#include <nvhw/drf.h>
#include <nvhw/ref/gb10b/dev_fbhub.h>
static void
gb202_fb_sysmem_flush_page_init(struct nvkm_fb *fb)
{
struct nvkm_device *device = fb->subdev.device;
const u64 addr = fb->sysmem.flush_page_addr;
nvkm_wr32(device, NV_PFB_FBHUB0_PCIE_FLUSH_SYSMEM_ADDR_HI, upper_32_bits(addr));
nvkm_wr32(device, NV_PFB_FBHUB0_PCIE_FLUSH_SYSMEM_ADDR_LO, lower_32_bits(addr));
}
static const struct nvkm_fb_func
gb202_fb = {
.sysmem.flush_page_init = gb202_fb_sysmem_flush_page_init,
.vidmem.size = ga102_fb_vidmem_size,
};
int
gb202_fb_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst, struct nvkm_fb **pfb)
{
return r535_fb_new(&gb202_fb, device, type, inst, pfb);
}

1
drivers/gpu/drm/nouveau/nvkm/subdev/fsp/Kbuild
View File

@@ -5,3 +5,4 @@
nvkm-y += nvkm/subdev/fsp/base.o
nvkm-y += nvkm/subdev/fsp/gh100.o
nvkm-y += nvkm/subdev/fsp/gb100.o
nvkm-y += nvkm/subdev/fsp/gb202.o

45
drivers/gpu/drm/nouveau/nvkm/subdev/fsp/gb202.c Normal file
View File

@@ -0,0 +1,45 @@
/* SPDX-License-Identifier: MIT
*
* Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved.
*/
#include "priv.h"
#include <nvhw/drf.h>
#include <nvhw/ref/gb202/dev_therm.h>
static int
gb202_fsp_wait_secure_boot(struct nvkm_fsp *fsp)
{
struct nvkm_device *device = fsp->subdev.device;
unsigned timeout_ms = 4000;
do {
u32 status = NVKM_RD32(device, NV_THERM, I2CS_SCRATCH, FSP_BOOT_COMPLETE_STATUS);
if (status == NV_THERM_I2CS_SCRATCH_FSP_BOOT_COMPLETE_STATUS_SUCCESS)
return 0;
usleep_range(1000, 2000);
} while (timeout_ms--);
return -ETIMEDOUT;
}
static const struct nvkm_fsp_func
gb202_fsp = {
.wait_secure_boot = gb202_fsp_wait_secure_boot,
.cot = {
.version = 2,
.size_hash = 48,
.size_pkey = 97,
.size_sig = 96,
.boot_gsp_fmc = gh100_fsp_boot_gsp_fmc,
},
};
int
gb202_fsp_new(struct nvkm_device *device,
enum nvkm_subdev_type type, int inst, struct nvkm_fsp **pfsp)
{
return nvkm_fsp_new_(&gb202_fsp, device, type, inst, pfsp);
}

1
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/Kbuild
View File

@@ -10,5 +10,6 @@ nvkm-y += nvkm/subdev/gsp/ga102.o
nvkm-y += nvkm/subdev/gsp/gh100.o
nvkm-y += nvkm/subdev/gsp/ad102.o
nvkm-y += nvkm/subdev/gsp/gb100.o
nvkm-y += nvkm/subdev/gsp/gb202.o
include $(src)/nvkm/subdev/gsp/rm/Kbuild

38
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/gb202.c Normal file
View File

@@ -0,0 +1,38 @@
/* SPDX-License-Identifier: MIT
*
* Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved.
*/
#include "priv.h"
static const struct nvkm_gsp_func
gb202_gsp = {
.flcn = &ga102_gsp_flcn,
.sig_section = ".fwsignature_gb20x",
.dtor = r535_gsp_dtor,
.oneinit = gh100_gsp_oneinit,
.init = gh100_gsp_init,
.fini = gh100_gsp_fini,
.rm.gpu = &gb20x_gpu,
};
static struct nvkm_gsp_fwif
gb202_gsps[] = {
{ 0, gh100_gsp_load, &gb202_gsp, &r570_rm_gb20x, "570.144", true },
{}
};
int
gb202_gsp_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
struct nvkm_gsp **pgsp)
{
return nvkm_gsp_new_(gb202_gsps, device, type, inst, pgsp);
}
NVKM_GSP_FIRMWARE_FMC(gb202, 570.144);
NVKM_GSP_FIRMWARE_FMC(gb203, 570.144);
NVKM_GSP_FIRMWARE_FMC(gb205, 570.144);
NVKM_GSP_FIRMWARE_FMC(gb206, 570.144);
NVKM_GSP_FIRMWARE_FMC(gb207, 570.144);

1
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/Kbuild
View File

@@ -13,6 +13,7 @@ nvkm-y += nvkm/subdev/gsp/rm/ga1xx.o
nvkm-y += nvkm/subdev/gsp/rm/ad10x.o
nvkm-y += nvkm/subdev/gsp/rm/gh100.o
nvkm-y += nvkm/subdev/gsp/rm/gb10x.o
nvkm-y += nvkm/subdev/gsp/rm/gb20x.o
include $(src)/nvkm/subdev/gsp/rm/r535/Kbuild
include $(src)/nvkm/subdev/gsp/rm/r570/Kbuild

44
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/gb20x.c Normal file
View File

@@ -0,0 +1,44 @@
/* SPDX-License-Identifier: MIT
*
* Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved.
*/
#include "gpu.h"
#include <engine/ce/priv.h>
#include <engine/fifo/priv.h>
#include <nvif/class.h>
const struct nvkm_rm_gpu
gb20x_gpu = {
.disp.class = {
.root = GB202_DISP,
.caps = GB202_DISP_CAPS,
.core = GB202_DISP_CORE_CHANNEL_DMA,
.wndw = GB202_DISP_WINDOW_CHANNEL_DMA,
.wimm = GB202_DISP_WINDOW_IMM_CHANNEL_DMA,
.curs = GB202_DISP_CURSOR,
},
.usermode.class = BLACKWELL_USERMODE_A,
.fifo.chan = {
.class = BLACKWELL_CHANNEL_GPFIFO_B,
.doorbell_handle = gb202_chan_doorbell_handle,
},
.ce = {
.class = BLACKWELL_DMA_COPY_B,
.grce_mask = gb202_ce_grce_mask,
},
.gr.class = {
.i2m = BLACKWELL_INLINE_TO_MEMORY_A,
.twod = FERMI_TWOD_A,
.threed = BLACKWELL_B,
.compute = BLACKWELL_COMPUTE_B,
},
.nvdec.class = NVCFB0_VIDEO_DECODER,
.nvenc.class = NVCFB7_VIDEO_ENCODER,
.nvjpg.class = NVCFD1_VIDEO_NVJPG,
.ofa.class = NVCFFA_VIDEO_OFA,
};

2
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/gpu.h
View File

@@ -31,6 +31,7 @@ struct nvkm_rm_gpu {
struct {
u32 class;
u32 (*grce_mask)(struct nvkm_device *);
} ce;
struct {
@@ -65,4 +66,5 @@ extern const struct nvkm_rm_gpu ga1xx_gpu;
extern const struct nvkm_rm_gpu ad10x_gpu;
extern const struct nvkm_rm_gpu gh100_gpu;
extern const struct nvkm_rm_gpu gb10x_gpu;
extern const struct nvkm_rm_gpu gb20x_gpu;
#endif

16
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/fifo.c
View File

@@ -507,6 +507,22 @@ r535_fifo_runl_ctor(struct nvkm_fifo *fifo)
continue;
}
/* Skip SW engine - there's currently no support for NV SW classes. */
if (type == NVKM_ENGINE_SW)
continue;
/* Skip lone GRCEs (ones not paired with GR on a runlist), as they
* don't appear to function as async copy engines.
*/
if (type == NVKM_ENGINE_CE &&
rm->gpu->ce.grce_mask &&
(rm->gpu->ce.grce_mask(device) & BIT(inst)) &&
!nvkm_runl_find_engn(engn, runl, engn->engine->subdev.type == NVKM_ENGINE_GR)) {
RUNL_DEBUG(runl, "skip LCE %d - GRCE without GR", inst);
nvkm_runl_del(runl);
continue;
}
ret = nvkm_rm_engine_new(gsp->rm, type, inst);
if (ret) {
nvkm_runl_del(runl);

16
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r570/rm.c
View File

@@ -39,6 +39,16 @@ r570_wpr_libos3_gb10x = {
.offset_set_by_acr = true,
};
static const struct nvkm_rm_wpr
r570_wpr_libos3_gb20x = {
.os_carveout_size = GSP_FW_HEAP_PARAM_OS_SIZE_LIBOS3_BAREMETAL,
.base_size = GSP_FW_HEAP_PARAM_BASE_RM_SIZE_GH100,
.heap_size_min = GSP_FW_HEAP_SIZE_OVERRIDE_LIBOS3_BAREMETAL_MIN_MB,
.heap_size_non_wpr = 0x220000,
.rsvd_size_pmu = ALIGN(0x0800000 + 0x1000000 + 0x0001000, 0x20000),
.offset_set_by_acr = true,
};
static const struct nvkm_rm_api
r570_api = {
.gsp = &r570_gsp,
@@ -81,3 +91,9 @@ r570_rm_gb10x = {
.wpr = &r570_wpr_libos3_gb10x,
.api = &r570_api,
};
const struct nvkm_rm_impl
r570_rm_gb20x = {
.wpr = &r570_wpr_libos3_gb20x,
.api = &r570_api,
};

1
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/rm.h
View File

@@ -178,6 +178,7 @@ extern const struct nvkm_rm_impl r570_rm_tu102;
extern const struct nvkm_rm_impl r570_rm_ga102;
extern const struct nvkm_rm_impl r570_rm_gh100;
extern const struct nvkm_rm_impl r570_rm_gb10x;
extern const struct nvkm_rm_impl r570_rm_gb20x;
extern const struct nvkm_rm_api_gsp r570_gsp;
extern const struct nvkm_rm_api_client r570_client;
extern const struct nvkm_rm_api_fbsr r570_fbsr;