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drm/nouveau/gsp: add hal for fifo.chan.doorbell_handle

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The doorbell register on GB20x GPUs has additional fields.

Signed-off-by: Ben Skeggs <bskeggs@nvidia.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Timur Tabi <ttabi@nvidia.com>
Tested-by: Timur Tabi <ttabi@nvidia.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
Ben Skeggs
2025-02-26 07:49:00 +10:00
committed by Dave Airlie
parent 32cb1cc358
commit 56c36f590a
10 changed files with 25 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/gpu/drm/nouveau/nvkm/engine/fifo/priv.h
View File

@@ -6,6 +6,7 @@
#include <core/enum.h>
struct nvkm_cctx;
struct nvkm_cgrp;
struct nvkm_chan;
struct nvkm_engn;
struct nvkm_memory;
struct nvkm_runl;
@@ -195,6 +196,7 @@ extern const struct nvkm_chan_func_ramfc gv100_chan_ramfc;
void tu102_fifo_intr_ctxsw_timeout_info(struct nvkm_engn *, u32 info);
extern const struct nvkm_fifo_func_mmu_fault tu102_fifo_mmu_fault;
u32 tu102_chan_doorbell_handle(struct nvkm_chan *);
int ga100_fifo_runl_ctor(struct nvkm_fifo *);
int ga100_fifo_nonstall_ctor(struct nvkm_fifo *);

2
drivers/gpu/drm/nouveau/nvkm/engine/fifo/tu102.c
View File

@@ -31,7 +31,7 @@
#include <nvif/class.h>
static u32
u32
tu102_chan_doorbell_handle(struct nvkm_chan *chan)
{
return (chan->cgrp->runl->id << 16) | chan->id;

3
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/ad10x.c
View File

@@ -4,6 +4,8 @@
*/
#include "gpu.h"
#include <engine/fifo/priv.h>
#include <nvif/class.h>
const struct nvkm_rm_gpu
@@ -21,6 +23,7 @@ ad10x_gpu = {
.fifo.chan = {
.class = AMPERE_CHANNEL_GPFIFO_A,
.doorbell_handle = tu102_chan_doorbell_handle,
},
.ce.class = AMPERE_DMA_COPY_B,

3
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/ga100.c
View File

@@ -4,6 +4,8 @@
*/
#include "gpu.h"
#include <engine/fifo/priv.h>
#include <nvif/class.h>
const struct nvkm_rm_gpu
@@ -12,6 +14,7 @@ ga100_gpu = {
.fifo.chan = {
.class = AMPERE_CHANNEL_GPFIFO_A,
.doorbell_handle = tu102_chan_doorbell_handle,
},
.ce.class = AMPERE_DMA_COPY_A,

3
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/ga1xx.c
View File

@@ -4,6 +4,8 @@
*/
#include "gpu.h"
#include <engine/fifo/priv.h>
#include <nvif/class.h>
const struct nvkm_rm_gpu
@@ -21,6 +23,7 @@ ga1xx_gpu = {
.fifo.chan = {
.class = AMPERE_CHANNEL_GPFIFO_A,
.doorbell_handle = tu102_chan_doorbell_handle,
},
.ce.class = AMPERE_DMA_COPY_B,

3
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/gb10x.c
View File

@@ -4,6 +4,8 @@
*/
#include "gpu.h"
#include <engine/fifo/priv.h>
#include <nvif/class.h>
const struct nvkm_rm_gpu
@@ -12,6 +14,7 @@ gb10x_gpu = {
.fifo.chan = {
.class = BLACKWELL_CHANNEL_GPFIFO_A,
.doorbell_handle = tu102_chan_doorbell_handle,
},
.ce.class = BLACKWELL_DMA_COPY_A,

3
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/gh100.c
View File

@@ -4,6 +4,8 @@
*/
#include "gpu.h"
#include <engine/fifo/priv.h>
#include <nvif/class.h>
const struct nvkm_rm_gpu
@@ -12,6 +14,7 @@ gh100_gpu = {
.fifo.chan = {
.class = HOPPER_CHANNEL_GPFIFO_A,
.doorbell_handle = tu102_chan_doorbell_handle,
},
.ce.class = HOPPER_DMA_COPY_A,

1
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/gpu.h
View File

@@ -25,6 +25,7 @@ struct nvkm_rm_gpu {
struct {
struct {
u32 class;
u32 (*doorbell_handle)(struct nvkm_chan *);
} chan;
} fifo;

4
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/fifo.c
View File

@@ -41,7 +41,9 @@
static u32
r535_chan_doorbell_handle(struct nvkm_chan *chan)
{
return (chan->cgrp->runl->id << 16) | chan->id;
struct nvkm_gsp *gsp = chan->rm.object.client->gsp;
return gsp->rm->gpu->fifo.chan.doorbell_handle(chan);
}
static void

3
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/tu1xx.c
View File

@@ -4,6 +4,8 @@
*/
#include "gpu.h"
#include <engine/fifo/priv.h>
#include <nvif/class.h>
const struct nvkm_rm_gpu
@@ -21,6 +23,7 @@ tu1xx_gpu = {
.fifo.chan = {
.class = TURING_CHANNEL_GPFIFO_A,
.doorbell_handle = tu102_chan_doorbell_handle,
},
.ce.class = TURING_DMA_COPY_A,