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Merge tag 'imx-dt-7.2' of git://git.kernel.org/pub/scm/linux/kernel/git/frank.li/linux into soc/dt

Browse Source 
i.MX ARM device tree changes for 7.2:

DT Binding Cleanup:
- Replaced undocumented compatible strings with proper ones:
  * edt,edt-ft5x06 -> edt,edt-ft5206
  * marvell,88E1510 -> ethernet-phy-ieee802.3-c22
  * karo,imx6qdl-tx6-sgtl5000 -> simple-audio-card
- Fixed incorrect VAR-SOM-MX6UL references (corrected to VAR-SOM-MX6)
- Added missing required properties:
  * #phy-cells for usb-nop-xceiv
  * #io-channel-cells to ADC nodes
  * bus-type for ov5642/ov5640 cameras
  * ti,deskew = <0> for ti,tfp410
- Added missing supply properties (power-supply, vdd-supply, dvdd-supply, avdd-supply)
- Removed redundant/empty properties (bus-width for video-mux, empty clock-names)
- Fixed boolean property warnings and non-existent property references
- Converted TS-4800 watchdog to DT schema
- Renamed wdt nodes to watchdog for consistency

New Features Added:
- PCIe Root Port nodes and PERST property for imx6qdl, imx6sx, and imx7d
- OV5645 camera support for imx7d-pico-pi
- LVDS display panel support for imx6ul-var-som
- WiFi and Bluetooth support for VAR-SOM boards
- nvmem-layout support for imx7
- New bus bindings: fsl,aipi-bus and fsl,emi-bus
- New board binding: variscite,var-som-imx6ull

Code Refactoring:
- VAR-SOM-MX6UL/ULL: factored out common parts for CPU variants
- Separated audio, ethernet (ENET1/ENET2), and SD card support into reusable components

* tag 'imx-dt-7.2' of git://git.kernel.org/pub/scm/linux/kernel/git/frank.li/linux: (35 commits)
  dt-bindings: soc: imx: Add fsl,aipi-bus and fsl,emi-bus
  ARM: dts: freescale: add bootph-all to i.MX7ULP watchdog nodes
  ARM: dts: imx7: add nvmem-layout
  ARM: dts: imx7d-pico-pi: add OV5645 camera support
  ARM: dts: imx6-display5: replace marvell,88E1510 with ethernet-phy-ieee802.3-c22
  ARM: dts: imx: replace undocumented compatible string edt,edt-ft5x06 with edt,edt-ft5206
  ARM: dts: imx6qdl-tx6: remove undocumented karo,imx6qdl-tx6-sgtl5000 and keep only simple-audio-card
  ARM: dts: imx: Add bus-type for ov5642/ov5640
  ARM: dts: imx: remove redundant bus-width for video-mux
  ARM: dts: imx: add (power|vdd)-supply for related node
  ARM: dts: imx53-ppd: add '#phy-cells' for usb-nop-xceiv
  ARM: dts: imx53-qsb: add dvdd and avdd supply for panel sii,43wvf1g
  ARM: dts: imx: add ti,deskew = <0> for ti,tfp410
  ARM: dts: imx7d: Add Root Port node and PERST property
  ARM: dts: imx6sx: Add Root Port node and PERST property
  ARM: dts: imx6qdl: Add Root Port node and PERST property
  ARM: dts: nxp: imx51-ts4800: Rename wdt node to watchdog
  dt-bindings: watchdog: Convert TS-4800 to DT schema
  ARM: dts: imx6ul: add #io-channel-cells to ADC
  ARM: dts: imx25: remove empty clock-names for nand-controller@bb000000
  ...

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
2026-06-09 18:00:12 +02:00
parent b55ed73106 8772e1f64c
commit 1c00051aa2
67 changed files with 1146 additions and 597 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
Documentation/devicetree/bindings/arm/fsl.yaml
View File

@@ -688,7 +688,7 @@ properties:
- const: phytec,imx6ul-pcl063 # PHYTEC phyCORE-i.MX 6UL
- const: fsl,imx6ul
- description: i.MX6UL Variscite VAR-SOM-MX6 Boards
- description: i.MX6UL Variscite VAR-SOM-6UL Boards
items:
- const: variscite,mx6ulconcerto
- const: variscite,var-som-imx6ul
@@ -797,6 +797,12 @@ properties:
- const: phytec,imx6ull-pcl063 # PHYTEC phyCORE-i.MX 6ULL
- const: fsl,imx6ull
- description: i.MX6ULL Variscite VAR-SOM-6UL Boards
items:
- const: variscite,mx6ullconcerto # Variscite VAR-SOM-6UL dev kit board
- const: variscite,var-som-imx6ull # Variscite VAR-SOM-6UL SoM (6ULL variant)
- const: fsl,imx6ull
- description: i.MX6ULL Boards with Toradex Colibri iMX6ULL Modules
items:
- enum:

4
Documentation/devicetree/bindings/bus/fsl,spba-bus.yaml
View File

@@ -26,8 +26,10 @@ select:
compatible:
contains:
enum:
- fsl,aipi-bus
- fsl,aips
- fsl,emi
- fsl,emi-bus
- fsl,spba-bus
required:
- compatible
@@ -39,8 +41,10 @@ properties:
compatible:
items:
- enum:
- fsl,aipi-bus
- fsl,aips
- fsl,emi
- fsl,emi-bus
- fsl,spba-bus
- const: simple-bus

40
Documentation/devicetree/bindings/watchdog/technologic,ts4800-wdt.yaml Normal file
View File

@@ -0,0 +1,40 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/watchdog/technologic,ts4800-wdt.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Technologic Systems TS-4800 Watchdog
maintainers:
- Eduard Bostina <egbostina@gmail.com>
properties:
compatible:
const: technologic,ts4800-wdt
syscon:
$ref: /schemas/types.yaml#/definitions/phandle-array
items:
- items:
- description: Phandle to the FPGA's syscon
- description: Offset to the watchdog register
description: Phandle / integers array that points to the syscon node which
describes the FPGA's syscon registers.
required:
- compatible
- syscon
allOf:
- $ref: watchdog.yaml#
unevaluatedProperties: false
examples:
- |
watchdog {
compatible = "technologic,ts4800-wdt";
syscon = <&syscon 0xe>;
timeout-sec = <10>;
};

25
Documentation/devicetree/bindings/watchdog/ts4800-wdt.txt
View File

@@ -1,25 +0,0 @@
Technologic Systems Watchdog
Required properties:
- compatible: must be "technologic,ts4800-wdt"
- syscon: phandle / integer array that points to the syscon node which
describes the FPGA's syscon registers.
- phandle to FPGA's syscon
- offset to the watchdog register
Optional property:
- timeout-sec: contains the watchdog timeout in seconds.
Example:
syscon: syscon@b0010000 {
compatible = "syscon", "simple-mfd";
reg = <0xb0010000 0x3d>;
reg-io-width = <2>;
wdt@e {
compatible = "technologic,ts4800-wdt";
syscon = <&syscon 0xe>;
timeout-sec = <10>;
};
}

3
arch/arm/boot/dts/nxp/imx/Makefile
View File

@@ -376,6 +376,7 @@ dtb-$(CONFIG_SOC_IMX6UL) += \
imx6ul-tx6ul-0011.dtb \
imx6ul-tx6ul-mainboard.dtb \
imx6ul-var-som-concerto.dtb \
imx6ul-var-som-concerto-full.dtb \
imx6ull-14x14-evk.dtb \
imx6ull-colibri-aster.dtb \
imx6ull-colibri-emmc-aster.dtb \
@@ -414,6 +415,8 @@ dtb-$(CONFIG_SOC_IMX6UL) += \
imx6ull-tqma6ull2-mba6ulx.dtb \
imx6ull-tqma6ull2l-mba6ulx.dtb \
imx6ull-uti260b.dtb \
imx6ull-var-som-concerto.dtb \
imx6ull-var-som-concerto-full.dtb \
imx6ulz-14x14-evk.dtb \
imx6ulz-bsh-smm-m2.dtb
dtb-$(CONFIG_SOC_IMX7D) += \

1
arch/arm/boot/dts/nxp/imx/imx25.dtsi
View File

@@ -618,7 +618,6 @@ nfc: nand-controller@bb000000 {
compatible = "fsl,imx25-nand";
reg = <0xbb000000 0x2000>;
clocks = <&clks 50>;
clock-names = "";
interrupts = <33>;
status = "disabled";
};

1
arch/arm/boot/dts/nxp/imx/imx35.dtsi
View File

@@ -369,7 +369,6 @@ nfc: nand-controller@bb000000 {
compatible = "fsl,imx35-nand", "fsl,imx25-nand";
reg = <0xbb000000 0x2000>;
clocks = <&clks 29>;
clock-names = "";
interrupts = <33>;
status = "disabled";
};

1
arch/arm/boot/dts/nxp/imx/imx51-babbage.dts
View File

@@ -126,6 +126,7 @@ dvi_connector_in: endpoint {
dvi-encoder {
compatible = "ti,tfp410";
ti,deskew = <0>;
ports {
#address-cells = <1>;

2
arch/arm/boot/dts/nxp/imx/imx51-ts4800.dts
View File

@@ -155,7 +155,7 @@ syscon: syscon@10000 {
reg = <0x10000 0x3d>;
reg-io-width = <2>;
wdt {
watchdog {
compatible = "technologic,ts4800-wdt";
syscon = <&syscon 0xe>;
};

1
arch/arm/boot/dts/nxp/imx/imx53-cx9020.dts
View File

@@ -60,6 +60,7 @@ dvi_connector_in: endpoint {
dvi-converter {
compatible = "ti,tfp410";
ti,deskew = <0>;
ports {
#address-cells = <1>;

11
arch/arm/boot/dts/nxp/imx/imx53-m53menlo.dts
View File

@@ -84,6 +84,7 @@ panel {
pinctrl-0 = <&pinctrl_display_gpio>;
pinctrl-names = "default";
enable-gpios = <&gpio6 0 GPIO_ACTIVE_HIGH>;
power-supply = <&reg_3p2v>;
port {
panel_in: endpoint {
@@ -98,6 +99,13 @@ beeper {
gpios = <&gpio6 3 GPIO_ACTIVE_HIGH>;
};
reg_3v3: regulator-3v3 {
compatible = "regulator-fixed";
regulator-name = "3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
reg_usbh1_vbus: regulator-usbh1-vbus {
compatible = "regulator-fixed";
regulator-name = "vbus";
@@ -240,7 +248,7 @@ &i2c1 {
status = "okay";
touchscreen@38 {
compatible = "edt,edt-ft5x06";
compatible = "edt,edt-ft5206";
reg = <0x38>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_edt_ft5x06>;
@@ -259,6 +267,7 @@ eeprom@50 {
dac@60 {
compatible = "microchip,mcp4725";
reg = <0x60>;
vdd-supply = <&reg_3v3>;
};
};

2
arch/arm/boot/dts/nxp/imx/imx53-ppd.dts
View File

@@ -258,6 +258,7 @@ usbphy2: usbphy-2 {
clock-names = "main_clk";
clock-frequency = <24000000>;
clocks = <&clks IMX5_CLK_CKO2>;
#phy-cells = <0>;
assigned-clocks = <&clks IMX5_CLK_CKO2_SEL>, <&clks IMX5_CLK_OSC>;
assigned-clock-parents = <&clks IMX5_CLK_OSC>;
};
@@ -270,6 +271,7 @@ usbphy3: usbphy-3 {
clock-frequency = <24000000>;
clocks = <&clks IMX5_CLK_CKO2>;
#phy-cells = <0>;
assigned-clocks = <&clks IMX5_CLK_CKO2_SEL>, <&clks IMX5_CLK_OSC>;
assigned-clock-parents = <&clks IMX5_CLK_OSC>;
};

10
arch/arm/boot/dts/nxp/imx/imx53-qsb-common.dtsi
View File

@@ -91,6 +91,8 @@ panel_dpi: panel {
pinctrl-0 = <&pinctrl_display_power>;
backlight = <&backlight_parallel>;
enable-gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>;
dvdd-supply = <&reg_3p2v>;
avdd-supply = <&reg_5v>;
port {
panel_in: endpoint {
@@ -107,6 +109,14 @@ reg_3p2v: regulator-3p2v {
regulator-always-on;
};
reg_5v: regulator-5v {
compatible = "regulator-fixed";
regulator-name = "5V";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
regulator-always-on;
};
reg_usb_vbus: regulator-usb-vbus {
compatible = "regulator-fixed";
regulator-name = "usb_vbus";

1
arch/arm/boot/dts/nxp/imx/imx53-sk-imx53-atm0700d4.dtsi
View File

@@ -10,6 +10,7 @@
/ {
panel: panel-rgb {
compatible = "powertip,ph800480t013-idf02";
power-supply = <&reg_5v>;
port {
panel_rgb_in: endpoint {

7
arch/arm/boot/dts/nxp/imx/imx53-sk-imx53.dts
View File

@@ -29,6 +29,13 @@ memory@70000000 {
reg = <0x70000000 0x20000000>;
};
reg_5v: regulator-5v {
compatible = "regulator-fixed";
regulator-name = "5v";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
reg_usb1_vbus: regulator-usb-vbus {
compatible = "regulator-fixed";
regulator-name = "usb_vbus";

2
arch/arm/boot/dts/nxp/imx/imx53-smd.dts
View File

@@ -5,6 +5,7 @@
/dts-v1/;
#include <dt-bindings/input/input.h>
#include <dt-bindings/media/video-interfaces.h>
#include "imx53.dtsi"
/ {
@@ -314,6 +315,7 @@ camera: ov5642@3c {
port {
ov5642_to_ipu_csi0: endpoint {
remote-endpoint = <&ipu_csi0_from_parallel_sensor>;
bus-type = <MEDIA_BUS_TYPE_PARALLEL>;
bus-width = <8>;
hsync-active = <1>;
vsync-active = <1>;

2
arch/arm/boot/dts/nxp/imx/imx53-tx53-x03x.dts
View File

@@ -201,7 +201,7 @@ sgtl5000: codec@a {
};
polytouch: edt-ft5x06@38 {
compatible = "edt,edt-ft5x06";
compatible = "edt,edt-ft5206";
reg = <0x38>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_edt_ft5x06_1>;

2
arch/arm/boot/dts/nxp/imx/imx6dl-gw52xx.dts
View File

@@ -32,12 +32,10 @@ adv7180_to_ipu1_csi1_mux: endpoint {
};
&ipu1_csi1_from_ipu1_csi1_mux {
bus-width = <8>;
};
&ipu1_csi1_mux_from_parallel_sensor {
remote-endpoint = <&adv7180_to_ipu1_csi1_mux>;
bus-width = <8>;
};
&ipu1_csi1 {

2
arch/arm/boot/dts/nxp/imx/imx6dl-gw53xx.dts
View File

@@ -32,12 +32,10 @@ adv7180_to_ipu1_csi1_mux: endpoint {
};
&ipu1_csi1_from_ipu1_csi1_mux {
bus-width = <8>;
};
&ipu1_csi1_mux_from_parallel_sensor {
remote-endpoint = <&adv7180_to_ipu1_csi1_mux>;
bus-width = <8>;
};
&ipu1_csi1 {

2
arch/arm/boot/dts/nxp/imx/imx6dl-gw54xx.dts
View File

@@ -32,12 +32,10 @@ adv7180_to_ipu1_csi1_mux: endpoint {
};
&ipu1_csi1_from_ipu1_csi1_mux {
bus-width = <8>;
};
&ipu1_csi1_mux_from_parallel_sensor {
remote-endpoint = <&adv7180_to_ipu1_csi1_mux>;
bus-width = <8>;
};
&ipu1_csi1 {

2
arch/arm/boot/dts/nxp/imx/imx6q-display5.dtsi
View File

@@ -208,7 +208,7 @@ mdio {
#address-cells = <1>;
#size-cells = <0>;
ethernet_phy0: ethernet-phy@0 {
compatible = "marvell,88E1510";
compatible = "ethernet-phy-ieee802.3-c22";
device_type = "ethernet-phy";
/* Set LED0 control: */
/* On - Link, Blink - Activity, Off - No Link */

2
arch/arm/boot/dts/nxp/imx/imx6q-gw52xx.dts
View File

@@ -32,12 +32,10 @@ adv7180_to_ipu2_csi1_mux: endpoint {
};
&ipu2_csi1_from_ipu2_csi1_mux {
bus-width = <8>;
};
&ipu2_csi1_mux_from_parallel_sensor {
remote-endpoint = <&adv7180_to_ipu2_csi1_mux>;
bus-width = <8>;
};
&ipu2_csi1 {

2
arch/arm/boot/dts/nxp/imx/imx6q-gw53xx.dts
View File

@@ -32,12 +32,10 @@ adv7180_to_ipu2_csi1_mux: endpoint {
};
&ipu2_csi1_from_ipu2_csi1_mux {
bus-width = <8>;
};
&ipu2_csi1_mux_from_parallel_sensor {
remote-endpoint = <&adv7180_to_ipu2_csi1_mux>;
bus-width = <8>;
};
&ipu2_csi1 {

4
arch/arm/boot/dts/nxp/imx/imx6q-gw54xx.dts
View File

@@ -90,12 +90,10 @@ tda1997x_to_ipu1_csi0_mux: endpoint {
};
&ipu1_csi0_from_ipu1_csi0_mux {
bus-width = <16>;
};
&ipu1_csi0_mux_from_parallel_sensor {
remote-endpoint = <&tda1997x_to_ipu1_csi0_mux>;
bus-width = <16>;
};
&ipu1_csi0 {
@@ -104,12 +102,10 @@ &ipu1_csi0 {
};
&ipu2_csi1_from_ipu2_csi1_mux {
bus-width = <8>;
};
&ipu2_csi1_mux_from_parallel_sensor {
remote-endpoint = <&adv7180_to_ipu2_csi1_mux>;
bus-width = <8>;
};
&ipu2_csi1 {

1
arch/arm/boot/dts/nxp/imx/imx6q-novena.dts
View File

@@ -109,6 +109,7 @@ led-heartbeat {
panel: panel {
compatible = "innolux,n133hse-ea1";
backlight = <&backlight>;
power-supply = <&reg_lvds_lcd>;
};
reg_2p5v: regulator-2p5v {

18
arch/arm/boot/dts/nxp/imx/imx6q-utilite-pro.dts
View File

@@ -61,6 +61,7 @@ aliases {
encoder {
compatible = "ti,tfp410";
ti,deskew = <0>;
ports {
#address-cells = <1>;
@@ -323,19 +324,10 @@ &ipu1_di0_disp0 {
remote-endpoint = <&parallel_display_in>;
};
&pcie {
pcie@0,0 {
reg = <0x000000 0 0 0 0>;
device_type = "pci";
#address-cells = <3>;
#size-cells = <2>;
bus-range = <0x00 0xff>;
ranges;
/* non-removable i211 ethernet card */
eth1: ethernet@0,0 {
reg = <0x010000 0 0 0 0>;
};
&pcie_port0 {
/* non-removable i211 ethernet card */
eth1: ethernet@0,0 {
reg = <0x010000 0 0 0 0>;
};
};

2
arch/arm/boot/dts/nxp/imx/imx6q-var-dt6customboard.dts
View File

@@ -169,7 +169,7 @@ &i2c3 {
status = "okay";
touchscreen@38 {
compatible = "edt,edt-ft5x06";
compatible = "edt,edt-ft5206";
reg = <0x38>;
interrupt-parent = <&gpio1>;
interrupts = <4 IRQ_TYPE_EDGE_FALLING>;

2
arch/arm/boot/dts/nxp/imx/imx6qdl-gw51xx.dtsi
View File

@@ -384,12 +384,10 @@ adv7180_to_ipu1_csi0_mux: endpoint {
};
&ipu1_csi0_from_ipu1_csi0_mux {
bus-width = <8>;
};
&ipu1_csi0_mux_from_parallel_sensor {
remote-endpoint = <&adv7180_to_ipu1_csi0_mux>;
bus-width = <8>;
};
&ipu1_csi0 {

2
arch/arm/boot/dts/nxp/imx/imx6qdl-gw551x.dtsi
View File

@@ -440,12 +440,10 @@ tda1997x_to_ipu1_csi0_mux: endpoint {
};
&ipu1_csi0_from_ipu1_csi0_mux {
bus-width = <16>;
};
&ipu1_csi0_mux_from_parallel_sensor {
remote-endpoint = <&tda1997x_to_ipu1_csi0_mux>;
bus-width = <16>;
};
&ipu1_csi0 {

2
arch/arm/boot/dts/nxp/imx/imx6qdl-gw553x.dtsi
View File

@@ -397,12 +397,10 @@ adv7180_to_ipu1_csi0_mux: endpoint {
};
&ipu1_csi0_from_ipu1_csi0_mux {
bus-width = <8>;
};
&ipu1_csi0_mux_from_parallel_sensor {
remote-endpoint = <&adv7180_to_ipu1_csi0_mux>;
bus-width = <8>;
};
&ipu1_csi0 {

2
arch/arm/boot/dts/nxp/imx/imx6qdl-nit6xlite.dtsi
View File

@@ -256,7 +256,7 @@ touchscreen@4 {
};
touchscreen@38 {
compatible = "edt,edt-ft5x06";
compatible = "edt,edt-ft5206";
reg = <0x38>;
interrupt-parent = <&gpio1>;
interrupts = <9 IRQ_TYPE_EDGE_FALLING>;

2
arch/arm/boot/dts/nxp/imx/imx6qdl-nitrogen6_max.dtsi
View File

@@ -405,7 +405,7 @@ touchscreen@4 {
};
touchscreen@38 {
compatible = "edt,edt-ft5x06";
compatible = "edt,edt-ft5206";
reg = <0x38>;
interrupt-parent = <&gpio1>;
interrupts = <9 IRQ_TYPE_EDGE_FALLING>;

2
arch/arm/boot/dts/nxp/imx/imx6qdl-nitrogen6_som2.dtsi
View File

@@ -326,7 +326,7 @@ touchscreen@4 {
};
touchscreen@38 {
compatible = "edt,edt-ft5x06";
compatible = "edt,edt-ft5206";
reg = <0x38>;
interrupt-parent = <&gpio1>;
interrupts = <9 IRQ_TYPE_EDGE_FALLING>;

2
arch/arm/boot/dts/nxp/imx/imx6qdl-nitrogen6x.dtsi
View File

@@ -333,7 +333,7 @@ touchscreen@4 {
};
touchscreen@38 {
compatible = "edt,edt-ft5x06";
compatible = "edt,edt-ft5206";
reg = <0x38>;
interrupt-parent = <&gpio1>;
interrupts = <9 IRQ_TYPE_EDGE_FALLING>;

2
arch/arm/boot/dts/nxp/imx/imx6qdl-pico.dtsi
View File

@@ -217,7 +217,7 @@ &i2c2 {
status = "okay";
touchscreen@38 {
compatible = "edt,edt-ft5x06";
compatible = "edt,edt-ft5206";
reg = <0x38>;
interrupt-parent = <&gpio5>;
interrupts = <31 IRQ_TYPE_EDGE_FALLING>;

2
arch/arm/boot/dts/nxp/imx/imx6qdl-sabreauto.dtsi
View File

@@ -245,12 +245,10 @@ accelerometer@1c {
};
&ipu1_csi0_from_ipu1_csi0_mux {
bus-width = <8>;
};
&ipu1_csi0_mux_from_parallel_sensor {
remote-endpoint = <&adv7180_to_ipu1_csi0_mux>;
bus-width = <8>;
};
&ipu1_csi0 {

5
arch/arm/boot/dts/nxp/imx/imx6qdl-sabresd.dtsi
View File

@@ -754,11 +754,16 @@ lvds0_out: endpoint {
&pcie {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie>;
/* This property is deprecated, use reset-gpios from the Root Port node. */
reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>;
vpcie-supply = <&reg_pcie>;
status = "okay";
};
&pcie_port0 {
reset-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>;
};
&pwm1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm1>;

5
arch/arm/boot/dts/nxp/imx/imx6qdl-tx6.dtsi
View File

@@ -148,8 +148,7 @@ reg_usbotg_vbus: regulator-usbotg-vbus {
};
sound {
compatible = "karo,imx6qdl-tx6-sgtl5000",
"simple-audio-card";
compatible = "simple-audio-card";
simple-audio-card,name = "imx6qdl-tx6-sgtl5000-audio";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audmux>;
@@ -293,7 +292,7 @@ sgtl5000: sgtl5000@a {
};
polytouch: edt-ft5x06@38 {
compatible = "edt,edt-ft5x06";
compatible = "edt,edt-ft5206";
reg = <0x38>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_edt_ft5x06>;

11
arch/arm/boot/dts/nxp/imx/imx6qdl.dtsi
View File

@@ -302,6 +302,17 @@ pcie: pcie@1ffc000 {
<&clks IMX6QDL_CLK_PCIE_REF_125M>;
clock-names = "pcie", "pcie_bus", "pcie_phy";
status = "disabled";
pcie_port0: pcie@0 {
compatible = "pciclass,0604";
device_type = "pci";
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
};
};
aips1: bus@2000000 { /* AIPS1 */

5
arch/arm/boot/dts/nxp/imx/imx6qp-sabreauto.dts
View File

@@ -45,10 +45,15 @@ MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
};
&pcie {
/* This property is deprecated, use reset-gpios from the Root Port node. */
reset-gpio = <&max7310_c 5 GPIO_ACTIVE_LOW>;
status = "okay";
};
&pcie_port0 {
reset-gpios = <&max7310_c 5 GPIO_ACTIVE_LOW>;
};
&sata {
status = "okay";
};

5
arch/arm/boot/dts/nxp/imx/imx6sx-sdb.dtsi
View File

@@ -282,11 +282,16 @@ codec: wm8962@1a {
&pcie {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pcie>;
/* This property is deprecated, use reset-gpios from the Root Port node. */
reset-gpio = <&gpio2 0 GPIO_ACTIVE_LOW>;
vpcie-supply = <&reg_pcie_gpio>;
status = "okay";
};
&pcie_port0 {
reset-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
};
&lcdif1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lcd>;

11
arch/arm/boot/dts/nxp/imx/imx6sx.dtsi
View File

@@ -1470,6 +1470,17 @@ pcie: pcie@8ffc000 {
power-domains = <&pd_disp>, <&pd_pci>;
power-domain-names = "pcie", "pcie_phy";
status = "disabled";
pcie_port0: pcie@0 {
compatible = "pciclass,0604";
device_type = "pci";
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
};
};
};
};

1
arch/arm/boot/dts/nxp/imx/imx6ul-14x14-evk.dtsi
View File

@@ -217,6 +217,7 @@ camera@3c {
port {
ov5640_to_parallel: endpoint {
remote-endpoint = <&parallel_from_ov5640>;
bus-type = <MEDIA_BUS_TYPE_PARALLEL>;
bus-width = <8>;
data-shift = <2>; /* lines 9:2 are used */
hsync-active = <0>;

2
arch/arm/boot/dts/nxp/imx/imx6ul-pico-hobbit.dts
View File

@@ -62,7 +62,7 @@ &i2c3 {
status = "okay";
polytouch: touchscreen@38 {
compatible = "edt,edt-ft5x06";
compatible = "edt,edt-ft5206";
reg = <0x38>;
interrupt-parent = <&gpio1>;
interrupts = <29 IRQ_TYPE_EDGE_FALLING>;

2
arch/arm/boot/dts/nxp/imx/imx6ul-pico-pi.dts
View File

@@ -65,7 +65,7 @@ &i2c3 {
status = "okay";
polytouch: touchscreen@38 {
compatible = "edt,edt-ft5x06";
compatible = "edt,edt-ft5206";
reg = <0x38>;
interrupt-parent = <&gpio1>;
interrupts = <29 IRQ_TYPE_EDGE_FALLING>;

2
arch/arm/boot/dts/nxp/imx/imx6ul-tx6ul.dtsi
View File

@@ -317,7 +317,7 @@ sgtl5000: codec@a {
};
polytouch: polytouch@38 {
compatible = "edt,edt-ft5x06";
compatible = "edt,edt-ft5206";
reg = <0x38>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_edt_ft5x06>;

30
arch/arm/boot/dts/nxp/imx/imx6ul-var-som-audio.dtsi Normal file
View File

@@ -0,0 +1,30 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Audio support for Variscite VAR-SOM-6UL module.
*
* Copyright 2019-2024 Variscite Ltd.
* Copyright 2026 Dimonoff
*/
&iomuxc {
pinctrl_sai2: sai2grp {
fsl,pins = <
MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088
MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088
MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x11088
MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x11088
MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x17088
>;
};
};
&sai2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai2>;
assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>,
<&clks IMX6UL_CLK_SAI2>;
assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
assigned-clock-rates = <0>, <12288000>;
fsl,sai-mclk-direction-output;
status = "okay";
};

187
arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi Normal file
View File

@@ -0,0 +1,187 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Support for the common parts shared by all the different CPU options on
* Variscite VAR-SOM-6UL Module
*
* Copyright 2019 Variscite Ltd.
* Copyright 2025 Bootlin
*/
#include <dt-bindings/clock/imx6ul-clock.h>
#include <dt-bindings/gpio/gpio.h>
/ {
model = "Variscite VAR-SOM-6UL module";
compatible = "variscite,var-som-imx6ul", "fsl,imx6ul";
memory@80000000 {
device_type = "memory";
reg = <0x80000000 0x20000000>;
};
reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";
regulator-name = "3P3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
reg_gpio_dvfs: reg-gpio-dvfs {
compatible = "regulator-gpio";
regulator-min-microvolt = <1300000>;
regulator-max-microvolt = <1400000>;
regulator-name = "gpio_dvfs";
regulator-type = "voltage";
gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>;
states = <1300000 0x1
1400000 0x0>;
};
};
&clks {
assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
assigned-clock-rates = <786432000>;
};
&iomuxc {
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX6UL_PAD_CSI_PIXCLK__I2C1_SCL 0x4001b8b0
MX6UL_PAD_CSI_MCLK__I2C1_SDA 0x4001b8b0
>;
};
pinctrl_tsc: tscgrp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0
MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0
MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0
MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1
MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1
MX6UL_PAD_UART2_CTS_B__UART2_DCE_CTS 0x1b0b1
MX6UL_PAD_UART2_RTS_B__UART2_DCE_RTS 0x1b0b1
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x17059
MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
>;
};
pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
fsl,pins = <
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9
MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
>;
};
pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
fsl,pins = <
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9
MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9
MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069
MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059
MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059
MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059
MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059
MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059
>;
};
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
fsl,pins = <
MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100b9
MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170b9
MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9
MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9
MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9
MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170b9
MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170b9
MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170b9
MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170b9
MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170b9
>;
};
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
fsl,pins = <
MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9
MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9
MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9
MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9
MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9
MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9
MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170f9
MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170f9
MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170f9
MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170f9
>;
};
};
&pxp {
status = "okay";
};
&snvs_poweroff {
status = "okay";
};
&tsc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_tsc>;
xnur-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
measure-delay-time = <0xffff>;
pre-charge-time = <0xfff>;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
uart-has-rtscts;
status = "okay";
};
&usdhc2 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
bus-width = <8>;
no-1-8-v;
non-removable;
keep-power-in-suspend;
wakeup-source;
status = "okay";
};

215
arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-common.dtsi Normal file
View File

@@ -0,0 +1,215 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Support for Variscite Concerto Carrier board with the VAR-SOM-6UL
* Variscite SoM mounted on it (all CPU variants)
*
* Copyright 2019 Variscite Ltd.
* Copyright 2025 Bootlin
*/
#include <dt-bindings/leds/common.h>
/ {
chosen {
stdout-path = &uart1;
};
gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_key_back>, <&pinctrl_gpio_key_wakeup>;
key-back {
gpios = <&gpio4 14 GPIO_ACTIVE_LOW>;
linux,code = <KEY_BACK>;
};
key-wakeup {
gpios = <&gpio5 8 GPIO_ACTIVE_LOW>;
linux,code = <KEY_WAKEUP>;
wakeup-source;
};
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_leds>;
led-0 {
function = LED_FUNCTION_STATUS;
color = <LED_COLOR_ID_GREEN>;
label = "gpled2";
gpios = <&gpio1 25 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
};
lvds_panel: lvds-panel {
compatible = "sgd,gktw70sdae4se", "panel-lvds";
data-mapping = "jeida-18";
width-mm = <153>;
height-mm = <86>;
panel-timing {
clock-frequency = <35000000>;
hactive = <800>;
vactive = <480>;
hback-porch = <40>;
hfront-porch = <40>;
vback-porch = <29>;
vfront-porch = <13>;
hsync-len = <48>;
vsync-len = <3>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <0>;
};
};
};
&can1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan1>;
status = "okay";
};
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
rtc@68 {
/*
* To actually use this interrupt
* connect pins J14.8 & J14.10 on the Concerto-Board.
*/
compatible = "dallas,ds1337";
reg = <0x68>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rtc>;
interrupt-parent = <&gpio1>;
interrupts = <10 IRQ_TYPE_EDGE_FALLING>;
};
};
&iomuxc {
pinctrl_flexcan1: flexcan1grp {
fsl,pins = <
MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020
MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020
>;
};
pinctrl_gpio_key_back: gpio-key-backgrp {
fsl,pins = <
MX6UL_PAD_NAND_CE1_B__GPIO4_IO14 0x17059
>;
};
pinctrl_gpio_key_wakeup: gpio-keys-wakeupgrp {
fsl,pins = <
MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x17059
>;
};
pinctrl_gpio_leds: gpio-ledsgrp {
fsl,pins = <
MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25 0x1b0b0 /* GPLED2 */
>;
};
pinctrl_rtc: rtcgrp {
fsl,pins = <
MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0x1b0b0 /* RTC alarm IRQ */
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
>;
};
pinctrl_uart5: uart5grp {
fsl,pins = <
MX6UL_PAD_CSI_DATA00__UART5_DCE_TX 0x1b0b1
MX6UL_PAD_CSI_DATA01__UART5_DCE_RX 0x1b0b1
MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS 0x1b0b1
MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS 0x1b0b1
>;
};
pinctrl_usb_otg1_id: usbotg1idgrp {
fsl,pins = <
MX6UL_PAD_UART3_TX_DATA__ANATOP_OTG1_ID 0x17059
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO01__WDOG1_WDOG_B 0x78b0
>;
};
};
&snvs_pwrkey {
status = "disabled";
};
&snvs_rtc {
status = "disabled";
};
&tsc {
/*
* Conflics with wdog1 ext-reset-output & SD CD pins,
* so we keep it disabled by default.
*/
status = "disabled";
};
/* Console UART */
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
/* ttymxc4 UART */
&uart5 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart5>;
uart-has-rtscts;
status = "okay";
};
&usbotg1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb_otg1_id>;
dr_mode = "otg";
disable-over-current;
srp-disable;
hnp-disable;
adp-disable;
status = "okay";
};
&usbotg2 {
dr_mode = "host";
disable-over-current;
status = "okay";
};
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
/*
* To actually use ext-reset-output
* connect pins J17.3 & J17.8 on the Concerto-Board
*/
fsl,ext-reset-output;
};

22
arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-full.dts Normal file
View File

@@ -0,0 +1,22 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Support for Variscite MX6 Concerto Carrier board with the VAR-SOM-6UL
* Variscite SoM mounted on it (6UL CPU variant).
*
* Copyright 2026 Dimonoff
*/
/dts-v1/;
#include "imx6ul-var-som.dtsi"
#include "imx6ul-var-som-concerto-common.dtsi"
#include "imx6ul-var-som-wifi.dtsi"
#include "imx6ul-var-som-enet2.dtsi"
#include "imx6ul-var-som-enet1.dtsi"
#include "imx6ul-var-som-audio.dtsi"
#include "imx6ul-var-som-lvds-panel.dtsi"
/ {
model = "Variscite VAR-SOM-6UL Concerto Board (6UL CPU)";
compatible = "variscite,mx6ulconcerto", "variscite,var-som-imx6ul", "fsl,imx6ul";
};

318
arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts
View File

@@ -1,320 +1,22 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Support for Variscite MX6 Concerto Carrier board with the VAR-SOM-MX6UL
* Variscite SoM mounted on it
* Support for Variscite Concerto Carrier board with the VAR-SOM-6UL
* Variscite SoM mounted on it (6UL CPU variant)
*
* Copyright 2019 Variscite Ltd.
* Copyright 2025 Bootlin
*/
/dts-v1/;
#include "imx6ul-var-som.dtsi"
#include <dt-bindings/leds/common.h>
#include "imx6ul-var-som-concerto-common.dtsi"
#include "imx6ul-var-som-sd.dtsi"
#include "imx6ul-var-som-enet2.dtsi"
#include "imx6ul-var-som-audio.dtsi"
#include "imx6ul-var-som-lvds-panel.dtsi"
/ {
model = "Variscite VAR-SOM-MX6UL Concerto Board";
model = "Variscite VAR-SOM-6UL Concerto Board (6UL CPU)";
compatible = "variscite,mx6ulconcerto", "variscite,var-som-imx6ul", "fsl,imx6ul";
chosen {
stdout-path = &uart1;
};
gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_key_back>, <&pinctrl_gpio_key_wakeup>;
key-back {
gpios = <&gpio4 14 GPIO_ACTIVE_LOW>;
linux,code = <KEY_BACK>;
};
key-wakeup {
gpios = <&gpio5 8 GPIO_ACTIVE_LOW>;
linux,code = <KEY_WAKEUP>;
wakeup-source;
};
};
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_leds>;
led-0 {
function = LED_FUNCTION_STATUS;
color = <LED_COLOR_ID_GREEN>;
label = "gpled2";
gpios = <&gpio1 25 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
};
};
&can1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan1>;
status = "okay";
};
&fec1 {
status = "disabled";
};
&fec2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet2>, <&pinctrl_enet2_gpio>, <&pinctrl_enet2_mdio>;
phy-mode = "rmii";
phy-handle = <&ethphy1>;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy1: ethernet-phy@3 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <3>;
clocks = <&rmii_ref_clk>;
clock-names = "rmii-ref";
reset-gpios = <&gpio5 5 GPIO_ACTIVE_LOW>;
reset-assert-us = <100000>;
micrel,led-mode = <0>;
micrel,rmii-reference-clock-select-25-mhz = <1>;
};
};
};
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
rtc@68 {
/*
* To actually use this interrupt
* connect pins J14.8 & J14.10 on the Concerto-Board.
*/
compatible = "dallas,ds1337";
reg = <0x68>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rtc>;
interrupt-parent = <&gpio1>;
interrupts = <10 IRQ_TYPE_EDGE_FALLING>;
};
};
&iomuxc {
pinctrl_enet2: enet2grp {
fsl,pins = <
MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0
MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0
MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031
>;
};
pinctrl_enet2_gpio: enet2-gpiogrp {
fsl,pins = <
MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x1b0b0 /* fec2 reset */
>;
};
pinctrl_enet2_mdio: enet2-mdiogrp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0
MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0
>;
};
pinctrl_flexcan1: flexcan1grp {
fsl,pins = <
MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020
MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020
>;
};
pinctrl_gpio_key_back: gpio-key-backgrp {
fsl,pins = <
MX6UL_PAD_NAND_CE1_B__GPIO4_IO14 0x17059
>;
};
pinctrl_gpio_leds: gpio-ledsgrp {
fsl,pins = <
MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25 0x1b0b0 /* GPLED2 */
>;
};
pinctrl_gpio_key_wakeup: gpio-keys-wakeupgrp {
fsl,pins = <
MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x17059
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX6UL_PAD_CSI_PIXCLK__I2C1_SCL 0x4001b8b0
MX6UL_PAD_CSI_MCLK__I2C1_SDA 0x4001b8b0
>;
};
pinctrl_pwm4: pwm4grp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO05__PWM4_OUT 0x110b0
>;
};
pinctrl_rtc: rtcgrp {
fsl,pins = <
MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0x1b0b0 /* RTC alarm IRQ */
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
>;
};
pinctrl_uart5: uart5grp {
fsl,pins = <
MX6UL_PAD_CSI_DATA00__UART5_DCE_TX 0x1b0b1
MX6UL_PAD_CSI_DATA01__UART5_DCE_RX 0x1b0b1
MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS 0x1b0b1
MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS 0x1b0b1
>;
};
pinctrl_usb_otg1_id: usbotg1idgrp {
fsl,pins = <
MX6UL_PAD_UART3_TX_DATA__ANATOP_OTG1_ID 0x17059
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x17059
MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
>;
};
pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
fsl,pins = <
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9
MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
>;
};
pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
fsl,pins = <
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9
MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9
MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
>;
};
pinctrl_usdhc1_gpio: usdhc1-gpiogrp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO00__GPIO1_IO00 0x1b0b1 /* CD */
>;
};
pinctrl_wdog: wdoggrp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO01__WDOG1_WDOG_B 0x78b0
>;
};
};
&pwm4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm4>;
status = "okay";
};
&snvs_pwrkey {
status = "disabled";
};
&snvs_rtc {
status = "disabled";
};
&tsc {
/*
* Conflics with wdog1 ext-reset-output & SD CD pins,
* so we keep it disabled by default.
*/
status = "disabled";
};
/* Console UART */
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
/* ttymxc4 UART */
&uart5 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart5>;
uart-has-rtscts;
status = "okay";
};
&usbotg1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb_otg1_id>;
dr_mode = "otg";
disable-over-current;
srp-disable;
hnp-disable;
adp-disable;
status = "okay";
};
&usbotg2 {
dr_mode = "host";
disable-over-current;
status = "okay";
};
&usdhc1 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>;
cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
no-1-8-v;
keep-power-in-suspend;
wakeup-source;
status = "okay";
};
&wdog1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_wdog>;
/*
* To actually use ext-reset-output
* connect pins J17.3 & J17.8 on the Concerto-Board
*/
fsl,ext-reset-output;
};

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arch/arm/boot/dts/nxp/imx/imx6ul-var-som-enet1.dtsi Normal file
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// SPDX-License-Identifier: GPL-2.0+
/*
* Ethernet ENET1 support for Variscite VAR-SOM-6UL module with
* the EC configuration option ((ethernet PHY assembled on SOM).
*
* Copyright 2019-2024 Variscite Ltd.
* Copyright 2026 Dimonoff
*/
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet1>, <&pinctrl_enet1_gpio>;
phy-mode = "rmii";
phy-handle = <&ethphy0>;
status = "okay";
};
&iomuxc {
pinctrl_enet1: enet1grp {
fsl,pins = <
MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031
>;
};
};
&mdio_enet2 {
ethphy0: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
clocks = <&rmii_ref_clk>;
clock-names = "rmii-ref";
reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
reset-assert-us = <100000>;
micrel,led-mode = <1>;
micrel,rmii-reference-clock-select-25-mhz;
};
};

79
arch/arm/boot/dts/nxp/imx/imx6ul-var-som-enet2.dtsi Normal file
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// SPDX-License-Identifier: GPL-2.0+
/*
* Ethernet ENET2 support for Variscite VAR-SOM-6UL module.
*
* Copyright 2019-2024 Variscite Ltd.
* Copyright 2026 Dimonoff
*/
/ {
rmii_ref_clk: rmii-ref-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
clock-output-names = "rmii-ref";
};
};
&fec2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet2>, <&pinctrl_enet2_gpio>, <&pinctrl_enet2_mdio>;
phy-mode = "rmii";
phy-handle = <&ethphy1>;
status = "okay";
mdio_enet2: mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
clocks = <&rmii_ref_clk>;
clock-names = "rmii-ref";
reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
reset-assert-us = <100000>;
micrel,led-mode = <1>;
micrel,rmii-reference-clock-select-25-mhz;
};
ethphy1: ethernet-phy@3 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <3>;
clocks = <&rmii_ref_clk>;
clock-names = "rmii-ref";
reset-gpios = <&gpio5 5 GPIO_ACTIVE_LOW>;
reset-assert-us = <100000>;
micrel,led-mode = <0>;
micrel,rmii-reference-clock-select-25-mhz;
};
};
};
&iomuxc {
pinctrl_enet2: enet2grp {
fsl,pins = <
MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0
MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0
MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031
>;
};
pinctrl_enet2_gpio: enet2-gpiogrp {
fsl,pins = <
MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x1b0b0 /* fec2 reset */
>;
};
pinctrl_enet2_mdio: enet2-mdiogrp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0
MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0
>;
};
};

112
arch/arm/boot/dts/nxp/imx/imx6ul-var-som-lvds-panel.dtsi Normal file
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// SPDX-License-Identifier: GPL-2.0+
/*
* LVDS panel support for Variscite VAR-SOM-6UL module.
*
* Copyright 2019-2024 Variscite Ltd.
* Copyright 2026 Dimonoff
*/
/ {
lcd_backlight: lcd-backlight {
compatible = "pwm-backlight";
pwms = <&pwm4 0 2000000 0>;
pwm-names = "LCD_BKLT_PWM";
brightness-levels = <0 4 8 16 32 64 128 255>;
default-brightness-level = <6>;
status = "okay";
};
lvds_encoder: lvds-encoder {
compatible = "ti,sn75lvds93", "lvds-encoder";
power-supply = <&reg_3p3v>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
lvds_enc_in: endpoint {
remote-endpoint = <&lcdif_out>;
};
};
port@1 {
reg = <1>;
lvds_enc_out: endpoint {
remote-endpoint = <&lvds_panel_in>;
};
};
};
};
};
&iomuxc {
pinctrl_lcdif_ctrl: lcdif-ctrl-grp {
fsl,pins = <
MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79
MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79
>;
};
pinctrl_lcdif_dat: lcdif-dat-grp {
fsl,pins = <
MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79
MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79
MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79
MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79
MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79
MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79
MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79
MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79
MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79
MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79
MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79
MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79
MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79
MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79
MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79
MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79
MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79
MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79
>;
};
pinctrl_pwm4: pwm4-grp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO05__PWM4_OUT 0x110b0 /* LCD BACKLIGHT */
>;
};
};
&lcdif {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lcdif_dat
&pinctrl_lcdif_ctrl>;
status = "okay";
port {
lcdif_out: endpoint {
remote-endpoint = <&lvds_enc_in>;
};
};
};
&lvds_panel {
status = "okay";
port {
lvds_panel_in: endpoint {
remote-endpoint = <&lvds_enc_out>;
};
};
};
/* PWM LCD */
&pwm4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm4>;
status = "okay";
};

27
arch/arm/boot/dts/nxp/imx/imx6ul-var-som-sd.dtsi Normal file
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// SPDX-License-Identifier: GPL-2.0+
/*
* Support optional SD card interface on Variscite VAR-SOM-6UL module.
*
* Copyright 2019-2024 Variscite Ltd.
* Copyright 2026 Dimonoff
*/
&iomuxc {
pinctrl_usdhc1_gpio: usdhc1-gpiogrp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO00__GPIO1_IO00 0x1b0b1 /* CD */
>;
};
};
&usdhc1 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>;
cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
no-1-8-v;
keep-power-in-suspend;
wakeup-source;
status = "okay";
};

75
arch/arm/boot/dts/nxp/imx/imx6ul-var-som-wifi.dtsi Normal file
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@@ -0,0 +1,75 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Support optional Wifi/Bluetooth on Variscite VAR-SOM-6UL module.
*
* Copyright 2019-2024 Variscite Ltd.
* Copyright 2026 Dimonoff
*/
/ {
reg_sd1_vmmc: regulator_sd1_vmmc {
compatible = "regulator-fixed";
regulator-name = "VMMC1";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>;
enable-active-high;
startup-delay-us = <10000>;
};
usdhc1_pwrseq: usdhc1-pwrseq {
compatible = "mmc-pwrseq-simple";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_brcm_wifi>;
reset-gpios = <&gpio5 6 GPIO_ACTIVE_LOW>;
};
};
&iomuxc {
pinctrl_32k_clk: 32kclkgrp {
/*
* For TP option, an additional oscillator is assembled on the
* SOM to provide 32 kHz to the WiFi module. Without TP option,
* this pin is configured to provide the 32 KHz clock to the
* WiFi module.
*/
fsl,pins = <
MX6UL_PAD_GPIO1_IO03__OSC32K_32K_OUT 0x03029
>;
};
};
&tsc {
status = "disabled";
};
/* Bluetooth UART */
&uart2 {
bluetooth {
compatible = "brcm,bcm43438-bt";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_brcm_bt>;
shutdown-gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>;
vbat-supply = <&reg_3p3v>;
vddio-supply = <&reg_3p3v>;
};
};
&usdhc1 {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_32k_clk>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_32k_clk>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_32k_clk>;
no-1-8-v;
non-removable;
mmc-pwrseq = <&usdhc1_pwrseq>;
vmmc-supply = <&reg_sd1_vmmc>;
status = "okay";
brcmf: wifi@1 {
compatible = "brcm,bcm4329-fmac"; /* LWB option: Sterling LWB5 */
reg = <1>;
};
};

219
arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi
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@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Support for Variscite VAR-SOM-MX6UL Module
* Support for Variscite VAR-SOM-6UL Module
*
* Copyright 2019 Variscite Ltd.
* Copyright 2025 Bootlin
@@ -9,84 +9,24 @@
/dts-v1/;
#include "imx6ul.dtsi"
#include <dt-bindings/clock/imx6ul-clock.h>
#include <dt-bindings/gpio/gpio.h>
#include "imx6ul-var-som-common.dtsi"
/ {
model = "Variscite VAR-SOM-MX6UL module";
model = "Variscite VAR-SOM-6UL module";
compatible = "variscite,var-som-imx6ul", "fsl,imx6ul";
memory@80000000 {
device_type = "memory";
reg = <0x80000000 0x20000000>;
};
reg_gpio_dvfs: reg-gpio-dvfs {
compatible = "regulator-gpio";
regulator-min-microvolt = <1300000>;
regulator-max-microvolt = <1400000>;
regulator-name = "gpio_dvfs";
regulator-type = "voltage";
gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>;
states = <1300000 0x1
1400000 0x0>;
};
rmii_ref_clk: rmii-ref-clk {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
clock-output-names = "rmii-ref";
};
};
&clks {
assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
assigned-clock-rates = <786432000>;
};
&cpu0 {
dc-supply = <&reg_gpio_dvfs>;
};
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet1>, <&pinctrl_enet1_gpio>, <&pinctrl_enet1_mdio>;
phy-mode = "rmii";
phy-handle = <&ethphy0>;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
clocks = <&rmii_ref_clk>;
clock-names = "rmii-ref";
reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
reset-assert-us = <100000>;
micrel,led-mode = <1>;
micrel,rmii-reference-clock-select-25-mhz = <1>;
};
};
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
pinctrl_enet1: enet1grp {
pinctrl_brcm_bt: brcm-bt-grp {
fsl,pins = <
MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031
MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x1b0b0 /* BT_REG_ON (BT_EN) */
>;
};
pinctrl_brcm_wifi: brcm-wifi-grp {
fsl,pins = <
MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1b0b0 /* WL_PWR (WIFI_PWR 5G) */
MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x1b0b0 /* WL_REG_ON (WIFI_EN) */
>;
};
@@ -95,139 +35,4 @@ pinctrl_enet1_gpio: enet1-gpiogrp {
MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b0b0 /* fec1 reset */
>;
};
pinctrl_enet1_mdio: enet1-mdiogrp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0
MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0
>;
};
pinctrl_hog: hoggrp {
fsl,pins = <
MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x1b0b0 /* BT Enable */
MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x03029 /* WLAN Enable */
>;
};
pinctrl_sai2: sai2grp {
fsl,pins = <
MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088
MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088
MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x11088
MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x11088
MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x17088
>;
};
pinctrl_tsc: tscgrp {
fsl,pins = <
MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0
MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0
MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0
MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1
MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1
MX6UL_PAD_UART2_CTS_B__UART2_DCE_CTS 0x1b0b1
MX6UL_PAD_UART2_RTS_B__UART2_DCE_RTS 0x1b0b1
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069
MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059
MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059
MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059
MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059
MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059
>;
};
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
fsl,pins = <
MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100b9
MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170b9
MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9
MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9
MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9
MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170b9
MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170b9
MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170b9
MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170b9
MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170b9
>;
};
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
fsl,pins = <
MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9
MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9
MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9
MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9
MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9
MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9
MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170f9
MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170f9
MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170f9
MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170f9
>;
};
};
&pxp {
status = "okay";
};
&sai2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai2>;
assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>,
<&clks IMX6UL_CLK_SAI2>;
assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
assigned-clock-rates = <0>, <12288000>;
fsl,sai-mclk-direction-output;
status = "okay";
};
&snvs_poweroff {
status = "okay";
};
&tsc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_tsc>;
xnur-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
measure-delay-time = <0xffff>;
pre-charge-time = <0xfff>;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
uart-has-rtscts;
status = "okay";
};
&usdhc2 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
bus-width = <8>;
no-1-8-v;
non-removable;
keep-power-in-suspend;
wakeup-source;
status = "okay";
};

1
arch/arm/boot/dts/nxp/imx/imx6ul.dtsi
View File

@@ -951,6 +951,7 @@ adc1: adc@2198000 {
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6UL_CLK_ADC1>;
clock-names = "adc";
#io-channel-cells = <1>;
fsl,adck-max-frequency = <30000000>, <40000000>,
<20000000>;
status = "disabled";

22
arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto-full.dts Normal file
View File

@@ -0,0 +1,22 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Support for Variscite MX6 Concerto Carrier board with the VAR-SOM-6UL
* Variscite SoM mounted on it (6ULL CPU variant).
*
* Copyright 2026 Dimonoff
*/
/dts-v1/;
#include "imx6ull-var-som.dtsi"
#include "imx6ul-var-som-concerto-common.dtsi"
#include "imx6ul-var-som-wifi.dtsi"
#include "imx6ul-var-som-enet2.dtsi"
#include "imx6ul-var-som-enet1.dtsi"
#include "imx6ul-var-som-audio.dtsi"
#include "imx6ul-var-som-lvds-panel.dtsi"
/ {
model = "Variscite VAR-SOM-6UL Concerto Board (6ULL CPU)";
compatible = "variscite,mx6ullconcerto", "variscite,var-som-imx6ull", "fsl,imx6ull";
};

21
arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto.dts Normal file
View File

@@ -0,0 +1,21 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Support for Variscite Concerto Carrier board with the VAR-SOM-6UL
* Variscite SoM mounted on it (6ULL CPU variant)
*
* Copyright 2026 Dimonoff
*/
/dts-v1/;
#include "imx6ull-var-som.dtsi"
#include "imx6ul-var-som-concerto-common.dtsi"
#include "imx6ul-var-som-sd.dtsi"
#include "imx6ul-var-som-enet2.dtsi"
#include "imx6ul-var-som-audio.dtsi"
#include "imx6ul-var-som-lvds-panel.dtsi"
/ {
model = "Variscite VAR-SOM-6UL Concerto Board (6ULL CPU)";
compatible = "variscite,mx6ullconcerto", "variscite,var-som-imx6ull", "fsl,imx6ull";
};

36
arch/arm/boot/dts/nxp/imx/imx6ull-var-som.dtsi Normal file
View File

@@ -0,0 +1,36 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Support for Variscite VAR-SOM-6UL module with imx6ull CPU
*
* Copyright 2019-2024 Variscite Ltd.
* Copyright 2026 Dimonoff
*/
#include "imx6ull.dtsi"
#include "imx6ul-var-som-common.dtsi"
/ {
model = "Variscite VAR-SOM-6UL module";
compatible = "variscite,var-som-imx6ull", "fsl,imx6ull";
};
&iomuxc {
pinctrl_brcm_bt: brcm-bt-grp {
fsl,pins = <
MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x1b0b0 /* BT_REG_ON (BT_EN) */
>;
};
pinctrl_brcm_wifi: brcm-wifi-grp {
fsl,pins = <
MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1b0b0 /* WL_PWR (WIFI_PWR 5G) */
MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x1b0b0 /* WL_REG_ON (WIFI_EN) */
>;
};
pinctrl_enet1_gpio: enet1-gpiogrp {
fsl,pins = <
MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b0b0 /* fec1 reset */
>;
};
};

10
arch/arm/boot/dts/nxp/imx/imx7-tqma7.dtsi
View File

@@ -151,6 +151,16 @@ m24c64: eeprom@50 {
reg = <0x50>;
pagesize = <32>;
vcc-supply = <&vgen4_reg>;
nvmem-layout {
compatible = "fixed-layout";
#address-cells = <1>;
#size-cells = <1>;
module_info: module-info@20 {
reg = <0x20 0x60>;
};
};
};
at24c02: eeprom@56 {

2
arch/arm/boot/dts/nxp/imx/imx7d-pico-dwarf.dts
View File

@@ -70,7 +70,7 @@ pca9554: io-expander@25 {
};
touchscreen@38 {
compatible = "edt,edt-ft5x06";
compatible = "edt,edt-ft5206";
reg = <0x38>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_touchscreen>;

70
arch/arm/boot/dts/nxp/imx/imx7d-pico-pi.dts
View File

@@ -19,6 +19,13 @@ led {
};
};
reg_1p5v: regulator-1p5v {
compatible = "regulator-fixed";
regulator-name = "1P5V";
regulator-min-microvolt = <1500000>;
regulator-max-microvolt = <1500000>;
};
sound {
compatible = "simple-audio-card";
simple-audio-card,name = "imx7-sgtl5000";
@@ -49,7 +56,7 @@ sgtl5000: codec@a {
&i2c4 {
polytouch: touchscreen@38 {
compatible = "edt,edt-ft5x06";
compatible = "edt,edt-ft5206";
reg = <0x38>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_touchscreen>;
@@ -59,6 +66,33 @@ polytouch: touchscreen@38 {
touchscreen-size-x = <800>;
touchscreen-size-y = <480>;
};
camera@3c {
compatible = "ovti,ov5645";
reg = <0x3c>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_camera>;
clocks = <&clks IMX7D_CLKO1_ROOT_DIV>;
assigned-clocks = <&clks IMX7D_CLKO1_ROOT_DIV>;
assigned-clock-rates = <24000000>;
enable-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
vdda-supply = <&reg_2p5v>;
vdddo-supply = <&reg_vref_1v8>;
vddd-supply = <&reg_1p5v>;
port {
ov5645_to_mipi_csi2: endpoint {
remote-endpoint = <&mipi_csi2_in>;
clock-lanes = <0>;
data-lanes = <1 2>;
};
};
};
};
&usdhc1 {
@@ -93,5 +127,37 @@ MX7D_PAD_EPDC_DATA04__GPIO2_IO4 0x14
MX7D_PAD_EPDC_DATA13__GPIO2_IO13 0x14
>;
};
};
&iomuxc_lpsr {
pinctrl_camera: cameragrp {
fsl,pins = <
MX7D_PAD_LPSR_GPIO1_IO04__GPIO1_IO4 0x15
MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x15
MX7D_PAD_LPSR_GPIO1_IO02__CCM_CLKO1 0x7d
>;
};
};
&csi {
status = "okay";
};
&mipi_csi {
status = "okay";
ports {
port@0 {
reg = <0>;
mipi_csi2_in: endpoint {
remote-endpoint = <&ov5645_to_mipi_csi2>;
data-lanes = <1 2>;
};
};
};
};
&video_mux {
status = "okay";
};

5
arch/arm/boot/dts/nxp/imx/imx7d-sdb.dts
View File

@@ -456,10 +456,15 @@ display_out: endpoint {
};
&pcie {
/* This property is deprecated, use reset-gpios from the Root Port node. */
reset-gpio = <&extended_io 1 GPIO_ACTIVE_LOW>;
status = "okay";
};
&pcie_port0 {
reset-gpios = <&extended_io 1 GPIO_ACTIVE_LOW>;
};
&reg_1p0d {
vin-supply = <&sw2_reg>;
};

11
arch/arm/boot/dts/nxp/imx/imx7d.dtsi
View File

@@ -155,6 +155,17 @@ pcie: pcie@33800000 {
reset-names = "pciephy", "apps", "turnoff";
fsl,imx7d-pcie-phy = <&pcie_phy>;
status = "disabled";
pcie_port0: pcie@0 {
compatible = "pciclass,0604";
device_type = "pci";
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
};
};
};
};

12
arch/arm/boot/dts/nxp/imx/imx7ulp.dtsi
View File

@@ -325,6 +325,18 @@ smc1: clock-controller@40410000 {
clock-names = "divcore", "hsrun_divcore";
};
wdog2: watchdog@40430000 {
compatible = "fsl,imx7ulp-wdt";
reg = <0x40430000 0x10000>;
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&pcc2 IMX7ULP_CLK_WDG2>;
assigned-clocks = <&pcc2 IMX7ULP_CLK_WDG2>;
assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>;
timeout-sec = <40>;
status = "disabled";
bootph-all;
};
pcc3: clock-controller@40b30000 {
compatible = "fsl,imx7ulp-pcc3";
reg = <0x40b30000 0x10000>;