From 0372cc5776e7fd5570884aed0c1e9a8a546cad66 Mon Sep 17 00:00:00 2001 From: Hugo Villeneuve Date: Thu, 5 Mar 2026 13:06:16 -0500 Subject: [PATCH 01/35] ARM: dts: imx6ul-var-som: fix warning for non-existent dc-supply property The dc-supply property is non-existent in Linux now, nor when this DTS file was created when importing it from Variscite own kernel. Therefore remove it to fix this warning: imx6ul-var-som-concerto.dtb: cpu@0 (arm,cortex-a7): Unevaluated properties are not allowed ('dc-supply' was unexpected) from schema $id: http://devicetree.org/schemas/arm/cpus.yaml Fixes: 9d6a67d9c7a9 ("ARM: dts: imx6ul: Add Variscite VAR-SOM-MX6UL SoM support") Cc: stable@kernel.org Signed-off-by: Hugo Villeneuve Signed-off-by: Frank Li --- arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi | 4 ---- 1 file changed, 4 deletions(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi index 4e536e0252de..3fb5e2fb6877 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi @@ -45,10 +45,6 @@ &clks { assigned-clock-rates = <786432000>; }; -&cpu0 { - dc-supply = <®_gpio_dvfs>; -}; - &fec1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet1>, <&pinctrl_enet1_gpio>, <&pinctrl_enet1_mdio>; From f9abbeb3e674ff7ccee647e8dd9e43c1e1b16854 Mon Sep 17 00:00:00 2001 From: Hugo Villeneuve Date: Thu, 5 Mar 2026 13:06:17 -0500 Subject: [PATCH 02/35] ARM: dts: imx6ul-var-som: fix warning for boolean property with a value dmesg warning: OF: /soc/bus@2000000/ethernet@20b4000/mdio/ethernet-phy@3: Read of boolean property 'micrel,rmii-reference-clock-select-25-mhz' with a value. Using of_property_read_bool() for non-boolean properties is deprecated and results in a warning during runtime since commit c141ecc3cecd ("of: Warn when of_property_read_bool() is used on non-boolean properties") micrel,rmii-reference-clock-select-25-mhz is a boolean property and should not have a value, so remove it. Signed-off-by: Hugo Villeneuve Signed-off-by: Frank Li --- arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts | 2 +- arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts index 9ff3b374a2b3..085985356668 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts @@ -79,7 +79,7 @@ ethphy1: ethernet-phy@3 { reset-gpios = <&gpio5 5 GPIO_ACTIVE_LOW>; reset-assert-us = <100000>; micrel,led-mode = <0>; - micrel,rmii-reference-clock-select-25-mhz = <1>; + micrel,rmii-reference-clock-select-25-mhz; }; }; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi index 3fb5e2fb6877..30032be6fdd5 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi @@ -64,7 +64,7 @@ ethphy0: ethernet-phy@1 { reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; reset-assert-us = <100000>; micrel,led-mode = <1>; - micrel,rmii-reference-clock-select-25-mhz = <1>; + micrel,rmii-reference-clock-select-25-mhz; }; }; }; From 8ce202ed73e037175dbd31c03bed446acff72cc0 Mon Sep 17 00:00:00 2001 From: Hugo Villeneuve Date: Thu, 5 Mar 2026 13:06:18 -0500 Subject: [PATCH 03/35] ARM: dts: imx6ul-var-som: change incorrect VAR-SOM-MX6UL references There is no Variscite module named VAR-SOM-MX6UL, but there is VAR-SOM-MX6 and also VAR-SOM-6UL, so it is confusing at first to know to which one it refers to. The imx6ul-var-som* dts/dtsi supports only the VAR-SOM-6UL [1], not VAR-SOM-MX6 [2], so modify comments and model descriptions accordingly. Link https://dev.variscite.com/var-som-6ul [1] Link: https://dev.variscite.com/var-som-mx6 [2] Signed-off-by: Hugo Villeneuve Signed-off-by: Frank Li --- arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts | 4 ++-- arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts index 085985356668..35ce647a6407 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Support for Variscite MX6 Concerto Carrier board with the VAR-SOM-MX6UL + * Support for Variscite Concerto Carrier board with the VAR-SOM-6UL * Variscite SoM mounted on it * * Copyright 2019 Variscite Ltd. @@ -11,7 +11,7 @@ #include / { - model = "Variscite VAR-SOM-MX6UL Concerto Board"; + model = "Variscite VAR-SOM-6UL Concerto Board"; compatible = "variscite,mx6ulconcerto", "variscite,var-som-imx6ul", "fsl,imx6ul"; chosen { diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi index 30032be6fdd5..7259526e2b88 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Support for Variscite VAR-SOM-MX6UL Module + * Support for Variscite VAR-SOM-6UL Module * * Copyright 2019 Variscite Ltd. * Copyright 2025 Bootlin @@ -13,7 +13,7 @@ #include / { - model = "Variscite VAR-SOM-MX6UL module"; + model = "Variscite VAR-SOM-6UL module"; compatible = "variscite,var-som-imx6ul", "fsl,imx6ul"; memory@80000000 { From cc04ee842ce82b02485f6bd6f68b1749c2518358 Mon Sep 17 00:00:00 2001 From: Hugo Villeneuve Date: Thu, 5 Mar 2026 13:06:19 -0500 Subject: [PATCH 04/35] dt-bindings: arm: fsl: change incorrect VAR-SOM-MX6UL references There is no Variscite module named VAR-SOM-MX6UL, but there is VAR-SOM-MX6 and also VAR-SOM-6UL, so it is confusing at first to know to which one it refers to. The imx6ul-var-som* dts/dtsi supports only the VAR-SOM-6UL [1], not VAR-SOM-MX6 [2], so modify comments and model descriptions accordingly. Link https://dev.variscite.com/var-som-6ul [1] Link: https://dev.variscite.com/var-som-mx6 [2] Signed-off-by: Hugo Villeneuve Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/all/20260305180651.1827087-4-hugo@hugovil.com/ [1] Signed-off-by: Frank Li --- Documentation/devicetree/bindings/arm/fsl.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 5716d701292c..99dc1b3f1ba9 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -688,7 +688,7 @@ properties: - const: phytec,imx6ul-pcl063 # PHYTEC phyCORE-i.MX 6UL - const: fsl,imx6ul - - description: i.MX6UL Variscite VAR-SOM-MX6 Boards + - description: i.MX6UL Variscite VAR-SOM-6UL Boards items: - const: variscite,mx6ulconcerto - const: variscite,var-som-imx6ul From 116f95fc84c85bc7f7c6e5665a53d825f2439710 Mon Sep 17 00:00:00 2001 From: Hugo Villeneuve Date: Thu, 5 Mar 2026 13:06:20 -0500 Subject: [PATCH 05/35] dt-bindings: arm: fsl: add variscite,var-som-imx6ull Add support for the imx6ull CPU variant of the Variscite concerto board evaluation kit with a VAR-SOM-6UL. Acked-by: Krzysztof Kozlowski Signed-off-by: Hugo Villeneuve Signed-off-by: Frank Li --- Documentation/devicetree/bindings/arm/fsl.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 99dc1b3f1ba9..61cda40d3187 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -797,6 +797,12 @@ properties: - const: phytec,imx6ull-pcl063 # PHYTEC phyCORE-i.MX 6ULL - const: fsl,imx6ull + - description: i.MX6ULL Variscite VAR-SOM-6UL Boards + items: + - const: variscite,mx6ullconcerto # Variscite VAR-SOM-6UL dev kit board + - const: variscite,var-som-imx6ull # Variscite VAR-SOM-6UL SoM (6ULL variant) + - const: fsl,imx6ull + - description: i.MX6ULL Boards with Toradex Colibri iMX6ULL Modules items: - enum: From e3b21b337513bab93bebea4cc6ad226281ef7ae5 Mon Sep 17 00:00:00 2001 From: Hugo Villeneuve Date: Thu, 5 Mar 2026 13:06:21 -0500 Subject: [PATCH 06/35] ARM: dts: imx6ul-var-som: Factor out common parts for all CPU variants Factor out the parts on the Variscite VAR-SOM-6UL [1] that are common to all CPU variants (6UL, 6ULL, etc). This will simplify adding future dedicated device tree files for each CPU variant. Link https://dev.variscite.com/var-som-6ul [1] Signed-off-by: Hugo Villeneuve Signed-off-by: Frank Li --- .../dts/nxp/imx/imx6ul-var-som-common.dtsi | 227 ++++++++++++++++++ arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi | 214 +---------------- .../arm/boot/dts/nxp/imx/imx6ull-var-som.dtsi | 15 ++ 3 files changed, 243 insertions(+), 213 deletions(-) create mode 100644 arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi create mode 100644 arch/arm/boot/dts/nxp/imx/imx6ull-var-som.dtsi diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi new file mode 100644 index 000000000000..2072e8ba4d46 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi @@ -0,0 +1,227 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Support for the common parts shared by all the different CPU options on + * Variscite VAR-SOM-6UL Module + * + * Copyright 2019 Variscite Ltd. + * Copyright 2025 Bootlin + */ + +#include +#include + +/ { + model = "Variscite VAR-SOM-6UL module"; + compatible = "variscite,var-som-imx6ul", "fsl,imx6ul"; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x20000000>; + }; + + reg_gpio_dvfs: reg-gpio-dvfs { + compatible = "regulator-gpio"; + regulator-min-microvolt = <1300000>; + regulator-max-microvolt = <1400000>; + regulator-name = "gpio_dvfs"; + regulator-type = "voltage"; + gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>; + states = <1300000 0x1 + 1400000 0x0>; + }; + + rmii_ref_clk: rmii-ref-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + clock-output-names = "rmii-ref"; + }; +}; + +&clks { + assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; + assigned-clock-rates = <786432000>; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>, <&pinctrl_enet1_gpio>, <&pinctrl_enet1_mdio>; + phy-mode = "rmii"; + phy-handle = <ðphy0>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + clocks = <&rmii_ref_clk>; + clock-names = "rmii-ref"; + reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; + reset-assert-us = <100000>; + micrel,led-mode = <1>; + micrel,rmii-reference-clock-select-25-mhz; + }; + }; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_hog>; + + pinctrl_enet1: enet1grp { + fsl,pins = < + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 + MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 + >; + }; + + pinctrl_enet1_gpio: enet1-gpiogrp { + fsl,pins = < + MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b0b0 /* fec1 reset */ + >; + }; + + pinctrl_enet1_mdio: enet1-mdiogrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0 + MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0 + >; + }; + + pinctrl_hog: hoggrp { + fsl,pins = < + MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x1b0b0 /* BT Enable */ + MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x03029 /* WLAN Enable */ + >; + }; + + pinctrl_sai2: sai2grp { + fsl,pins = < + MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088 + MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088 + MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x11088 + MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x11088 + MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x17088 + >; + }; + + pinctrl_tsc: tscgrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0 + MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0 + MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0 + MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1 + MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1 + MX6UL_PAD_UART2_CTS_B__UART2_DCE_CTS 0x1b0b1 + MX6UL_PAD_UART2_RTS_B__UART2_DCE_RTS 0x1b0b1 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100b9 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170b9 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170b9 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170b9 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170b9 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170b9 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170b9 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170f9 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170f9 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170f9 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170f9 + >; + }; +}; + +&pxp { + status = "okay"; +}; + +&sai2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai2>; + assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>, + <&clks IMX6UL_CLK_SAI2>; + assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; + assigned-clock-rates = <0>, <12288000>; + fsl,sai-mclk-direction-output; + status = "okay"; +}; + +&snvs_poweroff { + status = "okay"; +}; + +&tsc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tsc>; + xnur-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>; + measure-delay-time = <0xffff>; + pre-charge-time = <0xfff>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + uart-has-rtscts; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>; + bus-width = <8>; + no-1-8-v; + non-removable; + keep-power-in-suspend; + wakeup-source; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi index 7259526e2b88..35a0c0b3603f 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi @@ -9,221 +9,9 @@ /dts-v1/; #include "imx6ul.dtsi" -#include -#include +#include "imx6ul-var-som-common.dtsi" / { model = "Variscite VAR-SOM-6UL module"; compatible = "variscite,var-som-imx6ul", "fsl,imx6ul"; - - memory@80000000 { - device_type = "memory"; - reg = <0x80000000 0x20000000>; - }; - - reg_gpio_dvfs: reg-gpio-dvfs { - compatible = "regulator-gpio"; - regulator-min-microvolt = <1300000>; - regulator-max-microvolt = <1400000>; - regulator-name = "gpio_dvfs"; - regulator-type = "voltage"; - gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>; - states = <1300000 0x1 - 1400000 0x0>; - }; - - rmii_ref_clk: rmii-ref-clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; - clock-output-names = "rmii-ref"; - }; -}; - -&clks { - assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; - assigned-clock-rates = <786432000>; -}; - -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet1>, <&pinctrl_enet1_gpio>, <&pinctrl_enet1_mdio>; - phy-mode = "rmii"; - phy-handle = <ðphy0>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - clocks = <&rmii_ref_clk>; - clock-names = "rmii-ref"; - reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; - reset-assert-us = <100000>; - micrel,led-mode = <1>; - micrel,rmii-reference-clock-select-25-mhz; - }; - }; -}; - -&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - - pinctrl_enet1: enet1grp { - fsl,pins = < - MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 - MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 - MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 - MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 - MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 - MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 - MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 - MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 - >; - }; - - pinctrl_enet1_gpio: enet1-gpiogrp { - fsl,pins = < - MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b0b0 /* fec1 reset */ - >; - }; - - pinctrl_enet1_mdio: enet1-mdiogrp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0 - MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0 - >; - }; - - pinctrl_hog: hoggrp { - fsl,pins = < - MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x1b0b0 /* BT Enable */ - MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x03029 /* WLAN Enable */ - >; - }; - - pinctrl_sai2: sai2grp { - fsl,pins = < - MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088 - MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088 - MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x11088 - MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x11088 - MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x17088 - >; - }; - - pinctrl_tsc: tscgrp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0 - MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0 - MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0 - MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1 - MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1 - MX6UL_PAD_UART2_CTS_B__UART2_DCE_CTS 0x1b0b1 - MX6UL_PAD_UART2_RTS_B__UART2_DCE_RTS 0x1b0b1 - >; - }; - - pinctrl_usdhc2: usdhc2grp { - fsl,pins = < - MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069 - MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 - MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 - MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 - MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 - MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 - MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059 - MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059 - MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059 - MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059 - >; - }; - - pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { - fsl,pins = < - MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100b9 - MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170b9 - MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9 - MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9 - MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9 - MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170b9 - MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170b9 - MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170b9 - MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170b9 - MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170b9 - >; - }; - - pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { - fsl,pins = < - MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9 - MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9 - MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9 - MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9 - MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9 - MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9 - MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170f9 - MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170f9 - MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170f9 - MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170f9 - >; - }; -}; - -&pxp { - status = "okay"; -}; - -&sai2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sai2>; - assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>, - <&clks IMX6UL_CLK_SAI2>; - assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; - assigned-clock-rates = <0>, <12288000>; - fsl,sai-mclk-direction-output; - status = "okay"; -}; - -&snvs_poweroff { - status = "okay"; -}; - -&tsc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_tsc>; - xnur-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>; - measure-delay-time = <0xffff>; - pre-charge-time = <0xfff>; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - uart-has-rtscts; - status = "okay"; -}; - -&usdhc2 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc2>; - pinctrl-1 = <&pinctrl_usdhc2_100mhz>; - pinctrl-2 = <&pinctrl_usdhc2_200mhz>; - bus-width = <8>; - no-1-8-v; - non-removable; - keep-power-in-suspend; - wakeup-source; - status = "okay"; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-var-som.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ull-var-som.dtsi new file mode 100644 index 000000000000..ba482a97623b --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-var-som.dtsi @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Support for Variscite VAR-SOM-6UL module with imx6ull CPU + * + * Copyright 2019-2024 Variscite Ltd. + * Copyright 2026 Dimonoff + */ + +#include "imx6ull.dtsi" +#include "imx6ul-var-som-common.dtsi" + +/ { + model = "Variscite VAR-SOM-6UL module"; + compatible = "variscite,var-som-imx6ull", "fsl,imx6ull"; +}; From 19435b532a13122a795454f36a6688380e1b522c Mon Sep 17 00:00:00 2001 From: Hugo Villeneuve Date: Thu, 5 Mar 2026 13:06:22 -0500 Subject: [PATCH 07/35] ARM: dts: imx6ul-var-som-concerto: Factor out common parts for all CPU variants Export common parts to the Variscite VAR-SOM-6UL dtsi so that they can be reused on other boards and to simplify adding future dedicated device tree files for each CPU variant. Move i2c1 pinctrl to var-som dtsi pinmux, so that it can be reused by other boards. Signed-off-by: Hugo Villeneuve Signed-off-by: Frank Li --- arch/arm/boot/dts/nxp/imx/Makefile | 1 + .../dts/nxp/imx/imx6ul-var-som-common.dtsi | 7 + .../imx/imx6ul-var-som-concerto-common.dtsi | 309 +++++++++++++++++ .../dts/nxp/imx/imx6ul-var-som-concerto.dts | 312 +----------------- .../dts/nxp/imx/imx6ull-var-som-concerto.dts | 17 + 5 files changed, 339 insertions(+), 307 deletions(-) create mode 100644 arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-common.dtsi create mode 100644 arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto.dts diff --git a/arch/arm/boot/dts/nxp/imx/Makefile b/arch/arm/boot/dts/nxp/imx/Makefile index de4142e8f3ce..4f212569d2cd 100644 --- a/arch/arm/boot/dts/nxp/imx/Makefile +++ b/arch/arm/boot/dts/nxp/imx/Makefile @@ -377,6 +377,7 @@ dtb-$(CONFIG_SOC_IMX6UL) += \ imx6ull-tqma6ull2-mba6ulx.dtb \ imx6ull-tqma6ull2l-mba6ulx.dtb \ imx6ull-uti260b.dtb \ + imx6ull-var-som-concerto.dtb \ imx6ulz-14x14-evk.dtb \ imx6ulz-bsh-smm-m2.dtb dtb-$(CONFIG_SOC_IMX7D) += \ diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi index 2072e8ba4d46..22b0c4e0725a 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi @@ -104,6 +104,13 @@ MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x03029 /* WLAN Enable */ >; }; + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6UL_PAD_CSI_PIXCLK__I2C1_SCL 0x4001b8b0 + MX6UL_PAD_CSI_MCLK__I2C1_SDA 0x4001b8b0 + >; + }; + pinctrl_sai2: sai2grp { fsl,pins = < MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088 diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-common.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-common.dtsi new file mode 100644 index 000000000000..1cf4a4d6495f --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-common.dtsi @@ -0,0 +1,309 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Support for Variscite Concerto Carrier board with the VAR-SOM-6UL + * Variscite SoM mounted on it (all CPU variants) + * + * Copyright 2019 Variscite Ltd. + * Copyright 2025 Bootlin + */ + +#include + +/ { + chosen { + stdout-path = &uart1; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_key_back>, <&pinctrl_gpio_key_wakeup>; + + key-back { + gpios = <&gpio4 14 GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + key-wakeup { + gpios = <&gpio5 8 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + led-0 { + function = LED_FUNCTION_STATUS; + color = ; + label = "gpled2"; + gpios = <&gpio1 25 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + status = "okay"; +}; + +&fec1 { + status = "disabled"; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet2>, <&pinctrl_enet2_gpio>, <&pinctrl_enet2_mdio>; + phy-mode = "rmii"; + phy-handle = <ðphy1>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy1: ethernet-phy@3 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <3>; + clocks = <&rmii_ref_clk>; + clock-names = "rmii-ref"; + reset-gpios = <&gpio5 5 GPIO_ACTIVE_LOW>; + reset-assert-us = <100000>; + micrel,led-mode = <0>; + micrel,rmii-reference-clock-select-25-mhz; + }; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + rtc@68 { + /* + * To actually use this interrupt + * connect pins J14.8 & J14.10 on the Concerto-Board. + */ + compatible = "dallas,ds1337"; + reg = <0x68>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rtc>; + interrupt-parent = <&gpio1>; + interrupts = <10 IRQ_TYPE_EDGE_FALLING>; + }; +}; + +&iomuxc { + pinctrl_enet2: enet2grp { + fsl,pins = < + MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 + MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 + MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 + MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031 + >; + }; + + pinctrl_enet2_gpio: enet2-gpiogrp { + fsl,pins = < + MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x1b0b0 /* fec2 reset */ + >; + }; + + pinctrl_enet2_mdio: enet2-mdiogrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 + MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020 + MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020 + >; + }; + + pinctrl_gpio_key_back: gpio-key-backgrp { + fsl,pins = < + MX6UL_PAD_NAND_CE1_B__GPIO4_IO14 0x17059 + >; + }; + + pinctrl_gpio_leds: gpio-ledsgrp { + fsl,pins = < + MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25 0x1b0b0 /* GPLED2 */ + >; + }; + + pinctrl_gpio_key_wakeup: gpio-keys-wakeupgrp { + fsl,pins = < + MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x17059 + >; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO05__PWM4_OUT 0x110b0 + >; + }; + + pinctrl_rtc: rtcgrp { + fsl,pins = < + MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0x1b0b0 /* RTC alarm IRQ */ + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_uart5: uart5grp { + fsl,pins = < + MX6UL_PAD_CSI_DATA00__UART5_DCE_TX 0x1b0b1 + MX6UL_PAD_CSI_DATA01__UART5_DCE_RX 0x1b0b1 + MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS 0x1b0b1 + MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS 0x1b0b1 + >; + }; + + pinctrl_usb_otg1_id: usbotg1idgrp { + fsl,pins = < + MX6UL_PAD_UART3_TX_DATA__ANATOP_OTG1_ID 0x17059 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x17059 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 + >; + }; + + pinctrl_usdhc1_gpio: usdhc1-gpiogrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO00__GPIO1_IO00 0x1b0b1 /* CD */ + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO01__WDOG1_WDOG_B 0x78b0 + >; + }; +}; + +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; + status = "okay"; +}; + +&snvs_pwrkey { + status = "disabled"; +}; + +&snvs_rtc { + status = "disabled"; +}; + +&tsc { + /* + * Conflics with wdog1 ext-reset-output & SD CD pins, + * so we keep it disabled by default. + */ + status = "disabled"; +}; + +/* Console UART */ +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +/* ttymxc4 UART */ +&uart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + uart-has-rtscts; + status = "okay"; +}; + +&usbotg1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_otg1_id>; + dr_mode = "otg"; + disable-over-current; + srp-disable; + hnp-disable; + adp-disable; + status = "okay"; +}; + +&usbotg2 { + dr_mode = "host"; + disable-over-current; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>; + cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; + no-1-8-v; + keep-power-in-suspend; + wakeup-source; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + /* + * To actually use ext-reset-output + * connect pins J17.3 & J17.8 on the Concerto-Board + */ + fsl,ext-reset-output; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts index 35ce647a6407..8872bf55827e 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts @@ -1,320 +1,18 @@ // SPDX-License-Identifier: GPL-2.0+ /* * Support for Variscite Concerto Carrier board with the VAR-SOM-6UL - * Variscite SoM mounted on it + * Variscite SoM mounted on it (6UL CPU variant) * * Copyright 2019 Variscite Ltd. * Copyright 2025 Bootlin */ +/dts-v1/; + #include "imx6ul-var-som.dtsi" -#include +#include "imx6ul-var-som-concerto-common.dtsi" / { - model = "Variscite VAR-SOM-6UL Concerto Board"; + model = "Variscite VAR-SOM-6UL Concerto Board (6UL CPU)"; compatible = "variscite,mx6ulconcerto", "variscite,var-som-imx6ul", "fsl,imx6ul"; - - chosen { - stdout-path = &uart1; - }; - - gpio-keys { - compatible = "gpio-keys"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_key_back>, <&pinctrl_gpio_key_wakeup>; - - key-back { - gpios = <&gpio4 14 GPIO_ACTIVE_LOW>; - linux,code = ; - }; - - key-wakeup { - gpios = <&gpio5 8 GPIO_ACTIVE_LOW>; - linux,code = ; - wakeup-source; - }; - }; - - leds { - compatible = "gpio-leds"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio_leds>; - - led-0 { - function = LED_FUNCTION_STATUS; - color = ; - label = "gpled2"; - gpios = <&gpio1 25 GPIO_ACTIVE_HIGH>; - linux,default-trigger = "heartbeat"; - }; - }; -}; - -&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1>; - status = "okay"; -}; - -&fec1 { - status = "disabled"; -}; - -&fec2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet2>, <&pinctrl_enet2_gpio>, <&pinctrl_enet2_mdio>; - phy-mode = "rmii"; - phy-handle = <ðphy1>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy1: ethernet-phy@3 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <3>; - clocks = <&rmii_ref_clk>; - clock-names = "rmii-ref"; - reset-gpios = <&gpio5 5 GPIO_ACTIVE_LOW>; - reset-assert-us = <100000>; - micrel,led-mode = <0>; - micrel,rmii-reference-clock-select-25-mhz; - }; - }; -}; - -&i2c1 { - clock-frequency = <100000>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - rtc@68 { - /* - * To actually use this interrupt - * connect pins J14.8 & J14.10 on the Concerto-Board. - */ - compatible = "dallas,ds1337"; - reg = <0x68>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rtc>; - interrupt-parent = <&gpio1>; - interrupts = <10 IRQ_TYPE_EDGE_FALLING>; - }; -}; - -&iomuxc { - pinctrl_enet2: enet2grp { - fsl,pins = < - MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 - MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 - MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 - MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 - MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 - MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 - MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 - MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031 - >; - }; - - pinctrl_enet2_gpio: enet2-gpiogrp { - fsl,pins = < - MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x1b0b0 /* fec2 reset */ - >; - }; - - pinctrl_enet2_mdio: enet2-mdiogrp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 - MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 - >; - }; - - pinctrl_flexcan1: flexcan1grp { - fsl,pins = < - MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020 - MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020 - >; - }; - - pinctrl_gpio_key_back: gpio-key-backgrp { - fsl,pins = < - MX6UL_PAD_NAND_CE1_B__GPIO4_IO14 0x17059 - >; - }; - - pinctrl_gpio_leds: gpio-ledsgrp { - fsl,pins = < - MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25 0x1b0b0 /* GPLED2 */ - >; - }; - - pinctrl_gpio_key_wakeup: gpio-keys-wakeupgrp { - fsl,pins = < - MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x17059 - >; - }; - - pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6UL_PAD_CSI_PIXCLK__I2C1_SCL 0x4001b8b0 - MX6UL_PAD_CSI_MCLK__I2C1_SDA 0x4001b8b0 - >; - }; - - pinctrl_pwm4: pwm4grp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO05__PWM4_OUT 0x110b0 - >; - }; - - pinctrl_rtc: rtcgrp { - fsl,pins = < - MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0x1b0b0 /* RTC alarm IRQ */ - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 - MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 - >; - }; - - pinctrl_uart5: uart5grp { - fsl,pins = < - MX6UL_PAD_CSI_DATA00__UART5_DCE_TX 0x1b0b1 - MX6UL_PAD_CSI_DATA01__UART5_DCE_RX 0x1b0b1 - MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS 0x1b0b1 - MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS 0x1b0b1 - >; - }; - - pinctrl_usb_otg1_id: usbotg1idgrp { - fsl,pins = < - MX6UL_PAD_UART3_TX_DATA__ANATOP_OTG1_ID 0x17059 - >; - }; - - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 - MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x17059 - MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 - MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 - MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 - MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 - >; - }; - - pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { - fsl,pins = < - MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 - MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 - MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 - MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 - MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 - MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 - >; - }; - - pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { - fsl,pins = < - MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 - MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 - MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 - MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 - MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 - MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 - >; - }; - - pinctrl_usdhc1_gpio: usdhc1-gpiogrp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO00__GPIO1_IO00 0x1b0b1 /* CD */ - >; - }; - - pinctrl_wdog: wdoggrp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO01__WDOG1_WDOG_B 0x78b0 - >; - }; -}; - -&pwm4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm4>; - status = "okay"; -}; - -&snvs_pwrkey { - status = "disabled"; -}; - -&snvs_rtc { - status = "disabled"; -}; - -&tsc { - /* - * Conflics with wdog1 ext-reset-output & SD CD pins, - * so we keep it disabled by default. - */ - status = "disabled"; -}; - -/* Console UART */ -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - status = "okay"; -}; - -/* ttymxc4 UART */ -&uart5 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart5>; - uart-has-rtscts; - status = "okay"; -}; - -&usbotg1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb_otg1_id>; - dr_mode = "otg"; - disable-over-current; - srp-disable; - hnp-disable; - adp-disable; - status = "okay"; -}; - -&usbotg2 { - dr_mode = "host"; - disable-over-current; - status = "okay"; -}; - -&usdhc1 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>; - pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>; - pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>; - cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; - no-1-8-v; - keep-power-in-suspend; - wakeup-source; - status = "okay"; -}; - -&wdog1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_wdog>; - /* - * To actually use ext-reset-output - * connect pins J17.3 & J17.8 on the Concerto-Board - */ - fsl,ext-reset-output; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto.dts new file mode 100644 index 000000000000..9413c946e2d9 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto.dts @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Support for Variscite Concerto Carrier board with the VAR-SOM-6UL + * Variscite SoM mounted on it (6ULL CPU variant) + * + * Copyright 2026 Dimonoff + */ + +/dts-v1/; + +#include "imx6ull-var-som.dtsi" +#include "imx6ul-var-som-concerto-common.dtsi" + +/ { + model = "Variscite VAR-SOM-6UL Concerto Board (6ULL CPU)"; + compatible = "variscite,mx6ullconcerto", "variscite,var-som-imx6ull", "fsl,imx6ull"; +}; From 0d2f2cd6f4c2449d2338c8ce76a7ed73bbf0fde0 Mon Sep 17 00:00:00 2001 From: Hugo Villeneuve Date: Thu, 5 Mar 2026 13:06:23 -0500 Subject: [PATCH 08/35] ARM: dts: imx6ul-var-som-concerto: order DT properties reorder pinctrl_gpio_leds to respect alphabetical order. Signed-off-by: Hugo Villeneuve Signed-off-by: Frank Li --- .../dts/nxp/imx/imx6ul-var-som-concerto-common.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-common.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-common.dtsi index 1cf4a4d6495f..d40264b55324 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-common.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-common.dtsi @@ -140,18 +140,18 @@ MX6UL_PAD_NAND_CE1_B__GPIO4_IO14 0x17059 >; }; - pinctrl_gpio_leds: gpio-ledsgrp { - fsl,pins = < - MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25 0x1b0b0 /* GPLED2 */ - >; - }; - pinctrl_gpio_key_wakeup: gpio-keys-wakeupgrp { fsl,pins = < MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x17059 >; }; + pinctrl_gpio_leds: gpio-ledsgrp { + fsl,pins = < + MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25 0x1b0b0 /* GPLED2 */ + >; + }; + pinctrl_pwm4: pwm4grp { fsl,pins = < MX6UL_PAD_GPIO1_IO05__PWM4_OUT 0x110b0 From f47685063daa995cbeeca871330c64e0b88442a4 Mon Sep 17 00:00:00 2001 From: Hugo Villeneuve Date: Thu, 5 Mar 2026 13:06:24 -0500 Subject: [PATCH 09/35] ARM: dts: imx6ul-var-som: factor out SD card support Move SD support to a separate dtsi, since it cannot be used at the same time as the Wifi/BT module. Also not all boards support the SD card. Move pinctrl_usdhc1* to the common imx6ul-var-som-common dtsi so that it can be used by the future Wifi/BT dtsi. Signed-off-by: Hugo Villeneuve Signed-off-by: Frank Li --- .../dts/nxp/imx/imx6ul-var-som-common.dtsi | 33 ++++++++++++ .../imx/imx6ul-var-som-concerto-common.dtsi | 51 ------------------- .../dts/nxp/imx/imx6ul-var-som-concerto.dts | 1 + .../boot/dts/nxp/imx/imx6ul-var-som-sd.dtsi | 27 ++++++++++ .../dts/nxp/imx/imx6ull-var-som-concerto.dts | 1 + 5 files changed, 62 insertions(+), 51 deletions(-) create mode 100644 arch/arm/boot/dts/nxp/imx/imx6ul-var-som-sd.dtsi diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi index 22b0c4e0725a..dd4ecff1eb78 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi @@ -139,6 +139,39 @@ MX6UL_PAD_UART2_RTS_B__UART2_DCE_RTS 0x1b0b1 >; }; + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x17059 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 + >; + }; + pinctrl_usdhc2: usdhc2grp { fsl,pins = < MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069 diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-common.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-common.dtsi index d40264b55324..161b476474af 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-common.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-common.dtsi @@ -186,45 +186,6 @@ MX6UL_PAD_UART3_TX_DATA__ANATOP_OTG1_ID 0x17059 >; }; - pinctrl_usdhc1: usdhc1grp { - fsl,pins = < - MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 - MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x17059 - MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 - MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 - MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 - MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 - >; - }; - - pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { - fsl,pins = < - MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 - MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 - MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 - MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 - MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 - MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 - >; - }; - - pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { - fsl,pins = < - MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 - MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 - MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 - MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 - MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 - MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 - >; - }; - - pinctrl_usdhc1_gpio: usdhc1-gpiogrp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO00__GPIO1_IO00 0x1b0b1 /* CD */ - >; - }; - pinctrl_wdog: wdoggrp { fsl,pins = < MX6UL_PAD_GPIO1_IO01__WDOG1_WDOG_B 0x78b0 @@ -286,18 +247,6 @@ &usbotg2 { status = "okay"; }; -&usdhc1 { - pinctrl-names = "default", "state_100mhz", "state_200mhz"; - pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>; - pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>; - pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>; - cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; - no-1-8-v; - keep-power-in-suspend; - wakeup-source; - status = "okay"; -}; - &wdog1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_wdog>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts index 8872bf55827e..92d98e4fc775 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts @@ -11,6 +11,7 @@ #include "imx6ul-var-som.dtsi" #include "imx6ul-var-som-concerto-common.dtsi" +#include "imx6ul-var-som-sd.dtsi" / { model = "Variscite VAR-SOM-6UL Concerto Board (6UL CPU)"; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-sd.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-sd.dtsi new file mode 100644 index 000000000000..0e6d9b945eb4 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-sd.dtsi @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Support optional SD card interface on Variscite VAR-SOM-6UL module. + * + * Copyright 2019-2024 Variscite Ltd. + * Copyright 2026 Dimonoff + */ + +&iomuxc { + pinctrl_usdhc1_gpio: usdhc1-gpiogrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO00__GPIO1_IO00 0x1b0b1 /* CD */ + >; + }; +}; + +&usdhc1 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>; + cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; + no-1-8-v; + keep-power-in-suspend; + wakeup-source; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto.dts index 9413c946e2d9..d33d5c5afcc2 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto.dts @@ -10,6 +10,7 @@ #include "imx6ull-var-som.dtsi" #include "imx6ul-var-som-concerto-common.dtsi" +#include "imx6ul-var-som-sd.dtsi" / { model = "Variscite VAR-SOM-6UL Concerto Board (6ULL CPU)"; From 235c070343eb69c1a1d1b4aafb876578eb6d2c45 Mon Sep 17 00:00:00 2001 From: Hugo Villeneuve Date: Thu, 5 Mar 2026 13:06:25 -0500 Subject: [PATCH 10/35] ARM: dts: imx6ul-var-som: add proper Wifi and Bluetooth support Add proper support for the optional Wifi and Bluetooth configuration on VAR-SOM-6UL so that it works out of the box, without any custom scripts. The Wifi/BT module support is mutually exclusive with SD card interface. Signed-off-by: Hugo Villeneuve Signed-off-by: Frank Li --- arch/arm/boot/dts/nxp/imx/Makefile | 2 + .../dts/nxp/imx/imx6ul-var-som-common.dtsi | 18 ++--- .../nxp/imx/imx6ul-var-som-concerto-full.dts | 18 +++++ .../boot/dts/nxp/imx/imx6ul-var-som-wifi.dtsi | 75 +++++++++++++++++++ arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi | 15 ++++ .../nxp/imx/imx6ull-var-som-concerto-full.dts | 18 +++++ .../arm/boot/dts/nxp/imx/imx6ull-var-som.dtsi | 15 ++++ 7 files changed, 151 insertions(+), 10 deletions(-) create mode 100644 arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-full.dts create mode 100644 arch/arm/boot/dts/nxp/imx/imx6ul-var-som-wifi.dtsi create mode 100644 arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto-full.dts diff --git a/arch/arm/boot/dts/nxp/imx/Makefile b/arch/arm/boot/dts/nxp/imx/Makefile index 4f212569d2cd..b81668dcaccf 100644 --- a/arch/arm/boot/dts/nxp/imx/Makefile +++ b/arch/arm/boot/dts/nxp/imx/Makefile @@ -339,6 +339,7 @@ dtb-$(CONFIG_SOC_IMX6UL) += \ imx6ul-tx6ul-0011.dtb \ imx6ul-tx6ul-mainboard.dtb \ imx6ul-var-som-concerto.dtb \ + imx6ul-var-som-concerto-full.dtb \ imx6ull-14x14-evk.dtb \ imx6ull-colibri-aster.dtb \ imx6ull-colibri-emmc-aster.dtb \ @@ -378,6 +379,7 @@ dtb-$(CONFIG_SOC_IMX6UL) += \ imx6ull-tqma6ull2l-mba6ulx.dtb \ imx6ull-uti260b.dtb \ imx6ull-var-som-concerto.dtb \ + imx6ull-var-som-concerto-full.dtb \ imx6ulz-14x14-evk.dtb \ imx6ulz-bsh-smm-m2.dtb dtb-$(CONFIG_SOC_IMX7D) += \ diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi index dd4ecff1eb78..af8c5d2db53d 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi @@ -19,6 +19,14 @@ memory@80000000 { reg = <0x80000000 0x20000000>; }; + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + reg_gpio_dvfs: reg-gpio-dvfs { compatible = "regulator-gpio"; regulator-min-microvolt = <1300000>; @@ -68,9 +76,6 @@ ethphy0: ethernet-phy@1 { }; &iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_hog>; - pinctrl_enet1: enet1grp { fsl,pins = < MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 @@ -97,13 +102,6 @@ MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0 >; }; - pinctrl_hog: hoggrp { - fsl,pins = < - MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x1b0b0 /* BT Enable */ - MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x03029 /* WLAN Enable */ - >; - }; - pinctrl_i2c1: i2c1grp { fsl,pins = < MX6UL_PAD_CSI_PIXCLK__I2C1_SCL 0x4001b8b0 diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-full.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-full.dts new file mode 100644 index 000000000000..519250b31db2 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-full.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Support for Variscite MX6 Concerto Carrier board with the VAR-SOM-6UL + * Variscite SoM mounted on it (6UL CPU variant). + * + * Copyright 2026 Dimonoff + */ + +/dts-v1/; + +#include "imx6ul-var-som.dtsi" +#include "imx6ul-var-som-concerto-common.dtsi" +#include "imx6ul-var-som-wifi.dtsi" + +/ { + model = "Variscite VAR-SOM-6UL Concerto Board (6UL CPU)"; + compatible = "variscite,mx6ulconcerto", "variscite,var-som-imx6ul", "fsl,imx6ul"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-wifi.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-wifi.dtsi new file mode 100644 index 000000000000..6d16ff7909da --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-wifi.dtsi @@ -0,0 +1,75 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Support optional Wifi/Bluetooth on Variscite VAR-SOM-6UL module. + * + * Copyright 2019-2024 Variscite Ltd. + * Copyright 2026 Dimonoff + */ + +/ { + reg_sd1_vmmc: regulator_sd1_vmmc { + compatible = "regulator-fixed"; + regulator-name = "VMMC1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio5 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + startup-delay-us = <10000>; + }; + + usdhc1_pwrseq: usdhc1-pwrseq { + compatible = "mmc-pwrseq-simple"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_brcm_wifi>; + reset-gpios = <&gpio5 6 GPIO_ACTIVE_LOW>; + }; +}; + +&iomuxc { + pinctrl_32k_clk: 32kclkgrp { + /* + * For TP option, an additional oscillator is assembled on the + * SOM to provide 32 kHz to the WiFi module. Without TP option, + * this pin is configured to provide the 32 KHz clock to the + * WiFi module. + */ + fsl,pins = < + MX6UL_PAD_GPIO1_IO03__OSC32K_32K_OUT 0x03029 + >; + }; +}; + +&tsc { + status = "disabled"; +}; + +/* Bluetooth UART */ +&uart2 { + bluetooth { + compatible = "brcm,bcm43438-bt"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_brcm_bt>; + shutdown-gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>; + vbat-supply = <®_3p3v>; + vddio-supply = <®_3p3v>; + }; +}; + +&usdhc1 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_32k_clk>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_32k_clk>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_32k_clk>; + no-1-8-v; + non-removable; + mmc-pwrseq = <&usdhc1_pwrseq>; + vmmc-supply = <®_sd1_vmmc>; + status = "okay"; + + brcmf: wifi@1 { + compatible = "brcm,bcm4329-fmac"; /* LWB option: Sterling LWB5 */ + reg = <1>; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi index 35a0c0b3603f..b4e6a9316dd8 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi @@ -15,3 +15,18 @@ / { model = "Variscite VAR-SOM-6UL module"; compatible = "variscite,var-som-imx6ul", "fsl,imx6ul"; }; + +&iomuxc { + pinctrl_brcm_bt: brcm-bt-grp { + fsl,pins = < + MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x1b0b0 /* BT_REG_ON (BT_EN) */ + >; + }; + + pinctrl_brcm_wifi: brcm-wifi-grp { + fsl,pins = < + MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1b0b0 /* WL_PWR (WIFI_PWR 5G) */ + MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x1b0b0 /* WL_REG_ON (WIFI_EN) */ + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto-full.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto-full.dts new file mode 100644 index 000000000000..7c0e31360363 --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto-full.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Support for Variscite MX6 Concerto Carrier board with the VAR-SOM-6UL + * Variscite SoM mounted on it (6ULL CPU variant). + * + * Copyright 2026 Dimonoff + */ + +/dts-v1/; + +#include "imx6ull-var-som.dtsi" +#include "imx6ul-var-som-concerto-common.dtsi" +#include "imx6ul-var-som-wifi.dtsi" + +/ { + model = "Variscite VAR-SOM-6UL Concerto Board (6ULL CPU)"; + compatible = "variscite,mx6ullconcerto", "variscite,var-som-imx6ull", "fsl,imx6ull"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-var-som.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ull-var-som.dtsi index ba482a97623b..3067ff6a1bc7 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ull-var-som.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-var-som.dtsi @@ -13,3 +13,18 @@ / { model = "Variscite VAR-SOM-6UL module"; compatible = "variscite,var-som-imx6ull", "fsl,imx6ull"; }; + +&iomuxc { + pinctrl_brcm_bt: brcm-bt-grp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x1b0b0 /* BT_REG_ON (BT_EN) */ + >; + }; + + pinctrl_brcm_wifi: brcm-wifi-grp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1b0b0 /* WL_PWR (WIFI_PWR 5G) */ + MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x1b0b0 /* WL_REG_ON (WIFI_EN) */ + >; + }; +}; From 04b897252c5828e4cd31d92880229e26a630f2ff Mon Sep 17 00:00:00 2001 From: Hugo Villeneuve Date: Thu, 5 Mar 2026 13:06:26 -0500 Subject: [PATCH 11/35] ARM: dts: imx6ul-var-som: factor out ENET2 ethernet support Not all boards use the ethernet ENET2 port, so factor out this functionality to a separate dtsi. On the concerto board, this uses the ethernet PHY assembled on it. Signed-off-by: Hugo Villeneuve Signed-off-by: Frank Li --- .../dts/nxp/imx/imx6ul-var-som-common.dtsi | 7 -- .../imx/imx6ul-var-som-concerto-common.dtsi | 50 -------------- .../nxp/imx/imx6ul-var-som-concerto-full.dts | 1 + .../dts/nxp/imx/imx6ul-var-som-concerto.dts | 1 + .../dts/nxp/imx/imx6ul-var-som-enet2.dtsi | 68 +++++++++++++++++++ .../nxp/imx/imx6ull-var-som-concerto-full.dts | 1 + .../dts/nxp/imx/imx6ull-var-som-concerto.dts | 1 + 7 files changed, 72 insertions(+), 57 deletions(-) create mode 100644 arch/arm/boot/dts/nxp/imx/imx6ul-var-som-enet2.dtsi diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi index af8c5d2db53d..af9b92f7709b 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi @@ -37,13 +37,6 @@ reg_gpio_dvfs: reg-gpio-dvfs { states = <1300000 0x1 1400000 0x0>; }; - - rmii_ref_clk: rmii-ref-clk { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; - clock-output-names = "rmii-ref"; - }; }; &clks { diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-common.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-common.dtsi index 161b476474af..fead54ac8c6b 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-common.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-common.dtsi @@ -56,30 +56,6 @@ &fec1 { status = "disabled"; }; -&fec2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet2>, <&pinctrl_enet2_gpio>, <&pinctrl_enet2_mdio>; - phy-mode = "rmii"; - phy-handle = <ðphy1>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy1: ethernet-phy@3 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <3>; - clocks = <&rmii_ref_clk>; - clock-names = "rmii-ref"; - reset-gpios = <&gpio5 5 GPIO_ACTIVE_LOW>; - reset-assert-us = <100000>; - micrel,led-mode = <0>; - micrel,rmii-reference-clock-select-25-mhz; - }; - }; -}; - &i2c1 { clock-frequency = <100000>; pinctrl-names = "default"; @@ -101,32 +77,6 @@ rtc@68 { }; &iomuxc { - pinctrl_enet2: enet2grp { - fsl,pins = < - MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 - MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 - MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 - MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 - MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 - MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 - MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 - MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031 - >; - }; - - pinctrl_enet2_gpio: enet2-gpiogrp { - fsl,pins = < - MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x1b0b0 /* fec2 reset */ - >; - }; - - pinctrl_enet2_mdio: enet2-mdiogrp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 - MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 - >; - }; - pinctrl_flexcan1: flexcan1grp { fsl,pins = < MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020 diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-full.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-full.dts index 519250b31db2..3905171b47b3 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-full.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-full.dts @@ -11,6 +11,7 @@ #include "imx6ul-var-som.dtsi" #include "imx6ul-var-som-concerto-common.dtsi" #include "imx6ul-var-som-wifi.dtsi" +#include "imx6ul-var-som-enet2.dtsi" / { model = "Variscite VAR-SOM-6UL Concerto Board (6UL CPU)"; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts index 92d98e4fc775..7eebb5b4f5e4 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts @@ -12,6 +12,7 @@ #include "imx6ul-var-som.dtsi" #include "imx6ul-var-som-concerto-common.dtsi" #include "imx6ul-var-som-sd.dtsi" +#include "imx6ul-var-som-enet2.dtsi" / { model = "Variscite VAR-SOM-6UL Concerto Board (6UL CPU)"; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-enet2.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-enet2.dtsi new file mode 100644 index 000000000000..334ed3bbe02c --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-enet2.dtsi @@ -0,0 +1,68 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Ethernet ENET2 support for Variscite VAR-SOM-6UL module. + * + * Copyright 2019-2024 Variscite Ltd. + * Copyright 2026 Dimonoff + */ + +/ { + rmii_ref_clk: rmii-ref-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + clock-output-names = "rmii-ref"; + }; +}; + +&fec2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet2>, <&pinctrl_enet2_gpio>, <&pinctrl_enet2_mdio>; + phy-mode = "rmii"; + phy-handle = <ðphy1>; + status = "okay"; + + mdio_enet2: mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy1: ethernet-phy@3 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <3>; + clocks = <&rmii_ref_clk>; + clock-names = "rmii-ref"; + reset-gpios = <&gpio5 5 GPIO_ACTIVE_LOW>; + reset-assert-us = <100000>; + micrel,led-mode = <0>; + micrel,rmii-reference-clock-select-25-mhz; + }; + }; +}; + +&iomuxc { + pinctrl_enet2: enet2grp { + fsl,pins = < + MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 + MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 + MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 + MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 + MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031 + >; + }; + + pinctrl_enet2_gpio: enet2-gpiogrp { + fsl,pins = < + MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x1b0b0 /* fec2 reset */ + >; + }; + + pinctrl_enet2_mdio: enet2-mdiogrp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 + MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 + >; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto-full.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto-full.dts index 7c0e31360363..89b6032203a2 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto-full.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto-full.dts @@ -11,6 +11,7 @@ #include "imx6ull-var-som.dtsi" #include "imx6ul-var-som-concerto-common.dtsi" #include "imx6ul-var-som-wifi.dtsi" +#include "imx6ul-var-som-enet2.dtsi" / { model = "Variscite VAR-SOM-6UL Concerto Board (6ULL CPU)"; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto.dts index d33d5c5afcc2..0d3e0d9b0f11 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto.dts @@ -11,6 +11,7 @@ #include "imx6ull-var-som.dtsi" #include "imx6ul-var-som-concerto-common.dtsi" #include "imx6ul-var-som-sd.dtsi" +#include "imx6ul-var-som-enet2.dtsi" / { model = "Variscite VAR-SOM-6UL Concerto Board (6ULL CPU)"; From 38296261b071447a02eb3eb40efdb5da0a38876c Mon Sep 17 00:00:00 2001 From: Hugo Villeneuve Date: Thu, 5 Mar 2026 13:06:27 -0500 Subject: [PATCH 12/35] ARM: dts: imx6ul-var-som: add support for EC configuration option (ENET1) ENET1 is currently disabled and not supported/working on the concerto EVK. Add support for this optional configuration in a separate dtsi, so that it can be selectively enabled/disabled. Signed-off-by: Hugo Villeneuve Signed-off-by: Frank Li --- .../dts/nxp/imx/imx6ul-var-som-common.dtsi | 50 ------------------- .../imx/imx6ul-var-som-concerto-common.dtsi | 4 -- .../nxp/imx/imx6ul-var-som-concerto-full.dts | 1 + .../dts/nxp/imx/imx6ul-var-som-enet1.dtsi | 44 ++++++++++++++++ .../dts/nxp/imx/imx6ul-var-som-enet2.dtsi | 11 ++++ arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi | 6 +++ .../nxp/imx/imx6ull-var-som-concerto-full.dts | 1 + .../arm/boot/dts/nxp/imx/imx6ull-var-som.dtsi | 6 +++ 8 files changed, 69 insertions(+), 54 deletions(-) create mode 100644 arch/arm/boot/dts/nxp/imx/imx6ul-var-som-enet1.dtsi diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi index af9b92f7709b..70d19eccddb4 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi @@ -44,57 +44,7 @@ &clks { assigned-clock-rates = <786432000>; }; -&fec1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet1>, <&pinctrl_enet1_gpio>, <&pinctrl_enet1_mdio>; - phy-mode = "rmii"; - phy-handle = <ðphy0>; - status = "okay"; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - ethphy0: ethernet-phy@1 { - compatible = "ethernet-phy-ieee802.3-c22"; - reg = <1>; - clocks = <&rmii_ref_clk>; - clock-names = "rmii-ref"; - reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; - reset-assert-us = <100000>; - micrel,led-mode = <1>; - micrel,rmii-reference-clock-select-25-mhz; - }; - }; -}; - &iomuxc { - pinctrl_enet1: enet1grp { - fsl,pins = < - MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 - MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 - MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 - MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 - MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 - MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 - MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 - MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 - >; - }; - - pinctrl_enet1_gpio: enet1-gpiogrp { - fsl,pins = < - MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b0b0 /* fec1 reset */ - >; - }; - - pinctrl_enet1_mdio: enet1-mdiogrp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0 - MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0 - >; - }; - pinctrl_i2c1: i2c1grp { fsl,pins = < MX6UL_PAD_CSI_PIXCLK__I2C1_SCL 0x4001b8b0 diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-common.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-common.dtsi index fead54ac8c6b..f099ca5d0e8f 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-common.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-common.dtsi @@ -52,10 +52,6 @@ &can1 { status = "okay"; }; -&fec1 { - status = "disabled"; -}; - &i2c1 { clock-frequency = <100000>; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-full.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-full.dts index 3905171b47b3..b5e6a3306e1c 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-full.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-full.dts @@ -12,6 +12,7 @@ #include "imx6ul-var-som-concerto-common.dtsi" #include "imx6ul-var-som-wifi.dtsi" #include "imx6ul-var-som-enet2.dtsi" +#include "imx6ul-var-som-enet1.dtsi" / { model = "Variscite VAR-SOM-6UL Concerto Board (6UL CPU)"; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-enet1.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-enet1.dtsi new file mode 100644 index 000000000000..6b1e34347bec --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-enet1.dtsi @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Ethernet ENET1 support for Variscite VAR-SOM-6UL module with + * the EC configuration option ((ethernet PHY assembled on SOM). + * + * Copyright 2019-2024 Variscite Ltd. + * Copyright 2026 Dimonoff + */ + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>, <&pinctrl_enet1_gpio>; + phy-mode = "rmii"; + phy-handle = <ðphy0>; + status = "okay"; +}; + +&iomuxc { + pinctrl_enet1: enet1grp { + fsl,pins = < + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 + MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 + >; + }; +}; + +&mdio_enet2 { + ethphy0: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + clocks = <&rmii_ref_clk>; + clock-names = "rmii-ref"; + reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; + reset-assert-us = <100000>; + micrel,led-mode = <1>; + micrel,rmii-reference-clock-select-25-mhz; + }; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-enet2.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-enet2.dtsi index 334ed3bbe02c..b29fcdc079e3 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-enet2.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-enet2.dtsi @@ -26,6 +26,17 @@ mdio_enet2: mdio { #address-cells = <1>; #size-cells = <0>; + ethphy0: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + clocks = <&rmii_ref_clk>; + clock-names = "rmii-ref"; + reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; + reset-assert-us = <100000>; + micrel,led-mode = <1>; + micrel,rmii-reference-clock-select-25-mhz; + }; + ethphy1: ethernet-phy@3 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <3>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi index b4e6a9316dd8..feea24c0e068 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som.dtsi @@ -29,4 +29,10 @@ MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1b0b0 /* WL_PWR (WIFI_PWR 5G) */ MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x1b0b0 /* WL_REG_ON (WIFI_EN) */ >; }; + + pinctrl_enet1_gpio: enet1-gpiogrp { + fsl,pins = < + MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b0b0 /* fec1 reset */ + >; + }; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto-full.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto-full.dts index 89b6032203a2..86f558c76fb3 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto-full.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto-full.dts @@ -12,6 +12,7 @@ #include "imx6ul-var-som-concerto-common.dtsi" #include "imx6ul-var-som-wifi.dtsi" #include "imx6ul-var-som-enet2.dtsi" +#include "imx6ul-var-som-enet1.dtsi" / { model = "Variscite VAR-SOM-6UL Concerto Board (6ULL CPU)"; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-var-som.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ull-var-som.dtsi index 3067ff6a1bc7..f120b1dca75c 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ull-var-som.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-var-som.dtsi @@ -27,4 +27,10 @@ MX6ULL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1b0b0 /* WL_PWR (WIFI_PWR 5G) */ MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x1b0b0 /* WL_REG_ON (WIFI_EN) */ >; }; + + pinctrl_enet1_gpio: enet1-gpiogrp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x1b0b0 /* fec1 reset */ + >; + }; }; From 5f1733077a1a382a22260379b9ca333860bd00a1 Mon Sep 17 00:00:00 2001 From: Hugo Villeneuve Date: Thu, 5 Mar 2026 13:06:28 -0500 Subject: [PATCH 13/35] ARM: dts: imx6ul-var-som: factor out audio support Not all boards use the audio codec, so factor out this functionality to a separate dtsi. Signed-off-by: Hugo Villeneuve Signed-off-by: Frank Li --- .../dts/nxp/imx/imx6ul-var-som-audio.dtsi | 30 +++++++++++++++++++ .../dts/nxp/imx/imx6ul-var-som-common.dtsi | 21 ------------- .../nxp/imx/imx6ul-var-som-concerto-full.dts | 1 + .../dts/nxp/imx/imx6ul-var-som-concerto.dts | 1 + .../nxp/imx/imx6ull-var-som-concerto-full.dts | 1 + .../dts/nxp/imx/imx6ull-var-som-concerto.dts | 1 + 6 files changed, 34 insertions(+), 21 deletions(-) create mode 100644 arch/arm/boot/dts/nxp/imx/imx6ul-var-som-audio.dtsi diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-audio.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-audio.dtsi new file mode 100644 index 000000000000..3c480bc7a6ad --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-audio.dtsi @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Audio support for Variscite VAR-SOM-6UL module. + * + * Copyright 2019-2024 Variscite Ltd. + * Copyright 2026 Dimonoff + */ + +&iomuxc { + pinctrl_sai2: sai2grp { + fsl,pins = < + MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088 + MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088 + MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x11088 + MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x11088 + MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x17088 + >; + }; +}; + +&sai2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai2>; + assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>, + <&clks IMX6UL_CLK_SAI2>; + assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; + assigned-clock-rates = <0>, <12288000>; + fsl,sai-mclk-direction-output; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi index 70d19eccddb4..5600eeaa5854 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-common.dtsi @@ -52,16 +52,6 @@ MX6UL_PAD_CSI_MCLK__I2C1_SDA 0x4001b8b0 >; }; - pinctrl_sai2: sai2grp { - fsl,pins = < - MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088 - MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088 - MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x11088 - MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x11088 - MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x17088 - >; - }; - pinctrl_tsc: tscgrp { fsl,pins = < MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0 @@ -163,17 +153,6 @@ &pxp { status = "okay"; }; -&sai2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_sai2>; - assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>, - <&clks IMX6UL_CLK_SAI2>; - assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; - assigned-clock-rates = <0>, <12288000>; - fsl,sai-mclk-direction-output; - status = "okay"; -}; - &snvs_poweroff { status = "okay"; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-full.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-full.dts index b5e6a3306e1c..64a3cbd8b7c3 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-full.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-full.dts @@ -13,6 +13,7 @@ #include "imx6ul-var-som-wifi.dtsi" #include "imx6ul-var-som-enet2.dtsi" #include "imx6ul-var-som-enet1.dtsi" +#include "imx6ul-var-som-audio.dtsi" / { model = "Variscite VAR-SOM-6UL Concerto Board (6UL CPU)"; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts index 7eebb5b4f5e4..9c5cb96beeb1 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts @@ -13,6 +13,7 @@ #include "imx6ul-var-som-concerto-common.dtsi" #include "imx6ul-var-som-sd.dtsi" #include "imx6ul-var-som-enet2.dtsi" +#include "imx6ul-var-som-audio.dtsi" / { model = "Variscite VAR-SOM-6UL Concerto Board (6UL CPU)"; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto-full.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto-full.dts index 86f558c76fb3..2e1f75d5f25a 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto-full.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto-full.dts @@ -13,6 +13,7 @@ #include "imx6ul-var-som-wifi.dtsi" #include "imx6ul-var-som-enet2.dtsi" #include "imx6ul-var-som-enet1.dtsi" +#include "imx6ul-var-som-audio.dtsi" / { model = "Variscite VAR-SOM-6UL Concerto Board (6ULL CPU)"; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto.dts index 0d3e0d9b0f11..43a477db652f 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto.dts @@ -12,6 +12,7 @@ #include "imx6ul-var-som-concerto-common.dtsi" #include "imx6ul-var-som-sd.dtsi" #include "imx6ul-var-som-enet2.dtsi" +#include "imx6ul-var-som-audio.dtsi" / { model = "Variscite VAR-SOM-6UL Concerto Board (6ULL CPU)"; From fe886aec2ef0b05a2e31b3f184fbe85b6aa9743c Mon Sep 17 00:00:00 2001 From: Hugo Villeneuve Date: Thu, 5 Mar 2026 13:06:30 -0500 Subject: [PATCH 14/35] ARM: dts: imx6ul-var-som: add support for LVDS display panel Add support for the LD configuration option (LVDS encoder assembled on SOM) so that the LVDS display panel on the concerto EVK board works properly. Not all VAR-SOM-6UL SOMs have the LD configuration option so factor out this functionality to a separate dtsi. Signed-off-by: Hugo Villeneuve Signed-off-by: Frank Li --- .../imx/imx6ul-var-som-concerto-common.dtsi | 35 ++++-- .../nxp/imx/imx6ul-var-som-concerto-full.dts | 1 + .../dts/nxp/imx/imx6ul-var-som-concerto.dts | 1 + .../nxp/imx/imx6ul-var-som-lvds-panel.dtsi | 112 ++++++++++++++++++ .../nxp/imx/imx6ull-var-som-concerto-full.dts | 1 + .../dts/nxp/imx/imx6ull-var-som-concerto.dts | 1 + 6 files changed, 139 insertions(+), 12 deletions(-) create mode 100644 arch/arm/boot/dts/nxp/imx/imx6ul-var-som-lvds-panel.dtsi diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-common.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-common.dtsi index f099ca5d0e8f..e5637310ba63 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-common.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-common.dtsi @@ -44,6 +44,29 @@ led-0 { linux,default-trigger = "heartbeat"; }; }; + + lvds_panel: lvds-panel { + compatible = "sgd,gktw70sdae4se", "panel-lvds"; + data-mapping = "jeida-18"; + width-mm = <153>; + height-mm = <86>; + + panel-timing { + clock-frequency = <35000000>; + hactive = <800>; + vactive = <480>; + hback-porch = <40>; + hfront-porch = <40>; + vback-porch = <29>; + vfront-porch = <13>; + hsync-len = <48>; + vsync-len = <3>; + hsync-active = <0>; + vsync-active = <0>; + de-active = <1>; + pixelclk-active = <0>; + }; + }; }; &can1 { @@ -98,12 +121,6 @@ MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25 0x1b0b0 /* GPLED2 */ >; }; - pinctrl_pwm4: pwm4grp { - fsl,pins = < - MX6UL_PAD_GPIO1_IO05__PWM4_OUT 0x110b0 - >; - }; - pinctrl_rtc: rtcgrp { fsl,pins = < MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0x1b0b0 /* RTC alarm IRQ */ @@ -139,12 +156,6 @@ MX6UL_PAD_GPIO1_IO01__WDOG1_WDOG_B 0x78b0 }; }; -&pwm4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm4>; - status = "okay"; -}; - &snvs_pwrkey { status = "disabled"; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-full.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-full.dts index 64a3cbd8b7c3..725f34d6b7ee 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-full.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto-full.dts @@ -14,6 +14,7 @@ #include "imx6ul-var-som-enet2.dtsi" #include "imx6ul-var-som-enet1.dtsi" #include "imx6ul-var-som-audio.dtsi" +#include "imx6ul-var-som-lvds-panel.dtsi" / { model = "Variscite VAR-SOM-6UL Concerto Board (6UL CPU)"; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts index 9c5cb96beeb1..c249e15772b8 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-concerto.dts @@ -14,6 +14,7 @@ #include "imx6ul-var-som-sd.dtsi" #include "imx6ul-var-som-enet2.dtsi" #include "imx6ul-var-som-audio.dtsi" +#include "imx6ul-var-som-lvds-panel.dtsi" / { model = "Variscite VAR-SOM-6UL Concerto Board (6UL CPU)"; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-lvds-panel.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-lvds-panel.dtsi new file mode 100644 index 000000000000..996b37d35d6e --- /dev/null +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-var-som-lvds-panel.dtsi @@ -0,0 +1,112 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * LVDS panel support for Variscite VAR-SOM-6UL module. + * + * Copyright 2019-2024 Variscite Ltd. + * Copyright 2026 Dimonoff + */ + +/ { + lcd_backlight: lcd-backlight { + compatible = "pwm-backlight"; + pwms = <&pwm4 0 2000000 0>; + pwm-names = "LCD_BKLT_PWM"; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <6>; + status = "okay"; + }; + + lvds_encoder: lvds-encoder { + compatible = "ti,sn75lvds93", "lvds-encoder"; + power-supply = <®_3p3v>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + lvds_enc_in: endpoint { + remote-endpoint = <&lcdif_out>; + }; + }; + + port@1 { + reg = <1>; + + lvds_enc_out: endpoint { + remote-endpoint = <&lvds_panel_in>; + }; + }; + }; + }; +}; + +&iomuxc { + pinctrl_lcdif_ctrl: lcdif-ctrl-grp { + fsl,pins = < + MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79 + MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79 + >; + }; + + pinctrl_lcdif_dat: lcdif-dat-grp { + fsl,pins = < + MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79 + MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79 + MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79 + MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79 + MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79 + MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79 + MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79 + MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79 + MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79 + MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79 + MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79 + MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79 + MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79 + MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79 + MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79 + MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79 + MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79 + MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79 + >; + }; + + pinctrl_pwm4: pwm4-grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO05__PWM4_OUT 0x110b0 /* LCD BACKLIGHT */ + >; + }; +}; + +&lcdif { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcdif_dat + &pinctrl_lcdif_ctrl>; + status = "okay"; + + port { + lcdif_out: endpoint { + remote-endpoint = <&lvds_enc_in>; + }; + }; +}; + +&lvds_panel { + status = "okay"; + + port { + lvds_panel_in: endpoint { + remote-endpoint = <&lvds_enc_out>; + }; + }; +}; + +/* PWM LCD */ +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto-full.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto-full.dts index 2e1f75d5f25a..1b7c1a3383ee 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto-full.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto-full.dts @@ -14,6 +14,7 @@ #include "imx6ul-var-som-enet2.dtsi" #include "imx6ul-var-som-enet1.dtsi" #include "imx6ul-var-som-audio.dtsi" +#include "imx6ul-var-som-lvds-panel.dtsi" / { model = "Variscite VAR-SOM-6UL Concerto Board (6ULL CPU)"; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto.dts b/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto.dts index 43a477db652f..9c9d16eb1a11 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6ull-var-som-concerto.dts @@ -13,6 +13,7 @@ #include "imx6ul-var-som-sd.dtsi" #include "imx6ul-var-som-enet2.dtsi" #include "imx6ul-var-som-audio.dtsi" +#include "imx6ul-var-som-lvds-panel.dtsi" / { model = "Variscite VAR-SOM-6UL Concerto Board (6ULL CPU)"; From c1315c36141a3310723c443f6ab90a7e41ba60a0 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Fri, 3 Apr 2026 03:46:30 -0400 Subject: [PATCH 15/35] ARM: dts: imx35: remove empty clock-names for nand-controller@bb000000 clock-names is empty in nand-controller@bb000000, which is wrong. Remove it to fix below CHECK_DTBS warings: arch/arm/boot/dts/nxp/imx/imx35-pdk.dtb: nand-controller@bb000000 (fsl,imx35-nand): Unevaluated properties are not allowed ('clock-names' was unexpected) Reviewed-by: Miquel Raynal Signed-off-by: Frank Li --- arch/arm/boot/dts/nxp/imx/imx35.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx35.dtsi b/arch/arm/boot/dts/nxp/imx/imx35.dtsi index 111d7c0331f5..b1e599cb28e7 100644 --- a/arch/arm/boot/dts/nxp/imx/imx35.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx35.dtsi @@ -369,7 +369,6 @@ nfc: nand-controller@bb000000 { compatible = "fsl,imx35-nand", "fsl,imx25-nand"; reg = <0xbb000000 0x2000>; clocks = <&clks 29>; - clock-names = ""; interrupts = <33>; status = "disabled"; }; From 64b4b92f2b1650e8f6a0d142592325af2520695a Mon Sep 17 00:00:00 2001 From: Frank Li Date: Fri, 3 Apr 2026 03:46:31 -0400 Subject: [PATCH 16/35] ARM: dts: imx25: remove empty clock-names for nand-controller@bb000000 clock-names is empty in nand-controller@bb000000, which is wrong. Remove it to fix below CHECK_DTBS warings: arch/arm/boot/dts/nxp/imx/imx25-pdk.dtb: nand-controller@bb000000 (fsl,imx25-nand): Unevaluated properties are not allowed ('clock-names' was unexpected) Reviewed-by: Miquel Raynal Signed-off-by: Frank Li --- arch/arm/boot/dts/nxp/imx/imx25.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx25.dtsi b/arch/arm/boot/dts/nxp/imx/imx25.dtsi index 82601a4b7b4b..189ba3db2e63 100644 --- a/arch/arm/boot/dts/nxp/imx/imx25.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx25.dtsi @@ -618,7 +618,6 @@ nfc: nand-controller@bb000000 { compatible = "fsl,imx25-nand"; reg = <0xbb000000 0x2000>; clocks = <&clks 50>; - clock-names = ""; interrupts = <33>; status = "disabled"; }; From a2407a8a42784f90732351dc9982ec3f6f67a6d8 Mon Sep 17 00:00:00 2001 From: Markus Niebel Date: Thu, 9 Apr 2026 13:10:59 +0200 Subject: [PATCH 17/35] ARM: dts: imx6ul: add #io-channel-cells to ADC Add #io-channel-cells property to the ADC node. This property is required for an IIO consumer driver to work. Signed-off-by: Markus Niebel Signed-off-by: Alexander Stein Signed-off-by: Frank Li --- arch/arm/boot/dts/nxp/imx/imx6ul.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul.dtsi index 6eb80f867f50..a66af8116a06 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul.dtsi @@ -944,6 +944,7 @@ adc1: adc@2198000 { interrupts = ; clocks = <&clks IMX6UL_CLK_ADC1>; clock-names = "adc"; + #io-channel-cells = <1>; fsl,adck-max-frequency = <30000000>, <40000000>, <20000000>; status = "disabled"; From 6570a6354bd35619070bedd71dee027b5ecf6006 Mon Sep 17 00:00:00 2001 From: Eduard Bostina Date: Mon, 23 Mar 2026 19:59:44 +0200 Subject: [PATCH 18/35] dt-bindings: watchdog: Convert TS-4800 to DT schema Convert the Technologic Systems TS-4800 watchdog timer bindings to DT schema. Signed-off-by: Eduard Bostina Reviewed-by: Guenter Roeck Reviewed-by: Krzysztof Kozlowski Signed-off-by: Frank Li --- .../watchdog/technologic,ts4800-wdt.yaml | 40 +++++++++++++++++++ .../bindings/watchdog/ts4800-wdt.txt | 25 ------------ 2 files changed, 40 insertions(+), 25 deletions(-) create mode 100644 Documentation/devicetree/bindings/watchdog/technologic,ts4800-wdt.yaml delete mode 100644 Documentation/devicetree/bindings/watchdog/ts4800-wdt.txt diff --git a/Documentation/devicetree/bindings/watchdog/technologic,ts4800-wdt.yaml b/Documentation/devicetree/bindings/watchdog/technologic,ts4800-wdt.yaml new file mode 100644 index 000000000000..5c2541ac60cf --- /dev/null +++ b/Documentation/devicetree/bindings/watchdog/technologic,ts4800-wdt.yaml @@ -0,0 +1,40 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/watchdog/technologic,ts4800-wdt.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Technologic Systems TS-4800 Watchdog + +maintainers: + - Eduard Bostina + +properties: + compatible: + const: technologic,ts4800-wdt + + syscon: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: Phandle to the FPGA's syscon + - description: Offset to the watchdog register + description: Phandle / integers array that points to the syscon node which + describes the FPGA's syscon registers. + +required: + - compatible + - syscon + +allOf: + - $ref: watchdog.yaml# + +unevaluatedProperties: false + +examples: + - | + watchdog { + compatible = "technologic,ts4800-wdt"; + syscon = <&syscon 0xe>; + timeout-sec = <10>; + }; diff --git a/Documentation/devicetree/bindings/watchdog/ts4800-wdt.txt b/Documentation/devicetree/bindings/watchdog/ts4800-wdt.txt deleted file mode 100644 index 8f6caad4258d..000000000000 --- a/Documentation/devicetree/bindings/watchdog/ts4800-wdt.txt +++ /dev/null @@ -1,25 +0,0 @@ -Technologic Systems Watchdog - -Required properties: -- compatible: must be "technologic,ts4800-wdt" -- syscon: phandle / integer array that points to the syscon node which - describes the FPGA's syscon registers. - - phandle to FPGA's syscon - - offset to the watchdog register - -Optional property: -- timeout-sec: contains the watchdog timeout in seconds. - -Example: - -syscon: syscon@b0010000 { - compatible = "syscon", "simple-mfd"; - reg = <0xb0010000 0x3d>; - reg-io-width = <2>; - - wdt@e { - compatible = "technologic,ts4800-wdt"; - syscon = <&syscon 0xe>; - timeout-sec = <10>; - }; -} From dcf7bac8c2470a61cd457ed2e6f57960004ca392 Mon Sep 17 00:00:00 2001 From: Eduard Bostina Date: Mon, 23 Mar 2026 19:59:45 +0200 Subject: [PATCH 19/35] ARM: dts: nxp: imx51-ts4800: Rename wdt node to watchdog The Technologic Systems TS-4800 watchdog node was previously named 'wdt', which violates the core watchdog.yaml schema expecting generic node names. Rename the node to 'watchdog' to fix the following dtbs_check warning: 'wdt' does not match '^(pmic|timer|watchdog)(@.*|-([0-9]|[1-9][0-9]+))?$' Signed-off-by: Eduard Bostina Reviewed-by: Daniel Baluta Signed-off-by: Frank Li --- arch/arm/boot/dts/nxp/imx/imx51-ts4800.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx51-ts4800.dts b/arch/arm/boot/dts/nxp/imx/imx51-ts4800.dts index 079bd3d14999..4427d178be2c 100644 --- a/arch/arm/boot/dts/nxp/imx/imx51-ts4800.dts +++ b/arch/arm/boot/dts/nxp/imx/imx51-ts4800.dts @@ -155,7 +155,7 @@ syscon: syscon@10000 { reg = <0x10000 0x3d>; reg-io-width = <2>; - wdt { + watchdog { compatible = "technologic,ts4800-wdt"; syscon = <&syscon 0xe>; }; From 9dc39532172cbbc9e4fd5ef4e955b84ed5d96402 Mon Sep 17 00:00:00 2001 From: Sherry Sun Date: Wed, 22 Apr 2026 17:35:42 +0800 Subject: [PATCH 20/35] ARM: dts: imx6qdl: Add Root Port node and PERST property Since describing the PCIe PERST# property under Host Bridge node is now deprecated, it is recommended to add it to the Root Port node, so creating the Root Port node and add the reset-gpios property in Root Port. Signed-off-by: Sherry Sun Signed-off-by: Frank Li --- arch/arm/boot/dts/nxp/imx/imx6q-utilite-pro.dts | 17 ++++------------- arch/arm/boot/dts/nxp/imx/imx6qdl-sabresd.dtsi | 5 +++++ arch/arm/boot/dts/nxp/imx/imx6qdl.dtsi | 11 +++++++++++ arch/arm/boot/dts/nxp/imx/imx6qp-sabreauto.dts | 5 +++++ 4 files changed, 25 insertions(+), 13 deletions(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-utilite-pro.dts b/arch/arm/boot/dts/nxp/imx/imx6q-utilite-pro.dts index c78f101c3cc1..2ddd71f09da3 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6q-utilite-pro.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6q-utilite-pro.dts @@ -323,19 +323,10 @@ &ipu1_di0_disp0 { remote-endpoint = <¶llel_display_in>; }; -&pcie { - pcie@0,0 { - reg = <0x000000 0 0 0 0>; - device_type = "pci"; - #address-cells = <3>; - #size-cells = <2>; - bus-range = <0x00 0xff>; - ranges; - - /* non-removable i211 ethernet card */ - eth1: ethernet@0,0 { - reg = <0x010000 0 0 0 0>; - }; +&pcie_port0 { + /* non-removable i211 ethernet card */ + eth1: ethernet@0,0 { + reg = <0x010000 0 0 0 0>; }; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-sabresd.dtsi index ba29720e3f72..fe9046c03ddd 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-sabresd.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-sabresd.dtsi @@ -754,11 +754,16 @@ lvds0_out: endpoint { &pcie { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pcie>; + /* This property is deprecated, use reset-gpios from the Root Port node. */ reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>; vpcie-supply = <®_pcie>; status = "okay"; }; +&pcie_port0 { + reset-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>; +}; + &pwm1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm1>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl.dtsi index 76e6043e1f91..eeb376193398 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl.dtsi @@ -289,6 +289,17 @@ pcie: pcie@1ffc000 { <&clks IMX6QDL_CLK_PCIE_REF_125M>; clock-names = "pcie", "pcie_bus", "pcie_phy"; status = "disabled"; + + pcie_port0: pcie@0 { + compatible = "pciclass,0604"; + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; aips1: bus@2000000 { /* AIPS1 */ diff --git a/arch/arm/boot/dts/nxp/imx/imx6qp-sabreauto.dts b/arch/arm/boot/dts/nxp/imx/imx6qp-sabreauto.dts index c5b220aeaefd..6b12cab7175f 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qp-sabreauto.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6qp-sabreauto.dts @@ -45,10 +45,15 @@ MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1 }; &pcie { + /* This property is deprecated, use reset-gpios from the Root Port node. */ reset-gpio = <&max7310_c 5 GPIO_ACTIVE_LOW>; status = "okay"; }; +&pcie_port0 { + reset-gpios = <&max7310_c 5 GPIO_ACTIVE_LOW>; +}; + &sata { status = "okay"; }; From f96840444d86b3834f0b1a306d7f8a597fdcabd8 Mon Sep 17 00:00:00 2001 From: Sherry Sun Date: Wed, 22 Apr 2026 17:35:43 +0800 Subject: [PATCH 21/35] ARM: dts: imx6sx: Add Root Port node and PERST property Since describing the PCIe PERST# property under Host Bridge node is now deprecated, it is recommended to add it to the Root Port node, so creating the Root Port node and add the reset-gpios property in Root Port. Signed-off-by: Sherry Sun Signed-off-by: Frank Li --- arch/arm/boot/dts/nxp/imx/imx6sx-sdb.dtsi | 5 +++++ arch/arm/boot/dts/nxp/imx/imx6sx.dtsi | 11 +++++++++++ 2 files changed, 16 insertions(+) diff --git a/arch/arm/boot/dts/nxp/imx/imx6sx-sdb.dtsi b/arch/arm/boot/dts/nxp/imx/imx6sx-sdb.dtsi index 3e238d8118fa..338de4d144b2 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6sx-sdb.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6sx-sdb.dtsi @@ -282,11 +282,16 @@ codec: wm8962@1a { &pcie { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pcie>; + /* This property is deprecated, use reset-gpios from the Root Port node. */ reset-gpio = <&gpio2 0 GPIO_ACTIVE_LOW>; vpcie-supply = <®_pcie_gpio>; status = "okay"; }; +&pcie_port0 { + reset-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; +}; + &lcdif1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_lcd>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6sx.dtsi b/arch/arm/boot/dts/nxp/imx/imx6sx.dtsi index 1426f357d474..d42363cb5105 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6sx.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6sx.dtsi @@ -1470,6 +1470,17 @@ pcie: pcie@8ffc000 { power-domains = <&pd_disp>, <&pd_pci>; power-domain-names = "pcie", "pcie_phy"; status = "disabled"; + + pcie_port0: pcie@0 { + compatible = "pciclass,0604"; + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; }; }; From 01f13c165d1c43b1c941875bfade26a279121829 Mon Sep 17 00:00:00 2001 From: Sherry Sun Date: Wed, 22 Apr 2026 17:35:44 +0800 Subject: [PATCH 22/35] ARM: dts: imx7d: Add Root Port node and PERST property Since describing the PCIe PERST# property under Host Bridge node is now deprecated, it is recommended to add it to the Root Port node, so creating the Root Port node and add the reset-gpios property in Root Port. Signed-off-by: Sherry Sun Signed-off-by: Frank Li --- arch/arm/boot/dts/nxp/imx/imx7d-sdb.dts | 5 +++++ arch/arm/boot/dts/nxp/imx/imx7d.dtsi | 11 +++++++++++ 2 files changed, 16 insertions(+) diff --git a/arch/arm/boot/dts/nxp/imx/imx7d-sdb.dts b/arch/arm/boot/dts/nxp/imx/imx7d-sdb.dts index a370e868cafe..0046b276b8b9 100644 --- a/arch/arm/boot/dts/nxp/imx/imx7d-sdb.dts +++ b/arch/arm/boot/dts/nxp/imx/imx7d-sdb.dts @@ -456,10 +456,15 @@ display_out: endpoint { }; &pcie { + /* This property is deprecated, use reset-gpios from the Root Port node. */ reset-gpio = <&extended_io 1 GPIO_ACTIVE_LOW>; status = "okay"; }; +&pcie_port0 { + reset-gpios = <&extended_io 1 GPIO_ACTIVE_LOW>; +}; + ®_1p0d { vin-supply = <&sw2_reg>; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx7d.dtsi b/arch/arm/boot/dts/nxp/imx/imx7d.dtsi index d961c61a93af..3c5c1f2c1460 100644 --- a/arch/arm/boot/dts/nxp/imx/imx7d.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx7d.dtsi @@ -155,6 +155,17 @@ pcie: pcie@33800000 { reset-names = "pciephy", "apps", "turnoff"; fsl,imx7d-pcie-phy = <&pcie_phy>; status = "disabled"; + + pcie_port0: pcie@0 { + compatible = "pciclass,0604"; + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; }; }; From a767ab8ae66e574c6427ab88f55e9e43471edb4e Mon Sep 17 00:00:00 2001 From: Frank Li Date: Mon, 11 May 2026 17:04:57 -0400 Subject: [PATCH 23/35] ARM: dts: imx: add ti,deskew = <0> for ti,tfp410 Add required proprety ti,deskew for ti,tfp410, which have not defined default value in yaml. 0 is default value according to drivers/gpu/drm/bridge/ti-tfp410.c. Fix below check_dtbs warning: dvi-encoder (ti,tfp410): 'ti,deskew' is a required property Signed-off-by: Frank Li --- arch/arm/boot/dts/nxp/imx/imx51-babbage.dts | 1 + arch/arm/boot/dts/nxp/imx/imx53-cx9020.dts | 1 + arch/arm/boot/dts/nxp/imx/imx6q-utilite-pro.dts | 1 + 3 files changed, 3 insertions(+) diff --git a/arch/arm/boot/dts/nxp/imx/imx51-babbage.dts b/arch/arm/boot/dts/nxp/imx/imx51-babbage.dts index 1b6ec55f9068..6129795947d3 100644 --- a/arch/arm/boot/dts/nxp/imx/imx51-babbage.dts +++ b/arch/arm/boot/dts/nxp/imx/imx51-babbage.dts @@ -126,6 +126,7 @@ dvi_connector_in: endpoint { dvi-encoder { compatible = "ti,tfp410"; + ti,deskew = <0>; ports { #address-cells = <1>; diff --git a/arch/arm/boot/dts/nxp/imx/imx53-cx9020.dts b/arch/arm/boot/dts/nxp/imx/imx53-cx9020.dts index 0814f5665a59..02be8b6da696 100644 --- a/arch/arm/boot/dts/nxp/imx/imx53-cx9020.dts +++ b/arch/arm/boot/dts/nxp/imx/imx53-cx9020.dts @@ -60,6 +60,7 @@ dvi_connector_in: endpoint { dvi-converter { compatible = "ti,tfp410"; + ti,deskew = <0>; ports { #address-cells = <1>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-utilite-pro.dts b/arch/arm/boot/dts/nxp/imx/imx6q-utilite-pro.dts index 2ddd71f09da3..c69052d776e3 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6q-utilite-pro.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6q-utilite-pro.dts @@ -61,6 +61,7 @@ aliases { encoder { compatible = "ti,tfp410"; + ti,deskew = <0>; ports { #address-cells = <1>; From d6af25d182b2ece6223dbba0084b269526d3a5ae Mon Sep 17 00:00:00 2001 From: Frank Li Date: Mon, 11 May 2026 17:04:58 -0400 Subject: [PATCH 24/35] ARM: dts: imx53-qsb: add dvdd and avdd supply for panel sii,43wvf1g Add dvdd and avdd supply and regulators for panel sii,43wvf1g to fix below check_dtbs warnings: panel (sii,43wvf1g): 'dvdd-supply' is a required property Signed-off-by: Frank Li --- arch/arm/boot/dts/nxp/imx/imx53-qsb-common.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/nxp/imx/imx53-qsb-common.dtsi b/arch/arm/boot/dts/nxp/imx/imx53-qsb-common.dtsi index 1869ad86baf2..d3b27dc3c2c7 100644 --- a/arch/arm/boot/dts/nxp/imx/imx53-qsb-common.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx53-qsb-common.dtsi @@ -91,6 +91,8 @@ panel_dpi: panel { pinctrl-0 = <&pinctrl_display_power>; backlight = <&backlight_parallel>; enable-gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>; + dvdd-supply = <®_3p2v>; + avdd-supply = <®_5v>; port { panel_in: endpoint { @@ -107,6 +109,14 @@ reg_3p2v: regulator-3p2v { regulator-always-on; }; + reg_5v: regulator-5v { + compatible = "regulator-fixed"; + regulator-name = "5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + reg_usb_vbus: regulator-usb-vbus { compatible = "regulator-fixed"; regulator-name = "usb_vbus"; From 740e76b89b1cd75f519a949b77954ff9cf71c82f Mon Sep 17 00:00:00 2001 From: Frank Li Date: Mon, 11 May 2026 17:04:59 -0400 Subject: [PATCH 25/35] ARM: dts: imx53-ppd: add '#phy-cells' for usb-nop-xceiv Add '#phy-cells' for usb-nop-xceiv to fix below check_dtbs warnings: usbphy-2 (usb-nop-xceiv): '#phy-cells' is a required property Signed-off-by: Frank Li --- arch/arm/boot/dts/nxp/imx/imx53-ppd.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/nxp/imx/imx53-ppd.dts b/arch/arm/boot/dts/nxp/imx/imx53-ppd.dts index e45a97d3f449..f0fb88c14171 100644 --- a/arch/arm/boot/dts/nxp/imx/imx53-ppd.dts +++ b/arch/arm/boot/dts/nxp/imx/imx53-ppd.dts @@ -258,6 +258,7 @@ usbphy2: usbphy-2 { clock-names = "main_clk"; clock-frequency = <24000000>; clocks = <&clks IMX5_CLK_CKO2>; + #phy-cells = <0>; assigned-clocks = <&clks IMX5_CLK_CKO2_SEL>, <&clks IMX5_CLK_OSC>; assigned-clock-parents = <&clks IMX5_CLK_OSC>; }; @@ -270,6 +271,7 @@ usbphy3: usbphy-3 { clock-frequency = <24000000>; clocks = <&clks IMX5_CLK_CKO2>; + #phy-cells = <0>; assigned-clocks = <&clks IMX5_CLK_CKO2_SEL>, <&clks IMX5_CLK_OSC>; assigned-clock-parents = <&clks IMX5_CLK_OSC>; }; From 85125c5e9a74054e8f3e3c8910a517e34ad53ae1 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Thu, 21 May 2026 15:15:39 -0400 Subject: [PATCH 26/35] ARM: dts: imx: add (power|vdd)-supply for related node Add required power-supply and vdd-supply properties to fix below CHECK_DTB warnings: arch/arm/boot/dts/nxp/imx/imx53-m53menlo.dtb: panel (edt,etm0700g0dh6): 'power-supply' is a required property Signed-off-by: Frank Li --- arch/arm/boot/dts/nxp/imx/imx53-m53menlo.dts | 9 +++++++++ arch/arm/boot/dts/nxp/imx/imx53-sk-imx53-atm0700d4.dtsi | 1 + arch/arm/boot/dts/nxp/imx/imx53-sk-imx53.dts | 7 +++++++ arch/arm/boot/dts/nxp/imx/imx6q-novena.dts | 1 + 4 files changed, 18 insertions(+) diff --git a/arch/arm/boot/dts/nxp/imx/imx53-m53menlo.dts b/arch/arm/boot/dts/nxp/imx/imx53-m53menlo.dts index 6210673f93be..2acbc86cabb3 100644 --- a/arch/arm/boot/dts/nxp/imx/imx53-m53menlo.dts +++ b/arch/arm/boot/dts/nxp/imx/imx53-m53menlo.dts @@ -84,6 +84,7 @@ panel { pinctrl-0 = <&pinctrl_display_gpio>; pinctrl-names = "default"; enable-gpios = <&gpio6 0 GPIO_ACTIVE_HIGH>; + power-supply = <®_3p2v>; port { panel_in: endpoint { @@ -98,6 +99,13 @@ beeper { gpios = <&gpio6 3 GPIO_ACTIVE_HIGH>; }; + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + reg_usbh1_vbus: regulator-usbh1-vbus { compatible = "regulator-fixed"; regulator-name = "vbus"; @@ -259,6 +267,7 @@ eeprom@50 { dac@60 { compatible = "microchip,mcp4725"; reg = <0x60>; + vdd-supply = <®_3v3>; }; }; diff --git a/arch/arm/boot/dts/nxp/imx/imx53-sk-imx53-atm0700d4.dtsi b/arch/arm/boot/dts/nxp/imx/imx53-sk-imx53-atm0700d4.dtsi index e395004e80e6..34cb0c344ff6 100644 --- a/arch/arm/boot/dts/nxp/imx/imx53-sk-imx53-atm0700d4.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx53-sk-imx53-atm0700d4.dtsi @@ -10,6 +10,7 @@ / { panel: panel-rgb { compatible = "powertip,ph800480t013-idf02"; + power-supply = <®_5v>; port { panel_rgb_in: endpoint { diff --git a/arch/arm/boot/dts/nxp/imx/imx53-sk-imx53.dts b/arch/arm/boot/dts/nxp/imx/imx53-sk-imx53.dts index 1a00d290092a..ebec88495877 100644 --- a/arch/arm/boot/dts/nxp/imx/imx53-sk-imx53.dts +++ b/arch/arm/boot/dts/nxp/imx/imx53-sk-imx53.dts @@ -29,6 +29,13 @@ memory@70000000 { reg = <0x70000000 0x20000000>; }; + reg_5v: regulator-5v { + compatible = "regulator-fixed"; + regulator-name = "5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + reg_usb1_vbus: regulator-usb-vbus { compatible = "regulator-fixed"; regulator-name = "usb_vbus"; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-novena.dts b/arch/arm/boot/dts/nxp/imx/imx6q-novena.dts index 24fc3ff1c70c..cd9a050fa906 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6q-novena.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6q-novena.dts @@ -109,6 +109,7 @@ led-heartbeat { panel: panel { compatible = "innolux,n133hse-ea1"; backlight = <&backlight>; + power-supply = <®_lvds_lcd>; }; reg_2p5v: regulator-2p5v { From e1867c85f420271294ccf75d001e1992805b0116 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Thu, 21 May 2026 15:15:40 -0400 Subject: [PATCH 27/35] ARM: dts: imx: remove redundant bus-width for video-mux Remove redundant bus-width property according to video-mux.yaml to fix below CHECK_DTBS warnings: arch/arm/boot/dts/nxp/imx/imx6dl-gw51xx.dtb: ipu1_csi0_mux (video-mux): port@4:endpoint: Unevaluated properties are not allowed ('bus-width' was unexpected) from schema $id: http://devicetree.org/schemas/media/video-mux.yaml The bus-width already set at remote endpoint (camera). Signed-off-by: Frank Li --- arch/arm/boot/dts/nxp/imx/imx6dl-gw52xx.dts | 2 -- arch/arm/boot/dts/nxp/imx/imx6dl-gw53xx.dts | 2 -- arch/arm/boot/dts/nxp/imx/imx6dl-gw54xx.dts | 2 -- arch/arm/boot/dts/nxp/imx/imx6q-gw52xx.dts | 2 -- arch/arm/boot/dts/nxp/imx/imx6q-gw53xx.dts | 2 -- arch/arm/boot/dts/nxp/imx/imx6q-gw54xx.dts | 4 ---- arch/arm/boot/dts/nxp/imx/imx6qdl-gw51xx.dtsi | 2 -- arch/arm/boot/dts/nxp/imx/imx6qdl-gw551x.dtsi | 2 -- arch/arm/boot/dts/nxp/imx/imx6qdl-gw553x.dtsi | 2 -- arch/arm/boot/dts/nxp/imx/imx6qdl-sabreauto.dtsi | 2 -- 10 files changed, 22 deletions(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-gw52xx.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-gw52xx.dts index 9ea23dd54f3c..62b05fe70cd9 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6dl-gw52xx.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-gw52xx.dts @@ -32,12 +32,10 @@ adv7180_to_ipu1_csi1_mux: endpoint { }; &ipu1_csi1_from_ipu1_csi1_mux { - bus-width = <8>; }; &ipu1_csi1_mux_from_parallel_sensor { remote-endpoint = <&adv7180_to_ipu1_csi1_mux>; - bus-width = <8>; }; &ipu1_csi1 { diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-gw53xx.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-gw53xx.dts index 182e8194c249..c1787510d394 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6dl-gw53xx.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-gw53xx.dts @@ -32,12 +32,10 @@ adv7180_to_ipu1_csi1_mux: endpoint { }; &ipu1_csi1_from_ipu1_csi1_mux { - bus-width = <8>; }; &ipu1_csi1_mux_from_parallel_sensor { remote-endpoint = <&adv7180_to_ipu1_csi1_mux>; - bus-width = <8>; }; &ipu1_csi1 { diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-gw54xx.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-gw54xx.dts index a106c4e3e329..934b0325e6f5 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6dl-gw54xx.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-gw54xx.dts @@ -32,12 +32,10 @@ adv7180_to_ipu1_csi1_mux: endpoint { }; &ipu1_csi1_from_ipu1_csi1_mux { - bus-width = <8>; }; &ipu1_csi1_mux_from_parallel_sensor { remote-endpoint = <&adv7180_to_ipu1_csi1_mux>; - bus-width = <8>; }; &ipu1_csi1 { diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-gw52xx.dts b/arch/arm/boot/dts/nxp/imx/imx6q-gw52xx.dts index 6e1c493c9c8c..31996ddde117 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6q-gw52xx.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6q-gw52xx.dts @@ -32,12 +32,10 @@ adv7180_to_ipu2_csi1_mux: endpoint { }; &ipu2_csi1_from_ipu2_csi1_mux { - bus-width = <8>; }; &ipu2_csi1_mux_from_parallel_sensor { remote-endpoint = <&adv7180_to_ipu2_csi1_mux>; - bus-width = <8>; }; &ipu2_csi1 { diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-gw53xx.dts b/arch/arm/boot/dts/nxp/imx/imx6q-gw53xx.dts index f13df8e9c8c4..f224273fa863 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6q-gw53xx.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6q-gw53xx.dts @@ -32,12 +32,10 @@ adv7180_to_ipu2_csi1_mux: endpoint { }; &ipu2_csi1_from_ipu2_csi1_mux { - bus-width = <8>; }; &ipu2_csi1_mux_from_parallel_sensor { remote-endpoint = <&adv7180_to_ipu2_csi1_mux>; - bus-width = <8>; }; &ipu2_csi1 { diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-gw54xx.dts b/arch/arm/boot/dts/nxp/imx/imx6q-gw54xx.dts index d5d46908cf6e..804ee044be52 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6q-gw54xx.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6q-gw54xx.dts @@ -90,12 +90,10 @@ tda1997x_to_ipu1_csi0_mux: endpoint { }; &ipu1_csi0_from_ipu1_csi0_mux { - bus-width = <16>; }; &ipu1_csi0_mux_from_parallel_sensor { remote-endpoint = <&tda1997x_to_ipu1_csi0_mux>; - bus-width = <16>; }; &ipu1_csi0 { @@ -104,12 +102,10 @@ &ipu1_csi0 { }; &ipu2_csi1_from_ipu2_csi1_mux { - bus-width = <8>; }; &ipu2_csi1_mux_from_parallel_sensor { remote-endpoint = <&adv7180_to_ipu2_csi1_mux>; - bus-width = <8>; }; &ipu2_csi1 { diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw51xx.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw51xx.dtsi index beff5a0f58ab..fb18b87adb44 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw51xx.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw51xx.dtsi @@ -384,12 +384,10 @@ adv7180_to_ipu1_csi0_mux: endpoint { }; &ipu1_csi0_from_ipu1_csi0_mux { - bus-width = <8>; }; &ipu1_csi0_mux_from_parallel_sensor { remote-endpoint = <&adv7180_to_ipu1_csi0_mux>; - bus-width = <8>; }; &ipu1_csi0 { diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw551x.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw551x.dtsi index 6136a95b9259..55647c1dacfa 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw551x.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw551x.dtsi @@ -440,12 +440,10 @@ tda1997x_to_ipu1_csi0_mux: endpoint { }; &ipu1_csi0_from_ipu1_csi0_mux { - bus-width = <16>; }; &ipu1_csi0_mux_from_parallel_sensor { remote-endpoint = <&tda1997x_to_ipu1_csi0_mux>; - bus-width = <16>; }; &ipu1_csi0 { diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw553x.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw553x.dtsi index 552114a69f5b..bdbcad5e35d8 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-gw553x.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-gw553x.dtsi @@ -397,12 +397,10 @@ adv7180_to_ipu1_csi0_mux: endpoint { }; &ipu1_csi0_from_ipu1_csi0_mux { - bus-width = <8>; }; &ipu1_csi0_mux_from_parallel_sensor { remote-endpoint = <&adv7180_to_ipu1_csi0_mux>; - bus-width = <8>; }; &ipu1_csi0 { diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-sabreauto.dtsi index b9dde0af3b99..40d8887cb8bc 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-sabreauto.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-sabreauto.dtsi @@ -245,12 +245,10 @@ accelerometer@1c { }; &ipu1_csi0_from_ipu1_csi0_mux { - bus-width = <8>; }; &ipu1_csi0_mux_from_parallel_sensor { remote-endpoint = <&adv7180_to_ipu1_csi0_mux>; - bus-width = <8>; }; &ipu1_csi0 { From 202f97ae137bc6e08d2ed685e361c413edc8452a Mon Sep 17 00:00:00 2001 From: Frank Li Date: Thu, 21 May 2026 15:15:41 -0400 Subject: [PATCH 28/35] ARM: dts: imx: Add bus-type for ov5642/ov5640 Add bus-type (MEDIA_BUS_TYPE_PARALLEL) for ov5642/ov5640. i.MX53 and i.MX6UL only supports parallel csi interface. Fix below CHECK_DTBS warnings: arm/boot/dts/nxp/imx/imx53-smd.dtb: ov5642@3c (ovti,ov5642): port:endpoint: 'bus-type' is a required property Signed-off-by: Frank Li --- arch/arm/boot/dts/nxp/imx/imx53-smd.dts | 2 ++ arch/arm/boot/dts/nxp/imx/imx6ul-14x14-evk.dtsi | 1 + 2 files changed, 3 insertions(+) diff --git a/arch/arm/boot/dts/nxp/imx/imx53-smd.dts b/arch/arm/boot/dts/nxp/imx/imx53-smd.dts index 386371c816f4..c4255da157a3 100644 --- a/arch/arm/boot/dts/nxp/imx/imx53-smd.dts +++ b/arch/arm/boot/dts/nxp/imx/imx53-smd.dts @@ -5,6 +5,7 @@ /dts-v1/; #include +#include #include "imx53.dtsi" / { @@ -296,6 +297,7 @@ camera: ov5642@3c { port { ov5642_to_ipu_csi0: endpoint { remote-endpoint = <&ipu_csi0_from_parallel_sensor>; + bus-type = ; bus-width = <8>; hsync-active = <1>; vsync-active = <1>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-14x14-evk.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-14x14-evk.dtsi index 3d147b160ecf..32afe4130e21 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-14x14-evk.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-14x14-evk.dtsi @@ -217,6 +217,7 @@ camera@3c { port { ov5640_to_parallel: endpoint { remote-endpoint = <¶llel_from_ov5640>; + bus-type = ; bus-width = <8>; data-shift = <2>; /* lines 9:2 are used */ hsync-active = <0>; From 92c200493e1b70faf810b683fc7046d3b1738b15 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Thu, 21 May 2026 15:15:42 -0400 Subject: [PATCH 29/35] ARM: dts: imx6qdl-tx6: remove undocumented karo,imx6qdl-tx6-sgtl5000 and keep only simple-audio-card Remove the undocumented and unused compatible karo,imx6qdl-tx6-sgtl5000 and retain only the generic simple-audio-card sound configuration. The karo,imx6qdl-tx6-sgtl5000 compatible is not documented and is not referenced by any in-kernel driver. The audio setup is already fully described using simple-audio-card, which is the standard and supported binding for this hardware configuration. No known users (such as uboot) rely on karo,imx6qdl-tx6-sgtl5000. Fix below CHECK_DTBS warnings: arch/arm/boot/dts/nxp/imx/imx6dl-tx6dl-comtft.dtb: /sound: failed to match any schema with compatible: ['karo,imx6qdl-tx6-sgtl5000', 'simple-audio-card'] Signed-off-by: Frank Li --- arch/arm/boot/dts/nxp/imx/imx6qdl-tx6.dtsi | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-tx6.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-tx6.dtsi index d29adfef5fdb..18c29f46dac6 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-tx6.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-tx6.dtsi @@ -148,8 +148,7 @@ reg_usbotg_vbus: regulator-usbotg-vbus { }; sound { - compatible = "karo,imx6qdl-tx6-sgtl5000", - "simple-audio-card"; + compatible = "simple-audio-card"; simple-audio-card,name = "imx6qdl-tx6-sgtl5000-audio"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_audmux>; From 256807f42282e4d7d672784c4eacf6ca768920b4 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Thu, 21 May 2026 15:15:43 -0400 Subject: [PATCH 30/35] ARM: dts: imx: replace undocumented compatible string edt,edt-ft5x06 with edt,edt-ft5206 The edt,edt-ft5x06 compatible is not referenced in drivers/input/touchscreen/edt-ft5x06.c and is not documented. There is no publicly available datasheet or binding information that distinguishes edt-ft5206/ft5306/ft5406 variants and the driver treats these FT5x06-family controllers with the same configuration model. So switch to the lowest common and documented baseline compatible edt,edt-ft5206. Fix below CHECK_DTBS warnings: arch/arm/boot/dts/nxp/imx/imx53-m53menlo.dtb: /soc/bus@60000000/i2c@63fc8000/touchscreen@38: failed to match any schema with compatible: ['edt,edt-ft5x06'] ABI impact consideration: Not affect Linux kernel. The I2C subsystem uses a legacy fallback mechanism where it strips the vendor prefix from the compatible string to derive the client name, resulting in edt-ft5x06 { .name = "edt-ft5x06", .driver_data = (long)&edt_ft5x06_data }, After this, the driver was actively binding to these devices based on the compatible string. Known user (U-Boot) does not parse or use edt,edt-ft* touchscreen compatibles. Signed-off-by: Frank Li --- arch/arm/boot/dts/nxp/imx/imx53-m53menlo.dts | 2 +- arch/arm/boot/dts/nxp/imx/imx53-tx53-x03x.dts | 2 +- arch/arm/boot/dts/nxp/imx/imx6q-var-dt6customboard.dts | 2 +- arch/arm/boot/dts/nxp/imx/imx6qdl-nit6xlite.dtsi | 2 +- arch/arm/boot/dts/nxp/imx/imx6qdl-nitrogen6_max.dtsi | 2 +- arch/arm/boot/dts/nxp/imx/imx6qdl-nitrogen6_som2.dtsi | 2 +- arch/arm/boot/dts/nxp/imx/imx6qdl-nitrogen6x.dtsi | 2 +- arch/arm/boot/dts/nxp/imx/imx6qdl-pico.dtsi | 2 +- arch/arm/boot/dts/nxp/imx/imx6qdl-tx6.dtsi | 2 +- arch/arm/boot/dts/nxp/imx/imx6ul-pico-hobbit.dts | 2 +- arch/arm/boot/dts/nxp/imx/imx6ul-pico-pi.dts | 2 +- arch/arm/boot/dts/nxp/imx/imx6ul-tx6ul.dtsi | 2 +- arch/arm/boot/dts/nxp/imx/imx7d-pico-dwarf.dts | 2 +- arch/arm/boot/dts/nxp/imx/imx7d-pico-pi.dts | 2 +- 14 files changed, 14 insertions(+), 14 deletions(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx53-m53menlo.dts b/arch/arm/boot/dts/nxp/imx/imx53-m53menlo.dts index 2acbc86cabb3..aa1c7e5012c6 100644 --- a/arch/arm/boot/dts/nxp/imx/imx53-m53menlo.dts +++ b/arch/arm/boot/dts/nxp/imx/imx53-m53menlo.dts @@ -248,7 +248,7 @@ &i2c1 { status = "okay"; touchscreen@38 { - compatible = "edt,edt-ft5x06"; + compatible = "edt,edt-ft5206"; reg = <0x38>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_edt_ft5x06>; diff --git a/arch/arm/boot/dts/nxp/imx/imx53-tx53-x03x.dts b/arch/arm/boot/dts/nxp/imx/imx53-tx53-x03x.dts index 872cf7e16f20..6a1063c455f0 100644 --- a/arch/arm/boot/dts/nxp/imx/imx53-tx53-x03x.dts +++ b/arch/arm/boot/dts/nxp/imx/imx53-tx53-x03x.dts @@ -201,7 +201,7 @@ sgtl5000: codec@a { }; polytouch: edt-ft5x06@38 { - compatible = "edt,edt-ft5x06"; + compatible = "edt,edt-ft5206"; reg = <0x38>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_edt_ft5x06_1>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-var-dt6customboard.dts b/arch/arm/boot/dts/nxp/imx/imx6q-var-dt6customboard.dts index 0225a621ec7a..ccf6a048c918 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6q-var-dt6customboard.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6q-var-dt6customboard.dts @@ -169,7 +169,7 @@ &i2c3 { status = "okay"; touchscreen@38 { - compatible = "edt,edt-ft5x06"; + compatible = "edt,edt-ft5206"; reg = <0x38>; interrupt-parent = <&gpio1>; interrupts = <4 IRQ_TYPE_EDGE_FALLING>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-nit6xlite.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-nit6xlite.dtsi index 610b2a72fe82..cebfd622df68 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-nit6xlite.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-nit6xlite.dtsi @@ -256,7 +256,7 @@ touchscreen@4 { }; touchscreen@38 { - compatible = "edt,edt-ft5x06"; + compatible = "edt,edt-ft5206"; reg = <0x38>; interrupt-parent = <&gpio1>; interrupts = <9 IRQ_TYPE_EDGE_FALLING>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-nitrogen6_max.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-nitrogen6_max.dtsi index ef0c26688446..f8a7218b13ef 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-nitrogen6_max.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-nitrogen6_max.dtsi @@ -405,7 +405,7 @@ touchscreen@4 { }; touchscreen@38 { - compatible = "edt,edt-ft5x06"; + compatible = "edt,edt-ft5206"; reg = <0x38>; interrupt-parent = <&gpio1>; interrupts = <9 IRQ_TYPE_EDGE_FALLING>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-nitrogen6_som2.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-nitrogen6_som2.dtsi index 03fe053880ca..fb1c923c46bc 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-nitrogen6_som2.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-nitrogen6_som2.dtsi @@ -326,7 +326,7 @@ touchscreen@4 { }; touchscreen@38 { - compatible = "edt,edt-ft5x06"; + compatible = "edt,edt-ft5206"; reg = <0x38>; interrupt-parent = <&gpio1>; interrupts = <9 IRQ_TYPE_EDGE_FALLING>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-nitrogen6x.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-nitrogen6x.dtsi index 6a353a99e13d..9fe52e0ca7aa 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-nitrogen6x.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-nitrogen6x.dtsi @@ -333,7 +333,7 @@ touchscreen@4 { }; touchscreen@38 { - compatible = "edt,edt-ft5x06"; + compatible = "edt,edt-ft5206"; reg = <0x38>; interrupt-parent = <&gpio1>; interrupts = <9 IRQ_TYPE_EDGE_FALLING>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-pico.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-pico.dtsi index c39a9ebdaba1..ca4cb986efbc 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-pico.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-pico.dtsi @@ -217,7 +217,7 @@ &i2c2 { status = "okay"; touchscreen@38 { - compatible = "edt,edt-ft5x06"; + compatible = "edt,edt-ft5206"; reg = <0x38>; interrupt-parent = <&gpio5>; interrupts = <31 IRQ_TYPE_EDGE_FALLING>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-tx6.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-tx6.dtsi index 18c29f46dac6..83c4bf9f9438 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6qdl-tx6.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-tx6.dtsi @@ -296,7 +296,7 @@ sgtl5000: sgtl5000@a { }; polytouch: edt-ft5x06@38 { - compatible = "edt,edt-ft5x06"; + compatible = "edt,edt-ft5206"; reg = <0x38>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_edt_ft5x06>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-pico-hobbit.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-pico-hobbit.dts index bf7dbb4f1f3e..e99ba04216b8 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-pico-hobbit.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-pico-hobbit.dts @@ -62,7 +62,7 @@ &i2c3 { status = "okay"; polytouch: touchscreen@38 { - compatible = "edt,edt-ft5x06"; + compatible = "edt,edt-ft5206"; reg = <0x38>; interrupt-parent = <&gpio1>; interrupts = <29 IRQ_TYPE_EDGE_FALLING>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-pico-pi.dts b/arch/arm/boot/dts/nxp/imx/imx6ul-pico-pi.dts index 6cfc943a8fa3..f79090fb2e6e 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-pico-pi.dts +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-pico-pi.dts @@ -65,7 +65,7 @@ &i2c3 { status = "okay"; polytouch: touchscreen@38 { - compatible = "edt,edt-ft5x06"; + compatible = "edt,edt-ft5206"; reg = <0x38>; interrupt-parent = <&gpio1>; interrupts = <29 IRQ_TYPE_EDGE_FALLING>; diff --git a/arch/arm/boot/dts/nxp/imx/imx6ul-tx6ul.dtsi b/arch/arm/boot/dts/nxp/imx/imx6ul-tx6ul.dtsi index dc53f9286ffe..b87f5d6a2d88 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6ul-tx6ul.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6ul-tx6ul.dtsi @@ -321,7 +321,7 @@ sgtl5000: codec@a { }; polytouch: polytouch@38 { - compatible = "edt,edt-ft5x06"; + compatible = "edt,edt-ft5206"; reg = <0x38>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_edt_ft5x06>; diff --git a/arch/arm/boot/dts/nxp/imx/imx7d-pico-dwarf.dts b/arch/arm/boot/dts/nxp/imx/imx7d-pico-dwarf.dts index 347dd0fe4f82..fca8aab9d850 100644 --- a/arch/arm/boot/dts/nxp/imx/imx7d-pico-dwarf.dts +++ b/arch/arm/boot/dts/nxp/imx/imx7d-pico-dwarf.dts @@ -70,7 +70,7 @@ pca9554: io-expander@25 { }; touchscreen@38 { - compatible = "edt,edt-ft5x06"; + compatible = "edt,edt-ft5206"; reg = <0x38>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_touchscreen>; diff --git a/arch/arm/boot/dts/nxp/imx/imx7d-pico-pi.dts b/arch/arm/boot/dts/nxp/imx/imx7d-pico-pi.dts index 62221131336f..673bbe49de52 100644 --- a/arch/arm/boot/dts/nxp/imx/imx7d-pico-pi.dts +++ b/arch/arm/boot/dts/nxp/imx/imx7d-pico-pi.dts @@ -49,7 +49,7 @@ sgtl5000: codec@a { &i2c4 { polytouch: touchscreen@38 { - compatible = "edt,edt-ft5x06"; + compatible = "edt,edt-ft5206"; reg = <0x38>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_touchscreen>; From e6532261b1514d99cfa07db05c1fafaf32ffbfb2 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Thu, 21 May 2026 15:15:44 -0400 Subject: [PATCH 31/35] ARM: dts: imx6-display5: replace marvell,88E1510 with ethernet-phy-ieee802.3-c22 Replace the vendor-specific PHY compatible string with the generic ethernet-phy-ieee802.3-c22 compatible. The marvell,88E1510 compatible is listed in whitelist_phys[] and is never matched against a PHY driver. PHY devices are expected to use the generic ethernet-phy-ieee802.3-c22 compatible unless a specific MDIO driver match is required. The 88E1510 is compatible with Clause 22 PHY devices, so use the generic compatible string instead. Fix below CHECK_DTBS warnings: arch/arm/boot/dts/nxp/imx/imx6q-display5-tianma-tm070-1280x768.dtb: /soc/bus@2100000/ethernet@2188000/mdio/ethernet-phy@0: failed to match any schema with compatible: ['marvell,88E1510'] Known other user (uboot) did not use marvell,88E1510. Signed-off-by: Frank Li --- arch/arm/boot/dts/nxp/imx/imx6q-display5.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-display5.dtsi b/arch/arm/boot/dts/nxp/imx/imx6q-display5.dtsi index 4e448b4810f2..21e8bbdab4e6 100644 --- a/arch/arm/boot/dts/nxp/imx/imx6q-display5.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx6q-display5.dtsi @@ -208,7 +208,7 @@ mdio { #address-cells = <1>; #size-cells = <0>; ethernet_phy0: ethernet-phy@0 { - compatible = "marvell,88E1510"; + compatible = "ethernet-phy-ieee802.3-c22"; device_type = "ethernet-phy"; /* Set LED0 control: */ /* On - Link, Blink - Activity, Off - No Link */ From 1e2aa1b07bc1c5dd89ec0d14d9fe6f32f9b136c4 Mon Sep 17 00:00:00 2001 From: Lech Perczak Date: Wed, 27 May 2026 12:19:12 +0200 Subject: [PATCH 32/35] ARM: dts: imx7d-pico-pi: add OV5645 camera support Add OV5645 camera device node and enable relevant components in the video capture data path, so output stream can be captured, and the camera itself can be controlled over I2C bus. This is roughly based on descriptions found in downstream kernel tree [1], adapted to match upstream bindings. Link: https://github.com/technexion-android/kernel_imx/blob/ce8fd74abf518dac0a09e8dcb37f3496f6375124/arch/arm/boot/dts/imx7d-pico.dtsi#L874 [1] Signed-off-by: Lech Perczak Signed-off-by: Frank Li --- arch/arm/boot/dts/nxp/imx/imx7d-pico-pi.dts | 68 ++++++++++++++++++++- 1 file changed, 67 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/nxp/imx/imx7d-pico-pi.dts b/arch/arm/boot/dts/nxp/imx/imx7d-pico-pi.dts index 673bbe49de52..7a0e4dc5450e 100644 --- a/arch/arm/boot/dts/nxp/imx/imx7d-pico-pi.dts +++ b/arch/arm/boot/dts/nxp/imx/imx7d-pico-pi.dts @@ -19,6 +19,13 @@ led { }; }; + reg_1p5v: regulator-1p5v { + compatible = "regulator-fixed"; + regulator-name = "1P5V"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + }; + sound { compatible = "simple-audio-card"; simple-audio-card,name = "imx7-sgtl5000"; @@ -59,6 +66,33 @@ polytouch: touchscreen@38 { touchscreen-size-x = <800>; touchscreen-size-y = <480>; }; + + camera@3c { + compatible = "ovti,ov5645"; + reg = <0x3c>; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_camera>; + + clocks = <&clks IMX7D_CLKO1_ROOT_DIV>; + assigned-clocks = <&clks IMX7D_CLKO1_ROOT_DIV>; + assigned-clock-rates = <24000000>; + + enable-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio1 5 GPIO_ACTIVE_LOW>; + + vdda-supply = <®_2p5v>; + vdddo-supply = <®_vref_1v8>; + vddd-supply = <®_1p5v>; + + port { + ov5645_to_mipi_csi2: endpoint { + remote-endpoint = <&mipi_csi2_in>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; }; &usdhc1 { @@ -93,5 +127,37 @@ MX7D_PAD_EPDC_DATA04__GPIO2_IO4 0x14 MX7D_PAD_EPDC_DATA13__GPIO2_IO13 0x14 >; }; - +}; + +&iomuxc_lpsr { + pinctrl_camera: cameragrp { + fsl,pins = < + MX7D_PAD_LPSR_GPIO1_IO04__GPIO1_IO4 0x15 + MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x15 + MX7D_PAD_LPSR_GPIO1_IO02__CCM_CLKO1 0x7d + >; + }; +}; + +&csi { + status = "okay"; +}; + +&mipi_csi { + status = "okay"; + + ports { + port@0 { + reg = <0>; + + mipi_csi2_in: endpoint { + remote-endpoint = <&ov5645_to_mipi_csi2>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&video_mux { + status = "okay"; }; From da6662e9933880124ff6e8eea73e73a775d9ac65 Mon Sep 17 00:00:00 2001 From: Alexander Feilke Date: Wed, 27 May 2026 11:37:17 +0200 Subject: [PATCH 33/35] ARM: dts: imx7: add nvmem-layout TQMa7 has board-information located in EEPROM at offset 0x20. Add necessary nodes and properties for nvmem cell. Signed-off-by: Alexander Feilke Signed-off-by: Frank Li --- arch/arm/boot/dts/nxp/imx/imx7-tqma7.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/nxp/imx/imx7-tqma7.dtsi b/arch/arm/boot/dts/nxp/imx/imx7-tqma7.dtsi index 2966a33bc528..020eb0c7c353 100644 --- a/arch/arm/boot/dts/nxp/imx/imx7-tqma7.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx7-tqma7.dtsi @@ -151,6 +151,16 @@ m24c64: eeprom@50 { reg = <0x50>; pagesize = <32>; vcc-supply = <&vgen4_reg>; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + module_info: module-info@20 { + reg = <0x20 0x60>; + }; + }; }; at24c02: eeprom@56 { From 936bde7f106cac02c07c38894e0596ae25b65398 Mon Sep 17 00:00:00 2001 From: Alice Guo Date: Tue, 19 May 2026 18:55:16 +0800 Subject: [PATCH 34/35] ARM: dts: freescale: add bootph-all to i.MX7ULP watchdog nodes Add the bootph-all property to ULP watchdog nodes for i.MX7ULP, ensuring the watchdog is available during all boot phases. Signed-off-by: Alice Guo Signed-off-by: Frank Li --- arch/arm/boot/dts/nxp/imx/imx7ulp.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm/boot/dts/nxp/imx/imx7ulp.dtsi b/arch/arm/boot/dts/nxp/imx/imx7ulp.dtsi index 880b9a4f32b0..564783735de8 100644 --- a/arch/arm/boot/dts/nxp/imx/imx7ulp.dtsi +++ b/arch/arm/boot/dts/nxp/imx/imx7ulp.dtsi @@ -297,6 +297,18 @@ smc1: clock-controller@40410000 { clock-names = "divcore", "hsrun_divcore"; }; + wdog2: watchdog@40430000 { + compatible = "fsl,imx7ulp-wdt"; + reg = <0x40430000 0x10000>; + interrupts = ; + clocks = <&pcc2 IMX7ULP_CLK_WDG2>; + assigned-clocks = <&pcc2 IMX7ULP_CLK_WDG2>; + assigned-clock-parents = <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>; + timeout-sec = <40>; + status = "disabled"; + bootph-all; + }; + pcc3: clock-controller@40b30000 { compatible = "fsl,imx7ulp-pcc3"; reg = <0x40b30000 0x10000>; From 8772e1f64c7d69986821d71d8e58fd10594c9aa1 Mon Sep 17 00:00:00 2001 From: Frank Li Date: Fri, 13 Feb 2026 12:17:11 -0500 Subject: [PATCH 35/35] dt-bindings: soc: imx: Add fsl,aipi-bus and fsl,emi-bus Add the fsl,aipi-bus and fsl,emi-bus compatible strings for i.MX1 and i.MX2 variants. These compatibles are only intended for existing legacy chips (more than 15 years old) and will not be used for new device trees. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Frank Li --- Documentation/devicetree/bindings/bus/fsl,spba-bus.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/bus/fsl,spba-bus.yaml b/Documentation/devicetree/bindings/bus/fsl,spba-bus.yaml index 00bbde203f59..4808065fc911 100644 --- a/Documentation/devicetree/bindings/bus/fsl,spba-bus.yaml +++ b/Documentation/devicetree/bindings/bus/fsl,spba-bus.yaml @@ -26,8 +26,10 @@ select: compatible: contains: enum: + - fsl,aipi-bus - fsl,aips - fsl,emi + - fsl,emi-bus - fsl,spba-bus required: - compatible @@ -39,8 +41,10 @@ properties: compatible: items: - enum: + - fsl,aipi-bus - fsl,aips - fsl,emi + - fsl,emi-bus - fsl,spba-bus - const: simple-bus