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arm64: dts: imx8m: Add TMU phandle to calibration data in OCOTP

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The TMU TASR, TCALIVn, TRIM registers must be explicitly programmed with
calibration values in OCOTP. Add the OCOTP calibration values phandle so
the TMU driver can perform this programming.

The MX8MM/MX8MN TMUv1 uses only one OCOTP cell, while MX8MP TMUv2 uses 4.

Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This commit is contained in:
Marek Vasut
2022-12-02 17:23:52 +01:00
committed by Shawn Guo
parent 5b81a87ddd
commit 105b9bb84f
3 changed files with 18 additions and 0 deletions
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6
arch/arm64/boot/dts/freescale/imx8mm.dtsi
View File

@@ -496,6 +496,8 @@ tmu: tmu@30260000 {
compatible = "fsl,imx8mm-tmu";
reg = <0x30260000 0x10000>;
clocks = <&clk IMX8MM_CLK_TMU_ROOT>;
nvmem-cells = <&tmu_calib>;
nvmem-cell-names = "calib";
#thermal-sensor-cells = <0>;
};
@@ -584,6 +586,10 @@ cpu_speed_grade: speed-grade@10 { /* 0x440 */
reg = <0x10 4>;
};
tmu_calib: calib@3c { /* 0x4f0 */
reg = <0x3c 4>;
};
fec_mac_address: mac-address@90 { /* 0x640 */
reg = <0x90 6>;
};

6
arch/arm64/boot/dts/freescale/imx8mn.dtsi
View File

@@ -498,6 +498,8 @@ tmu: tmu@30260000 {
compatible = "fsl,imx8mn-tmu", "fsl,imx8mm-tmu";
reg = <0x30260000 0x10000>;
clocks = <&clk IMX8MN_CLK_TMU_ROOT>;
nvmem-cells = <&tmu_calib>;
nvmem-cell-names = "calib";
#thermal-sensor-cells = <0>;
};
@@ -585,6 +587,10 @@ cpu_speed_grade: speed-grade@10 { /* 0x440 */
reg = <0x10 4>;
};
tmu_calib: calib@3c { /* 0x4f0 */
reg = <0x3c 4>;
};
fec_mac_address: mac-address@90 { /* 0x640 */
reg = <0x90 6>;
};

6
arch/arm64/boot/dts/freescale/imx8mp.dtsi
View File

@@ -380,6 +380,8 @@ tmu: tmu@30260000 {
compatible = "fsl,imx8mp-tmu";
reg = <0x30260000 0x10000>;
clocks = <&clk IMX8MP_CLK_TSENSOR_ROOT>;
nvmem-cells = <&tmu_calib>;
nvmem-cell-names = "calib";
#thermal-sensor-cells = <1>;
};
@@ -453,6 +455,10 @@ eth_mac1: mac-address@90 { /* 0x640 */
eth_mac2: mac-address@96 { /* 0x658 */
reg = <0x96 6>;
};
tmu_calib: calib@264 { /* 0xd90-0xdc0 */
reg = <0x264 0x10>;
};
};
anatop: clock-controller@30360000 {