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arm64: dts: ti: k3-j7200: Remove PCIe endpoint node

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This node is an example node for the PCIe controller in "endpoint" mode.
By default the controller is in "root complex" mode and there is already a
DT node for the same.

Examples should go in the bindings or other documentation.

Remove this node.

Signed-off-by: Andrew Davis <afd@ti.com>
Link: https://lore.kernel.org/r/20240124183659.149119-2-afd@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
This commit is contained in:
Andrew Davis
2024-01-24 12:36:57 -06:00
committed by Vignesh Raghavendra
parent 1b63a1b480
commit 0b16abe711
2 changed files with 0 additions and 27 deletions
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7
arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
View File

@@ -388,10 +388,3 @@ &pcie1_rc {
phy-names = "pcie-phy";
num-lanes = <2>;
};
&pcie1_ep {
phys = <&serdes0_pcie_link>;
phy-names = "pcie-phy";
num-lanes = <2>;
status = "disabled";
};

20
arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
View File

@@ -773,26 +773,6 @@ pcie1_rc: pcie@2910000 {
status = "disabled";
};
pcie1_ep: pcie-ep@2910000 {
compatible = "ti,j7200-pcie-ep", "ti,j721e-pcie-ep";
reg = <0x00 0x02910000 0x00 0x1000>,
<0x00 0x02917000 0x00 0x400>,
<0x00 0x0d800000 0x00 0x00800000>,
<0x00 0x18000000 0x00 0x08000000>;
reg-names = "intd_cfg", "user_cfg", "reg", "mem";
interrupt-names = "link_state";
interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
ti,syscon-pcie-ctrl = <&scm_conf 0x4074>;
max-link-speed = <3>;
num-lanes = <4>;
power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 240 6>;
clock-names = "fck";
max-functions = /bits/ 8 <6>;
max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
dma-coherent;
};
usbss0: cdns-usb@4104000 {
compatible = "ti,j721e-usb";
reg = <0x00 0x4104000 0x00 0x100>;