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arm64: dts: ti: k3-j7200: Enable PCIe nodes at the board level

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PCIe node defined in the top-level J7200 SoC dtsi file is incomplete
and will not be functional unless it is extended with a SerDes PHY.

As the PHY and mode is only known at the board integration level, this
node should only be enabled when provided with this information.

Disable the PCIe node in the dtsi files and only enable when it is
actually pinned out on a given board.

Signed-off-by: Andrew Davis <afd@ti.com>
Link: https://lore.kernel.org/r/20240124183659.149119-1-afd@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
This commit is contained in:
Andrew Davis
2024-01-24 12:36:56 -06:00
committed by Vignesh Raghavendra
parent b1898456a4
commit 1b63a1b480
2 changed files with 2 additions and 0 deletions
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1
arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
View File

@@ -382,6 +382,7 @@ serdes0_qsgmii_link: phy@1 {
};
&pcie1_rc {
status = "okay";
reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>;
phys = <&serdes0_pcie_link>;
phy-names = "pcie-phy";

1
arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
View File

@@ -770,6 +770,7 @@ pcie1_rc: pcie@2910000 {
ranges = <0x01000000 0x0 0x18001000 0x00 0x18001000 0x0 0x0010000>,
<0x02000000 0x0 0x18011000 0x00 0x18011000 0x0 0x7fef000>;
dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
status = "disabled";
};
pcie1_ep: pcie-ep@2910000 {