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Merge tag 'renesas-dt-for-v4.15' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/soc

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Pull "Renesas ARM Based SoC DT Updates for v4.15" from Simon Horman:

* r7s72100 (RZ/A1) Peach board
  - Add pin groups for SCIF2 serial debug interface and Ethernet
    This avoids relying on bootloader settings
  - Support control of LED1 using gpio-leds

* r8a7743 (RZ/G1M) and r8a7745 (RZ/G1E) SoCs
  - Add MSIOF[012] support and define aliases for spi[0123]

* r8a7743 (RZ/G1M) SoC
  - Add I2C and IIC core nodes

* r8a7743 (RZ/G1M) iW-RainboW-G20D-Qseven development platform
   - Enable SDHI1 SD controller supporting high-speed and SDR50 transfers
   - Add chosen node to allow correct selection of serial console
     and the kernel command line
   - Enable RTC support
   - Enable USB2.0 host support
     This includes enabling USB PHY and internal PCI

* r8a7743 (RZ/G1M) iW-RainboW-G20M-Qseven and
  r8a7745 (RZ/G1E) iW-RainboW-G22M-SM SoMs
   - Enable Add SPI NOR support
     This devices is used to boot up the system to the SoM DT

* r8a7743 (RZ/G1M) iW-RainboW-G20M-Qseven SoM
  - Enable SDHI0 SD controller supporting high-speed transfers

* r8a7745 (RZ/G1E) iW-RainboW-G22D development platform
  - Add pnctl support for scif4
    This avoids reling on boot loader settings
  - Add EtherAVB support

* r8a7745 (RZ/G1E) iW-RainboW-G22M-SM SoM
  - Add basic SoM support
  - Enable MMCIF eMMC support
  - Enable RTC support
  - Enable SDHI1 SD controller supporting high-speed transfers

* r8a779[0-4] R-Car Gen2 SoCs
  - Add reset control properties
    Geert Uytterhoeven says:

    This patch series describes the reset topology on all R-Car Gen2 Socs,
    like was done before for R-Car Gen3 and RZ/G1.

    Resets usually match the corresponding module clocks.  Exceptions are:
      - The audio module has resets for the Serial Sound Interfaces only,
      - The display module has only a single reset for all DU channels, but
	adding reset properties for the display is postponed upon request
	from Laurent.

   - Convert to new CPG/MSSR bindings
     Geert Uytterhoven says:

     Currently Renesas R-Car Gen2 SoCs use the common clk-rcar-gen2,
     clk-mstp, and clk-div6 drivers, which depend on most clocks being
     described in DT.  Especially the module (MSTP) clocks are cumbersome
     and error prone, due to 3 arrays (clocks, clock-indices, and
     clock-output-names) to be kept in sync. In addition, the clk-mstp
     driver cannot be extended easily to also support module resets, which
     are provided by the same hardware module.

     Hence when developing support for R-Car Gen3 SoCs, another approach
     was chosen, which led to the CPG/MSSR driver core, and SoC-specific
     subdrivers (initially for R-Car Gen3, but later also for RZ/G1).

     This series converts the various R-Car Gen2 DTSes to migrate to the
     new CPG/MSSR drivers that were added in v4.13-rc1.

* r8a779[0,1,3,4] R-Car Gen2 SoCs
  - Stop grouping clocks under a "clocks" subnode
    Geert Uytterhoeven says:

    The current practice is to not group clocks under a "clocks" subnode,
    but just put them together with the other on-SoC devices.

    Hence this patch series implements this for the various R-Car Gen2
    DTSes that still need this (r8a7792.dtsi is OK).

* r8a7794 (E2) Alt board
  - Correct inverted sense of SD wip pins

* tag 'renesas-dt-for-v4.15' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (48 commits)
  ARM: dts: r8a7743: Add MSIOF[012] support
  ARM: dts: r8a7745: Add MSIOF[012] support
  ARM: dts: iwg22d: Enable SDHI0 controller
  ARM: dts: iwg22m: Add SPI NOR support
  ARM: dts: r8a7745: Add QSPI support
  ARM: dts: iwg20m: Add SPI NOR support
  ARM: dts: r8a7743: Add QSPI support
  ARM: dts: iwg22m: Enable SDHI1 controller
  ARM: dts: r8a7745: Add SDHI controllers
  ARM: dts: r8a7794: Add reset control properties
  ARM: dts: r8a7793: Add reset control properties
  ARM: dts: r8a7792: Add reset control properties
  ARM: dts: r8a7791: Add reset control properties
  ARM: dts: r8a7790: Add reset control properties
  ARM: dts: r8a7743: Add IIC cores to dtsi
  ARM: dts: alt: use correct logic for SD WP pins
  ARM: dts: iwg20d-q7: Enable USB PHY
  ARM: dts: iwg20d-q7: Enable internal PCI
  ARM: dts: r8a7743: Link PCI USB devices to USB PHY
  ARM: dts: r8a7743: Add USB PHY DT support
  ...
This commit is contained in:
Arnd Bergmann
2017-10-19 23:41:57 +02:00
parent c305cf3388 7031a219f6
commit 063f7c8248
21 changed files with 1931 additions and 2268 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
arch/arm/boot/dts/Makefile
View File

@@ -725,6 +725,7 @@ dtb-$(CONFIG_ARCH_RENESAS) += \
r8a7740-armadillo800eva.dtb \
r8a7743-iwg20d-q7.dtb \
r8a7743-sk-rzg1m.dtb \
r8a7745-iwg22d-sodimm.dtb \
r8a7745-sk-rzg1e.dtb \
r8a7778-bockw.dtb \
r8a7779-marzen.dtb \

22
arch/arm/boot/dts/r7s72100-gr-peach.dts
View File

@@ -11,6 +11,8 @@
/dts-v1/;
#include "r7s72100.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/r7s72100-pinctrl.h>
/ {
model = "GR-Peach";
@@ -28,7 +30,6 @@ chosen {
memory@20000000 {
device_type = "memory";
reg = <0x20000000 0x00a00000>;
};
lbsc {
@@ -51,6 +52,22 @@ rootfs@600000 {
reg = <0x00600000 0x00200000>;
};
};
leds {
status = "okay";
compatible = "gpio-leds";
led1 {
gpios = <&port6 12 GPIO_ACTIVE_HIGH>;
};
};
};
&pinctrl {
scif2_pins: serial2 {
/* P6_2 as RxD2; P6_3 as TxD2 */
pinmux = <RZA1_PINMUX(6, 2, 7)>, <RZA1_PINMUX(6, 3, 7)>;
};
};
&extal_clk {
@@ -62,5 +79,8 @@ &usb_x1_clk {
};
&scif2 {
pinctrl-names = "default";
pinctrl-0 = <&scif2_pins>;
status = "okay";
};

97
arch/arm/boot/dts/r8a7743-iwg20d-q7.dts
View File

@@ -19,9 +19,42 @@ aliases {
serial0 = &scif0;
ethernet0 = &avb;
};
chosen {
bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
stdout-path = "serial0:115200n8";
};
vcc_sdhi1: regulator-vcc-sdhi1 {
compatible = "regulator-fixed";
regulator-name = "SDHI1 Vcc";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio1 16 GPIO_ACTIVE_LOW>;
};
vccq_sdhi1: regulator-vccq-sdhi1 {
compatible = "regulator-gpio";
regulator-name = "SDHI1 VccQ";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
gpios = <&gpio2 30 GPIO_ACTIVE_LOW>;
gpios-states = <1>;
states = <3300000 1
1800000 0>;
};
};
&pfc {
i2c2_pins: i2c2 {
groups = "i2c2";
function = "i2c2";
};
scif0_pins: scif0 {
groups = "scif0_data_d";
function = "scif0";
@@ -31,6 +64,28 @@ avb_pins: avb {
groups = "avb_mdio", "avb_gmii";
function = "avb";
};
sdhi1_pins: sd1 {
groups = "sdhi1_data4", "sdhi1_ctrl";
function = "sdhi1";
power-source = <3300>;
};
sdhi1_pins_uhs: sd1_uhs {
groups = "sdhi1_data4", "sdhi1_ctrl";
function = "sdhi1";
power-source = <1800>;
};
usb0_pins: usb0 {
groups = "usb0";
function = "usb0";
};
usb1_pins: usb1 {
groups = "usb1";
function = "usb1";
};
};
&scif0 {
@@ -54,3 +109,45 @@ phy3: ethernet-phy@3 {
micrel,led-mode = <1>;
};
};
&sdhi1 {
pinctrl-0 = <&sdhi1_pins>;
pinctrl-1 = <&sdhi1_pins_uhs>;
pinctrl-names = "default", "state_uhs";
vmmc-supply = <&vcc_sdhi1>;
vqmmc-supply = <&vccq_sdhi1>;
cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>;
sd-uhs-sdr50;
status = "okay";
};
&i2c2 {
pinctrl-0 = <&i2c2_pins>;
pinctrl-names = "default";
status = "okay";
clock-frequency = <400000>;
rtc@68 {
compatible = "ti,bq32000";
reg = <0x68>;
};
};
&pci0 {
status = "okay";
pinctrl-0 = <&usb0_pins>;
pinctrl-names = "default";
};
&pci1 {
status = "okay";
pinctrl-0 = <&usb1_pins>;
pinctrl-names = "default";
};
&usbphy {
status = "okay";
};

43
arch/arm/boot/dts/r8a7743-iwg20m.dtsi
View File

@@ -9,6 +9,7 @@
*/
#include "r8a7743.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
compatible = "iwave,g20m", "renesas,r8a7743";
@@ -42,6 +43,17 @@ mmcif0_pins: mmc {
groups = "mmc_data8_b", "mmc_ctrl";
function = "mmc";
};
qspi_pins: qspi {
groups = "qspi_ctrl", "qspi_data2";
function = "qspi";
};
sdhi0_pins: sd0 {
groups = "sdhi0_data4", "sdhi0_ctrl";
function = "sdhi0";
power-source = <3300>;
};
};
&mmcif0 {
@@ -53,3 +65,34 @@ &mmcif0 {
non-removable;
status = "okay";
};
&qspi {
pinctrl-0 = <&qspi_pins>;
pinctrl-names = "default";
status = "okay";
/* WARNING - This device contains the bootloader. Handle with care. */
flash: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "sst,sst25vf016b", "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <50000000>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <1>;
m25p,fast-read;
spi-cpol;
spi-cpha;
};
};
&sdhi0 {
pinctrl-0 = <&sdhi0_pins>;
pinctrl-names = "default";
vmmc-supply = <&reg_3p3v>;
vqmmc-supply = <&reg_3p3v>;
cd-gpios = <&gpio7 11 GPIO_ACTIVE_LOW>;
status = "okay";
};

257
arch/arm/boot/dts/r8a7743.dtsi
View File

@@ -25,6 +25,13 @@ aliases {
i2c3 = &i2c3;
i2c4 = &i2c4;
i2c5 = &i2c5;
i2c6 = &iic0;
i2c7 = &iic1;
i2c8 = &iic3;
spi0 = &qspi;
spi1 = &msiof0;
spi2 = &msiof1;
spi3 = &msiof2;
};
cpus {
@@ -436,6 +443,58 @@ i2c5: i2c@e6528000 {
status = "disabled";
};
iic0: i2c@e6500000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "renesas,iic-r8a7743",
"renesas,rcar-gen2-iic",
"renesas,rmobile-iic";
reg = <0 0xe6500000 0 0x425>;
interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 318>;
dmas = <&dmac0 0x61>, <&dmac0 0x62>,
<&dmac1 0x61>, <&dmac1 0x62>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
resets = <&cpg 318>;
status = "disabled";
};
iic1: i2c@e6510000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "renesas,iic-r8a7743",
"renesas,rcar-gen2-iic",
"renesas,rmobile-iic";
reg = <0 0xe6510000 0 0x425>;
interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 323>;
dmas = <&dmac0 0x65>, <&dmac0 0x66>,
<&dmac1 0x65>, <&dmac1 0x66>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
resets = <&cpg 323>;
status = "disabled";
};
iic3: i2c@e60b0000 {
/* doesn't need pinmux */
#address-cells = <1>;
#size-cells = <0>;
compatible = "renesas,iic-r8a7743",
"renesas,rcar-gen2-iic",
"renesas,rmobile-iic";
reg = <0 0xe60b0000 0 0x425>;
interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 926>;
dmas = <&dmac0 0x77>, <&dmac0 0x78>,
<&dmac1 0x77>, <&dmac1 0x78>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
resets = <&cpg 926>;
status = "disabled";
};
scifa0: serial@e6c40000 {
compatible = "renesas,scifa-r8a7743",
"renesas,rcar-gen2-scifa", "renesas,scifa";
@@ -779,6 +838,204 @@ mmcif0: mmc@ee200000 {
max-frequency = <97500000>;
status = "disabled";
};
qspi: spi@e6b10000 {
compatible = "renesas,qspi-r8a7743", "renesas,qspi";
reg = <0 0xe6b10000 0 0x2c>;
interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 917>;
dmas = <&dmac0 0x17>, <&dmac0 0x18>,
<&dmac1 0x17>, <&dmac1 0x18>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
num-cs = <1>;
#address-cells = <1>;
#size-cells = <0>;
resets = <&cpg 917>;
status = "disabled";
};
msiof0: spi@e6e20000 {
compatible = "renesas,msiof-r8a7743",
"renesas,rcar-gen2-msiof";
reg = <0 0xe6e20000 0 0x0064>;
interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 000>;
dmas = <&dmac0 0x51>, <&dmac0 0x52>,
<&dmac1 0x51>, <&dmac1 0x52>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
#address-cells = <1>;
#size-cells = <0>;
resets = <&cpg 000>;
status = "disabled";
};
msiof1: spi@e6e10000 {
compatible = "renesas,msiof-r8a7743",
"renesas,rcar-gen2-msiof";
reg = <0 0xe6e10000 0 0x0064>;
interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 208>;
dmas = <&dmac0 0x55>, <&dmac0 0x56>,
<&dmac1 0x55>, <&dmac1 0x56>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
#address-cells = <1>;
#size-cells = <0>;
resets = <&cpg 208>;
status = "disabled";
};
msiof2: spi@e6e00000 {
compatible = "renesas,msiof-r8a7743",
"renesas,rcar-gen2-msiof";
reg = <0 0xe6e00000 0 0x0064>;
interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 205>;
dmas = <&dmac0 0x41>, <&dmac0 0x42>,
<&dmac1 0x41>, <&dmac1 0x42>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
#address-cells = <1>;
#size-cells = <0>;
resets = <&cpg 205>;
status = "disabled";
};
sdhi0: sd@ee100000 {
compatible = "renesas,sdhi-r8a7743";
reg = <0 0xee100000 0 0x328>;
interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 314>;
dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
<&dmac1 0xcd>, <&dmac1 0xce>;
dma-names = "tx", "rx", "tx", "rx";
max-frequency = <195000000>;
power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
resets = <&cpg 314>;
status = "disabled";
};
sdhi1: sd@ee140000 {
compatible = "renesas,sdhi-r8a7743";
reg = <0 0xee140000 0 0x100>;
interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 312>;
dmas = <&dmac0 0xc1>, <&dmac0 0xc2>,
<&dmac1 0xc1>, <&dmac1 0xc2>;
dma-names = "tx", "rx", "tx", "rx";
max-frequency = <97500000>;
power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
resets = <&cpg 312>;
status = "disabled";
};
sdhi2: sd@ee160000 {
compatible = "renesas,sdhi-r8a7743";
reg = <0 0xee160000 0 0x100>;
interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 311>;
dmas = <&dmac0 0xd3>, <&dmac0 0xd4>,
<&dmac1 0xd3>, <&dmac1 0xd4>;
dma-names = "tx", "rx", "tx", "rx";
max-frequency = <97500000>;
power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
resets = <&cpg 311>;
status = "disabled";
};
usbphy: usb-phy@e6590100 {
compatible = "renesas,usb-phy-r8a7743",
"renesas,rcar-gen2-usb-phy";
reg = <0 0xe6590100 0 0x100>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&cpg CPG_MOD 704>;
clock-names = "usbhs";
power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
resets = <&cpg 704>;
status = "disabled";
usb0: usb-channel@0 {
reg = <0>;
#phy-cells = <1>;
};
usb2: usb-channel@2 {
reg = <2>;
#phy-cells = <1>;
};
};
pci0: pci@ee090000 {
compatible = "renesas,pci-r8a7743",
"renesas,pci-rcar-gen2";
device_type = "pci";
reg = <0 0xee090000 0 0xc00>,
<0 0xee080000 0 0x1100>;
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 703>;
power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
resets = <&cpg 703>;
status = "disabled";
bus-range = <0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
interrupt-map-mask = <0xff00 0 0 0x7>;
interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
usb@1,0 {
reg = <0x800 0 0 0 0>;
phys = <&usb0 0>;
phy-names = "usb";
};
usb@2,0 {
reg = <0x1000 0 0 0 0>;
phys = <&usb0 0>;
phy-names = "usb";
};
};
pci1: pci@ee0d0000 {
compatible = "renesas,pci-r8a7743",
"renesas,pci-rcar-gen2";
device_type = "pci";
reg = <0 0xee0d0000 0 0xc00>,
<0 0xee0c0000 0 0x1100>;
interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 703>;
power-domains = <&sysc R8A7743_PD_ALWAYS_ON>;
resets = <&cpg 703>;
status = "disabled";
bus-range = <1 1>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
interrupt-map-mask = <0xff00 0 0 0x7>;
interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
usb@1,0 {
reg = <0x10800 0 0 0 0>;
phys = <&usb2 0>;
phy-names = "usb";
};
usb@2,0 {
reg = <0x11000 0 0 0 0>;
phys = <&usb2 0>;
phy-names = "usb";
};
};
};
/* External root clock */

94
arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts Normal file
View File

@@ -0,0 +1,94 @@
/*
* Device Tree Source for the iWave-RZG1E SODIMM carrier board
*
* Copyright (C) 2017 Renesas Electronics Corp.
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
* kind, whether express or implied.
*/
/dts-v1/;
#include "r8a7745-iwg22m.dtsi"
/ {
model = "iWave Systems RainboW-G22D-SODIMM board based on RZ/G1E";
compatible = "iwave,g22d", "iwave,g22m", "renesas,r8a7745";
aliases {
serial0 = &scif4;
ethernet0 = &avb;
};
chosen {
bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
stdout-path = "serial0:115200n8";
};
vccq_sdhi0: regulator-vccq-sdhi0 {
compatible = "regulator-gpio";
regulator-name = "SDHI0 VccQ";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
gpios = <&gpio0 20 GPIO_ACTIVE_LOW>;
gpios-states = <1>;
states = <3300000 1
1800000 0>;
};
};
&pfc {
scif4_pins: scif4 {
groups = "scif4_data_b";
function = "scif4";
};
avb_pins: avb {
groups = "avb_mdio", "avb_gmii";
function = "avb";
};
sdhi0_pins: sd0 {
groups = "sdhi0_data4", "sdhi0_ctrl";
function = "sdhi0";
power-source = <3300>;
};
};
&scif4 {
pinctrl-0 = <&scif4_pins>;
pinctrl-names = "default";
status = "okay";
};
&avb {
pinctrl-0 = <&avb_pins>;
pinctrl-names = "default";
phy-handle = <&phy3>;
phy-mode = "gmii";
renesas,no-ether-link;
status = "okay";
phy3: ethernet-phy@3 {
/*
* On some older versions of the platform (before R4.0) the phy address
* may be 1 or 3. The address is fixed to 3 for R4.0 onwards.
*/
reg = <3>;
micrel,led-mode = <1>;
};
};
&sdhi0 {
pinctrl-0 = <&sdhi0_pins>;
pinctrl-names = "default";
vmmc-supply = <&reg_3p3v>;
vqmmc-supply = <&vccq_sdhi0>;
cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>;
status = "okay";
};

111
arch/arm/boot/dts/r8a7745-iwg22m.dtsi Normal file
View File

@@ -0,0 +1,111 @@
/*
* Device Tree Source for the iWave-RZG1E-G22M SODIMM SOM
*
* Copyright (C) 2017 Renesas Electronics Corp.
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
* kind, whether express or implied.
*/
#include "r8a7745.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
compatible = "iwave,g22m", "renesas,r8a7745";
memory@40000000 {
device_type = "memory";
reg = <0 0x40000000 0 0x20000000>;
};
reg_3p3v: 3p3v {
compatible = "regulator-fixed";
regulator-name = "3P3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
};
};
&extal_clk {
clock-frequency = <20000000>;
};
&pfc {
mmcif0_pins: mmc {
groups = "mmc_data8", "mmc_ctrl";
function = "mmc";
};
qspi_pins: qspi {
groups = "qspi_ctrl", "qspi_data2";
function = "qspi";
};
sdhi1_pins: sd1 {
groups = "sdhi1_data4", "sdhi1_ctrl";
function = "sdhi1";
power-source = <3300>;
};
i2c3_pins: i2c3 {
groups = "i2c3_b";
function = "i2c3";
};
};
&mmcif0 {
pinctrl-0 = <&mmcif0_pins>;
pinctrl-names = "default";
vmmc-supply = <&reg_3p3v>;
bus-width = <8>;
non-removable;
status = "okay";
};
&qspi {
pinctrl-0 = <&qspi_pins>;
pinctrl-names = "default";
status = "okay";
/* WARNING - This device contains the bootloader. Handle with care. */
flash: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "sst,sst25vf016b", "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <50000000>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <1>;
m25p,fast-read;
spi-cpol;
spi-cpha;
};
};
&sdhi1 {
pinctrl-0 = <&sdhi1_pins>;
pinctrl-names = "default";
vmmc-supply = <&reg_3p3v>;
vqmmc-supply = <&reg_3p3v>;
cd-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>;
status = "okay";
};
&i2c3 {
pinctrl-0 = <&i2c3_pins>;
pinctrl-names = "default";
status = "okay";
clock-frequency = <400000>;
rtc@68 {
compatible = "ti,bq32000";
reg = <0x68>;
};
};

337
arch/arm/boot/dts/r8a7745.dtsi
View File

@@ -18,6 +18,19 @@ / {
#address-cells = <2>;
#size-cells = <2>;
aliases {
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c2 = &i2c2;
i2c3 = &i2c3;
i2c4 = &i2c4;
i2c5 = &i2c5;
spi0 = &qspi;
spi1 = &msiof0;
spi2 = &msiof1;
spi3 = &msiof2;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -65,6 +78,111 @@ gic: interrupt-controller@f1001000 {
resets = <&cpg 408>;
};
gpio0: gpio@e6050000 {
compatible = "renesas,gpio-r8a7745",
"renesas,rcar-gen2-gpio";
reg = <0 0xe6050000 0 0x50>;
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
gpio-controller;
gpio-ranges = <&pfc 0 0 32>;
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&cpg CPG_MOD 912>;
power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
resets = <&cpg 912>;
};
gpio1: gpio@e6051000 {
compatible = "renesas,gpio-r8a7745",
"renesas,rcar-gen2-gpio";
reg = <0 0xe6051000 0 0x50>;
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
gpio-controller;
gpio-ranges = <&pfc 0 32 26>;
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&cpg CPG_MOD 911>;
power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
resets = <&cpg 911>;
};
gpio2: gpio@e6052000 {
compatible = "renesas,gpio-r8a7745",
"renesas,rcar-gen2-gpio";
reg = <0 0xe6052000 0 0x50>;
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
gpio-controller;
gpio-ranges = <&pfc 0 64 32>;
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&cpg CPG_MOD 910>;
power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
resets = <&cpg 910>;
};
gpio3: gpio@e6053000 {
compatible = "renesas,gpio-r8a7745",
"renesas,rcar-gen2-gpio";
reg = <0 0xe6053000 0 0x50>;
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
gpio-controller;
gpio-ranges = <&pfc 0 96 32>;
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&cpg CPG_MOD 909>;
power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
resets = <&cpg 909>;
};
gpio4: gpio@e6054000 {
compatible = "renesas,gpio-r8a7745",
"renesas,rcar-gen2-gpio";
reg = <0 0xe6054000 0 0x50>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
gpio-controller;
gpio-ranges = <&pfc 0 128 32>;
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&cpg CPG_MOD 908>;
power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
resets = <&cpg 908>;
};
gpio5: gpio@e6055000 {
compatible = "renesas,gpio-r8a7745",
"renesas,rcar-gen2-gpio";
reg = <0 0xe6055000 0 0x50>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
gpio-controller;
gpio-ranges = <&pfc 0 160 28>;
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&cpg CPG_MOD 907>;
power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
resets = <&cpg 907>;
};
gpio6: gpio@e6055400 {
compatible = "renesas,gpio-r8a7745",
"renesas,rcar-gen2-gpio";
reg = <0 0xe6055400 0 0x50>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
gpio-controller;
gpio-ranges = <&pfc 0 192 26>;
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&cpg CPG_MOD 905>;
power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
resets = <&cpg 905>;
};
irqc: interrupt-controller@e61c0000 {
compatible = "renesas,irqc-r8a7745", "renesas,irqc";
#interrupt-cells = <2>;
@@ -508,6 +626,225 @@ ether: ethernet@ee700000 {
#size-cells = <0>;
status = "disabled";
};
avb: ethernet@e6800000 {
compatible = "renesas,etheravb-r8a7745",
"renesas,etheravb-rcar-gen2";
reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 812>;
power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
resets = <&cpg 812>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c0: i2c@e6508000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "renesas,i2c-r8a7745",
"renesas,rcar-gen2-i2c";
reg = <0 0xe6508000 0 0x40>;
interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 931>;
power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
resets = <&cpg 931>;
i2c-scl-internal-delay-ns = <6>;
status = "disabled";
};
i2c1: i2c@e6518000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "renesas,i2c-r8a7745",
"renesas,rcar-gen2-i2c";
reg = <0 0xe6518000 0 0x40>;
interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 930>;
power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
resets = <&cpg 930>;
i2c-scl-internal-delay-ns = <6>;
status = "disabled";
};
i2c2: i2c@e6530000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "renesas,i2c-r8a7745",
"renesas,rcar-gen2-i2c";
reg = <0 0xe6530000 0 0x40>;
interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 929>;
power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
resets = <&cpg 929>;
i2c-scl-internal-delay-ns = <6>;
status = "disabled";
};
i2c3: i2c@e6540000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "renesas,i2c-r8a7745",
"renesas,rcar-gen2-i2c";
reg = <0 0xe6540000 0 0x40>;
interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 928>;
power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
resets = <&cpg 928>;
i2c-scl-internal-delay-ns = <6>;
status = "disabled";
};
i2c4: i2c@e6520000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "renesas,i2c-r8a7745",
"renesas,rcar-gen2-i2c";
reg = <0 0xe6520000 0 0x40>;
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 927>;
power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
resets = <&cpg 927>;
i2c-scl-internal-delay-ns = <6>;
status = "disabled";
};
i2c5: i2c@e6528000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "renesas,i2c-r8a7745",
"renesas,rcar-gen2-i2c";
reg = <0 0xe6528000 0 0x40>;
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 925>;
power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
resets = <&cpg 925>;
i2c-scl-internal-delay-ns = <6>;
status = "disabled";
};
mmcif0: mmc@ee200000 {
compatible = "renesas,mmcif-r8a7745",
"renesas,sh-mmcif";
reg = <0 0xee200000 0 0x80>;
interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 315>;
dmas = <&dmac0 0xd1>, <&dmac0 0xd2>,
<&dmac1 0xd1>, <&dmac1 0xd2>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
resets = <&cpg 315>;
reg-io-width = <4>;
max-frequency = <97500000>;
status = "disabled";
};
qspi: spi@e6b10000 {
compatible = "renesas,qspi-r8a7745", "renesas,qspi";
reg = <0 0xe6b10000 0 0x2c>;
interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 917>;
dmas = <&dmac0 0x17>, <&dmac0 0x18>,
<&dmac1 0x17>, <&dmac1 0x18>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
num-cs = <1>;
#address-cells = <1>;
#size-cells = <0>;
resets = <&cpg 917>;
status = "disabled";
};
msiof0: spi@e6e20000 {
compatible = "renesas,msiof-r8a7745",
"renesas,rcar-gen2-msiof";
reg = <0 0xe6e20000 0 0x0064>;
interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 000>;
dmas = <&dmac0 0x51>, <&dmac0 0x52>,
<&dmac1 0x51>, <&dmac1 0x52>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
#address-cells = <1>;
#size-cells = <0>;
resets = <&cpg 000>;
status = "disabled";
};
msiof1: spi@e6e10000 {
compatible = "renesas,msiof-r8a7745",
"renesas,rcar-gen2-msiof";
reg = <0 0xe6e10000 0 0x0064>;
interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 208>;
dmas = <&dmac0 0x55>, <&dmac0 0x56>,
<&dmac1 0x55>, <&dmac1 0x56>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
#address-cells = <1>;
#size-cells = <0>;
resets = <&cpg 208>;
status = "disabled";
};
msiof2: spi@e6e00000 {
compatible = "renesas,msiof-r8a7745",
"renesas,rcar-gen2-msiof";
reg = <0 0xe6e00000 0 0x0064>;
interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 205>;
dmas = <&dmac0 0x41>, <&dmac0 0x42>,
<&dmac1 0x41>, <&dmac1 0x42>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
#address-cells = <1>;
#size-cells = <0>;
resets = <&cpg 205>;
status = "disabled";
};
sdhi0: sd@ee100000 {
compatible = "renesas,sdhi-r8a7745";
reg = <0 0xee100000 0 0x328>;
interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 314>;
dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
<&dmac1 0xcd>, <&dmac1 0xce>;
dma-names = "tx", "rx", "tx", "rx";
max-frequency = <195000000>;
power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
resets = <&cpg 314>;
status = "disabled";
};
sdhi1: sd@ee140000 {
compatible = "renesas,sdhi-r8a7745";
reg = <0 0xee140000 0 0x100>;
interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 312>;
dmas = <&dmac0 0xc1>, <&dmac0 0xc2>,
<&dmac1 0xc1>, <&dmac1 0xc2>;
dma-names = "tx", "rx", "tx", "rx";
max-frequency = <97500000>;
power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
resets = <&cpg 312>;
status = "disabled";
};
sdhi2: sd@ee160000 {
compatible = "renesas,sdhi-r8a7745";
reg = <0 0xee160000 0 0x100>;
interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 311>;
dmas = <&dmac0 0xd3>, <&dmac0 0xd4>,
<&dmac1 0xd3>, <&dmac1 0xd4>;
dma-names = "tx", "rx", "tx", "rx";
max-frequency = <97500000>;
power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
resets = <&cpg 311>;
status = "disabled";
};
};
/* External root clock */

7
arch/arm/boot/dts/r8a7790-lager.dts
View File

@@ -316,11 +316,8 @@ &du {
pinctrl-names = "default";
status = "okay";
clocks = <&mstp7_clks R8A7790_CLK_DU0>,
<&mstp7_clks R8A7790_CLK_DU1>,
<&mstp7_clks R8A7790_CLK_DU2>,
<&mstp7_clks R8A7790_CLK_LVDS0>,
<&mstp7_clks R8A7790_CLK_LVDS1>,
clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&cpg CPG_MOD 722>,
<&cpg CPG_MOD 726>, <&cpg CPG_MOD 725>,
<&x13_clk>, <&x2_clk>;
clock-names = "du.0", "du.1", "du.2", "lvds.0", "lvds.1",
"dclkin.0", "dclkin.1";

748
arch/arm/boot/dts/r8a7790.dtsi
View File

File diff suppressed because it is too large Load Diff

4
arch/arm/boot/dts/r8a7791-koelsch.dts
View File

@@ -330,9 +330,7 @@ &du {
pinctrl-names = "default";
status = "okay";
clocks = <&mstp7_clks R8A7791_CLK_DU0>,
<&mstp7_clks R8A7791_CLK_DU1>,
<&mstp7_clks R8A7791_CLK_LVDS0>,
clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&cpg CPG_MOD 726>,
<&x13_clk>, <&x2_clk>;
clock-names = "du.0", "du.1", "lvds.0",
"dclkin.0", "dclkin.1";

4
arch/arm/boot/dts/r8a7791-porter.dts
View File

@@ -419,9 +419,7 @@ &du {
pinctrl-names = "default";
status = "okay";
clocks = <&mstp7_clks R8A7791_CLK_DU0>,
<&mstp7_clks R8A7791_CLK_DU1>,
<&mstp7_clks R8A7791_CLK_LVDS0>,
clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&cpg CPG_MOD 726>,
<&x3_clk>, <&x16_clk>;
clock-names = "du.0", "du.1", "lvds.0",
"dclkin.0", "dclkin.1";

754
arch/arm/boot/dts/r8a7791.dtsi
View File

File diff suppressed because it is too large Load Diff

3
arch/arm/boot/dts/r8a7792-blanche.dts
View File

@@ -310,8 +310,7 @@ &du {
pinctrl-0 = <&du0_pins &du1_pins>;
pinctrl-names = "default";
clocks = <&mstp7_clks R8A7792_CLK_DU0>, <&mstp7_clks R8A7792_CLK_DU1>,
<&x1_clk>, <&x2_clk>;
clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&x1_clk>, <&x2_clk>;
clock-names = "du.0", "du.1", "dclkin.0", "dclkin.1";
status = "okay";

3
arch/arm/boot/dts/r8a7792-wheat.dts
View File

@@ -305,8 +305,7 @@ &du {
pinctrl-0 = <&du0_pins &du1_pins>;
pinctrl-names = "default";
clocks = <&mstp7_clks R8A7792_CLK_DU0>, <&mstp7_clks R8A7792_CLK_DU1>,
<&osc2_clk>;
clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&osc2_clk>;
clock-names = "du.0", "du.1", "dclkin.0";
status = "okay";

378
arch/arm/boot/dts/r8a7792.dtsi
View File

@@ -8,7 +8,7 @@
* kind, whether express or implied.
*/
#include <dt-bindings/clock/r8a7792-clock.h>
#include <dt-bindings/clock/r8a7792-cpg-mssr.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/r8a7792-sysc.h>
@@ -46,7 +46,7 @@ cpu0: cpu@0 {
compatible = "arm,cortex-a15";
reg = <0>;
clock-frequency = <1000000000>;
clocks = <&z_clk>;
clocks = <&cpg CPG_CORE R8A7792_CLK_Z>;
power-domains = <&sysc R8A7792_PD_CA15_CPU0>;
next-level-cache = <&L2_CA15>;
};
@@ -92,9 +92,10 @@ gic: interrupt-controller@f1001000 {
<0 0xf1006000 0 0x2000>;
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
IRQ_TYPE_LEVEL_HIGH)>;
clocks = <&mstp4_clks R8A7792_CLK_INTC_SYS>;
clocks = <&cpg CPG_MOD 408>;
clock-names = "clk";
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
resets = <&cpg 408>;
};
irqc: interrupt-controller@e61c0000 {
@@ -106,8 +107,9 @@ irqc: interrupt-controller@e61c0000 {
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp4_clks R8A7792_CLK_IRQC>;
clocks = <&cpg CPG_MOD 407>;
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
resets = <&cpg 407>;
};
timer {
@@ -153,8 +155,9 @@ gpio0: gpio@e6050000 {
gpio-ranges = <&pfc 0 0 29>;
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&mstp9_clks R8A7792_CLK_GPIO0>;
clocks = <&cpg CPG_MOD 912>;
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
resets = <&cpg 912>;
};
gpio1: gpio@e6051000 {
@@ -167,8 +170,9 @@ gpio1: gpio@e6051000 {
gpio-ranges = <&pfc 0 32 23>;
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&mstp9_clks R8A7792_CLK_GPIO1>;
clocks = <&cpg CPG_MOD 911>;
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
resets = <&cpg 911>;
};
gpio2: gpio@e6052000 {
@@ -181,8 +185,9 @@ gpio2: gpio@e6052000 {
gpio-ranges = <&pfc 0 64 32>;
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&mstp9_clks R8A7792_CLK_GPIO2>;
clocks = <&cpg CPG_MOD 910>;
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
resets = <&cpg 910>;
};
gpio3: gpio@e6053000 {
@@ -195,8 +200,9 @@ gpio3: gpio@e6053000 {
gpio-ranges = <&pfc 0 96 28>;
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&mstp9_clks R8A7792_CLK_GPIO3>;
clocks = <&cpg CPG_MOD 909>;
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
resets = <&cpg 909>;
};
gpio4: gpio@e6054000 {
@@ -209,8 +215,9 @@ gpio4: gpio@e6054000 {
gpio-ranges = <&pfc 0 128 17>;
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&mstp9_clks R8A7792_CLK_GPIO4>;
clocks = <&cpg CPG_MOD 908>;
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
resets = <&cpg 908>;
};
gpio5: gpio@e6055000 {
@@ -223,8 +230,9 @@ gpio5: gpio@e6055000 {
gpio-ranges = <&pfc 0 160 17>;
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&mstp9_clks R8A7792_CLK_GPIO5>;
clocks = <&cpg CPG_MOD 907>;
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
resets = <&cpg 907>;
};
gpio6: gpio@e6055100 {
@@ -237,8 +245,9 @@ gpio6: gpio@e6055100 {
gpio-ranges = <&pfc 0 192 17>;
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&mstp9_clks R8A7792_CLK_GPIO6>;
clocks = <&cpg CPG_MOD 905>;
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
resets = <&cpg 905>;
};
gpio7: gpio@e6055200 {
@@ -251,8 +260,9 @@ gpio7: gpio@e6055200 {
gpio-ranges = <&pfc 0 224 17>;
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&mstp9_clks R8A7792_CLK_GPIO7>;
clocks = <&cpg CPG_MOD 904>;
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
resets = <&cpg 904>;
};
gpio8: gpio@e6055300 {
@@ -265,8 +275,9 @@ gpio8: gpio@e6055300 {
gpio-ranges = <&pfc 0 256 17>;
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&mstp9_clks R8A7792_CLK_GPIO8>;
clocks = <&cpg CPG_MOD 921>;
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
resets = <&cpg 921>;
};
gpio9: gpio@e6055400 {
@@ -279,8 +290,9 @@ gpio9: gpio@e6055400 {
gpio-ranges = <&pfc 0 288 17>;
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&mstp9_clks R8A7792_CLK_GPIO9>;
clocks = <&cpg CPG_MOD 919>;
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
resets = <&cpg 919>;
};
gpio10: gpio@e6055500 {
@@ -293,8 +305,9 @@ gpio10: gpio@e6055500 {
gpio-ranges = <&pfc 0 320 32>;
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&mstp9_clks R8A7792_CLK_GPIO10>;
clocks = <&cpg CPG_MOD 914>;
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
resets = <&cpg 914>;
};
gpio11: gpio@e6055600 {
@@ -307,8 +320,9 @@ gpio11: gpio@e6055600 {
gpio-ranges = <&pfc 0 352 30>;
#interrupt-cells = <2>;
interrupt-controller;
clocks = <&mstp9_clks R8A7792_CLK_GPIO11>;
clocks = <&cpg CPG_MOD 913>;
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
resets = <&cpg 913>;
};
dmac0: dma-controller@e6700000 {
@@ -336,9 +350,10 @@ GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
"ch4", "ch5", "ch6", "ch7",
"ch8", "ch9", "ch10", "ch11",
"ch12", "ch13", "ch14";
clocks = <&mstp2_clks R8A7792_CLK_SYS_DMAC0>;
clocks = <&cpg CPG_MOD 219>;
clock-names = "fck";
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
resets = <&cpg 219>;
#dma-cells = <1>;
dma-channels = <15>;
};
@@ -368,9 +383,10 @@ GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
"ch4", "ch5", "ch6", "ch7",
"ch8", "ch9", "ch10", "ch11",
"ch12", "ch13", "ch14";
clocks = <&mstp2_clks R8A7792_CLK_SYS_DMAC1>;
clocks = <&cpg CPG_MOD 218>;
clock-names = "fck";
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
resets = <&cpg 218>;
#dma-cells = <1>;
dma-channels = <15>;
};
@@ -380,13 +396,14 @@ scif0: serial@e6e60000 {
"renesas,rcar-gen2-scif", "renesas,scif";
reg = <0 0xe6e60000 0 64>;
interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp7_clks R8A7792_CLK_SCIF0>, <&zs_clk>,
<&scif_clk>;
clocks = <&cpg CPG_MOD 721>,
<&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
<&dmac1 0x29>, <&dmac1 0x2a>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
resets = <&cpg 721>;
status = "disabled";
};
@@ -395,13 +412,14 @@ scif1: serial@e6e68000 {
"renesas,rcar-gen2-scif", "renesas,scif";
reg = <0 0xe6e68000 0 64>;
interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp7_clks R8A7792_CLK_SCIF1>, <&zs_clk>,
<&scif_clk>;
clocks = <&cpg CPG_MOD 720>,
<&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
<&dmac1 0x2d>, <&dmac1 0x2e>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
resets = <&cpg 720>;
status = "disabled";
};
@@ -410,13 +428,14 @@ scif2: serial@e6e58000 {
"renesas,rcar-gen2-scif", "renesas,scif";
reg = <0 0xe6e58000 0 64>;
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp7_clks R8A7792_CLK_SCIF2>, <&zs_clk>,
<&scif_clk>;
clocks = <&cpg CPG_MOD 719>,
<&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
<&dmac1 0x2b>, <&dmac1 0x2c>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
resets = <&cpg 719>;
status = "disabled";
};
@@ -425,13 +444,14 @@ scif3: serial@e6ea8000 {
"renesas,rcar-gen2-scif", "renesas,scif";
reg = <0 0xe6ea8000 0 64>;
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp7_clks R8A7792_CLK_SCIF3>, <&zs_clk>,
<&scif_clk>;
clocks = <&cpg CPG_MOD 718>,
<&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
<&dmac1 0x2f>, <&dmac1 0x30>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
resets = <&cpg 718>;
status = "disabled";
};
@@ -440,13 +460,14 @@ hscif0: serial@e62c0000 {
"renesas,rcar-gen2-hscif", "renesas,hscif";
reg = <0 0xe62c0000 0 96>;
interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp7_clks R8A7792_CLK_HSCIF0>, <&zs_clk>,
<&scif_clk>;
clocks = <&cpg CPG_MOD 717>,
<&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
<&dmac1 0x39>, <&dmac1 0x3a>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
resets = <&cpg 717>;
status = "disabled";
};
@@ -455,13 +476,14 @@ hscif1: serial@e62c8000 {
"renesas,rcar-gen2-hscif", "renesas,hscif";
reg = <0 0xe62c8000 0 96>;
interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp7_clks R8A7792_CLK_HSCIF1>, <&zs_clk>,
<&scif_clk>;
clocks = <&cpg CPG_MOD 716>,
<&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
<&dmac1 0x4d>, <&dmac1 0x4e>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
resets = <&cpg 716>;
status = "disabled";
};
@@ -490,8 +512,9 @@ sdhi0: sd@ee100000 {
dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
<&dmac1 0xcd>, <&dmac1 0xce>;
dma-names = "tx", "rx", "tx", "rx";
clocks = <&mstp3_clks R8A7792_CLK_SDHI0>;
clocks = <&cpg CPG_MOD 314>;
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
resets = <&cpg 314>;
status = "disabled";
};
@@ -500,8 +523,9 @@ jpu: jpeg-codec@fe980000 {
"renesas,rcar-gen2-jpu";
reg = <0 0xfe980000 0 0x10300>;
interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp1_clks R8A7792_CLK_JPU>;
clocks = <&cpg CPG_MOD 106>;
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
resets = <&cpg 106>;
};
avb: ethernet@e6800000 {
@@ -509,8 +533,9 @@ avb: ethernet@e6800000 {
"renesas,etheravb-rcar-gen2";
reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp8_clks R8A7792_CLK_ETHERAVB>;
clocks = <&cpg CPG_MOD 812>;
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
resets = <&cpg 812>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -522,8 +547,9 @@ i2c0: i2c@e6508000 {
"renesas,rcar-gen2-i2c";
reg = <0 0xe6508000 0 0x40>;
interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp9_clks R8A7792_CLK_I2C0>;
clocks = <&cpg CPG_MOD 931>;
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
resets = <&cpg 931>;
i2c-scl-internal-delay-ns = <6>;
#address-cells = <1>;
#size-cells = <0>;
@@ -535,8 +561,9 @@ i2c1: i2c@e6518000 {
"renesas,rcar-gen2-i2c";
reg = <0 0xe6518000 0 0x40>;
interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp9_clks R8A7792_CLK_I2C1>;
clocks = <&cpg CPG_MOD 930>;
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
resets = <&cpg 930>;
i2c-scl-internal-delay-ns = <6>;
#address-cells = <1>;
#size-cells = <0>;
@@ -548,8 +575,9 @@ i2c2: i2c@e6530000 {
"renesas,rcar-gen2-i2c";
reg = <0 0xe6530000 0 0x40>;
interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp9_clks R8A7792_CLK_I2C2>;
clocks = <&cpg CPG_MOD 929>;
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
resets = <&cpg 929>;
i2c-scl-internal-delay-ns = <6>;
#address-cells = <1>;
#size-cells = <0>;
@@ -561,8 +589,9 @@ i2c3: i2c@e6540000 {
"renesas,rcar-gen2-i2c";
reg = <0 0xe6540000 0 0x40>;
interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp9_clks R8A7792_CLK_I2C3>;
clocks = <&cpg CPG_MOD 928>;
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
resets = <&cpg 928>;
i2c-scl-internal-delay-ns = <6>;
#address-cells = <1>;
#size-cells = <0>;
@@ -574,8 +603,9 @@ i2c4: i2c@e6520000 {
"renesas,rcar-gen2-i2c";
reg = <0 0xe6520000 0 0x40>;
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp9_clks R8A7792_CLK_I2C4>;
clocks = <&cpg CPG_MOD 927>;
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
resets = <&cpg 927>;
i2c-scl-internal-delay-ns = <6>;
#address-cells = <1>;
#size-cells = <0>;
@@ -587,8 +617,9 @@ i2c5: i2c@e6528000 {
"renesas,rcar-gen2-i2c";
reg = <0 0xe6528000 0 0x40>;
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp9_clks R8A7792_CLK_I2C5>;
clocks = <&cpg CPG_MOD 925>;
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
resets = <&cpg 925>;
i2c-scl-internal-delay-ns = <110>;
#address-cells = <1>;
#size-cells = <0>;
@@ -599,11 +630,12 @@ qspi: spi@e6b10000 {
compatible = "renesas,qspi-r8a7792", "renesas,qspi";
reg = <0 0xe6b10000 0 0x2c>;
interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp9_clks R8A7792_CLK_QSPI_MOD>;
clocks = <&cpg CPG_MOD 917>;
dmas = <&dmac0 0x17>, <&dmac0 0x18>,
<&dmac1 0x17>, <&dmac1 0x18>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
resets = <&cpg 917>;
num-cs = <1>;
#address-cells = <1>;
#size-cells = <0>;
@@ -615,11 +647,12 @@ msiof0: spi@e6e20000 {
"renesas,rcar-gen2-msiof";
reg = <0 0xe6e20000 0 0x0064>;
interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp0_clks R8A7792_CLK_MSIOF0>;
clocks = <&cpg CPG_MOD 000>;
dmas = <&dmac0 0x51>, <&dmac0 0x52>,
<&dmac1 0x51>, <&dmac1 0x52>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
resets = <&cpg 000>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -630,11 +663,12 @@ msiof1: spi@e6e10000 {
"renesas,rcar-gen2-msiof";
reg = <0 0xe6e10000 0 0x0064>;
interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp2_clks R8A7792_CLK_MSIOF1>;
clocks = <&cpg CPG_MOD 208>;
dmas = <&dmac0 0x55>, <&dmac0 0x56>,
<&dmac1 0x55>, <&dmac1 0x56>;
dma-names = "tx", "rx", "tx", "rx";
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
resets = <&cpg 208>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -646,8 +680,8 @@ du: display@feb00000 {
reg-names = "du";
interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp7_clks R8A7792_CLK_DU0>,
<&mstp7_clks R8A7792_CLK_DU1>;
clocks = <&cpg CPG_MOD 724>,
<&cpg CPG_MOD 723>;
clock-names = "du.0", "du.1";
status = "disabled";
@@ -673,10 +707,11 @@ can0: can@e6e80000 {
"renesas,rcar-gen2-can";
reg = <0 0xe6e80000 0 0x1000>;
interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp9_clks R8A7792_CLK_CAN0>,
<&rcan_clk>, <&can_clk>;
clocks = <&cpg CPG_MOD 916>,
<&cpg CPG_CORE R8A7792_CLK_RCAN>, <&can_clk>;
clock-names = "clkp1", "clkp2", "can_clk";
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
resets = <&cpg 916>;
status = "disabled";
};
@@ -685,10 +720,11 @@ can1: can@e6e88000 {
"renesas,rcar-gen2-can";
reg = <0 0xe6e88000 0 0x1000>;
interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp9_clks R8A7792_CLK_CAN1>,
<&rcan_clk>, <&can_clk>;
clocks = <&cpg CPG_MOD 915>,
<&cpg CPG_CORE R8A7792_CLK_RCAN>, <&can_clk>;
clock-names = "clkp1", "clkp2", "can_clk";
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
resets = <&cpg 915>;
status = "disabled";
};
@@ -697,8 +733,9 @@ vin0: video@e6ef0000 {
"renesas,rcar-gen2-vin";
reg = <0 0xe6ef0000 0 0x1000>;
interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp8_clks R8A7792_CLK_VIN0>;
clocks = <&cpg CPG_MOD 811>;
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
resets = <&cpg 811>;
status = "disabled";
};
@@ -707,8 +744,9 @@ vin1: video@e6ef1000 {
"renesas,rcar-gen2-vin";
reg = <0 0xe6ef1000 0 0x1000>;
interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp8_clks R8A7792_CLK_VIN1>;
clocks = <&cpg CPG_MOD 810>;
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
resets = <&cpg 810>;
status = "disabled";
};
@@ -717,8 +755,9 @@ vin2: video@e6ef2000 {
"renesas,rcar-gen2-vin";
reg = <0 0xe6ef2000 0 0x1000>;
interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp8_clks R8A7792_CLK_VIN2>;
clocks = <&cpg CPG_MOD 809>;
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
resets = <&cpg 809>;
status = "disabled";
};
@@ -727,8 +766,9 @@ vin3: video@e6ef3000 {
"renesas,rcar-gen2-vin";
reg = <0 0xe6ef3000 0 0x1000>;
interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp8_clks R8A7792_CLK_VIN3>;
clocks = <&cpg CPG_MOD 808>;
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
resets = <&cpg 808>;
status = "disabled";
};
@@ -737,8 +777,9 @@ vin4: video@e6ef4000 {
"renesas,rcar-gen2-vin";
reg = <0 0xe6ef4000 0 0x1000>;
interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp8_clks R8A7792_CLK_VIN4>;
clocks = <&cpg CPG_MOD 805>;
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
resets = <&cpg 805>;
status = "disabled";
};
@@ -747,8 +788,9 @@ vin5: video@e6ef5000 {
"renesas,rcar-gen2-vin";
reg = <0 0xe6ef5000 0 0x1000>;
interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp8_clks R8A7792_CLK_VIN5>;
clocks = <&cpg CPG_MOD 804>;
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
resets = <&cpg 804>;
status = "disabled";
};
@@ -756,245 +798,37 @@ vsp1@fe928000 {
compatible = "renesas,vsp1";
reg = <0 0xfe928000 0 0x8000>;
interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp1_clks R8A7792_CLK_VSP1_SY>;
clocks = <&cpg CPG_MOD 131>;
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
resets = <&cpg 131>;
};
vsp1@fe930000 {
compatible = "renesas,vsp1";
reg = <0 0xfe930000 0 0x8000>;
interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp1_clks R8A7792_CLK_VSP1DU0>;
clocks = <&cpg CPG_MOD 128>;
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
resets = <&cpg 128>;
};
vsp1@fe938000 {
compatible = "renesas,vsp1";
reg = <0 0xfe938000 0 0x8000>;
interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp1_clks R8A7792_CLK_VSP1DU1>;
clocks = <&cpg CPG_MOD 127>;
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
resets = <&cpg 127>;
};
/* Special CPG clocks */
cpg_clocks: cpg_clocks@e6150000 {
compatible = "renesas,r8a7792-cpg-clocks",
"renesas,rcar-gen2-cpg-clocks";
cpg: clock-controller@e6150000 {
compatible = "renesas,r8a7792-cpg-mssr";
reg = <0 0xe6150000 0 0x1000>;
clocks = <&extal_clk>;
#clock-cells = <1>;
clock-output-names = "main", "pll0", "pll1", "pll3",
"lb", "qspi";
clock-names = "extal";
#clock-cells = <2>;
#power-domain-cells = <0>;
};
/* Fixed factor clocks */
pll1_div2_clk: pll1_div2 {
compatible = "fixed-factor-clock";
clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
#clock-cells = <0>;
clock-div = <2>;
clock-mult = <1>;
};
z_clk: z {
compatible = "fixed-factor-clock";
clocks = <&cpg_clocks R8A7792_CLK_PLL0>;
#clock-cells = <0>;
clock-div = <1>;
clock-mult = <1>;
};
zx_clk: zx {
compatible = "fixed-factor-clock";
clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
#clock-cells = <0>;
clock-div = <3>;
clock-mult = <1>;
};
zs_clk: zs {
compatible = "fixed-factor-clock";
clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
#clock-cells = <0>;
clock-div = <6>;
clock-mult = <1>;
};
hp_clk: hp {
compatible = "fixed-factor-clock";
clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
#clock-cells = <0>;
clock-div = <12>;
clock-mult = <1>;
};
p_clk: p {
compatible = "fixed-factor-clock";
clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
#clock-cells = <0>;
clock-div = <24>;
clock-mult = <1>;
};
cp_clk: cp {
compatible = "fixed-factor-clock";
clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
#clock-cells = <0>;
clock-div = <48>;
clock-mult = <1>;
};
mp_clk: mp {
compatible = "fixed-factor-clock";
clocks = <&pll1_div2_clk>;
#clock-cells = <0>;
clock-div = <15>;
clock-mult = <1>;
};
m2_clk: m2 {
compatible = "fixed-factor-clock";
clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
#clock-cells = <0>;
clock-div = <8>;
clock-mult = <1>;
};
sd_clk: sd {
compatible = "fixed-factor-clock";
clocks = <&pll1_div2_clk>;
#clock-cells = <0>;
clock-div = <8>;
clock-mult = <1>;
};
rcan_clk: rcan {
compatible = "fixed-factor-clock";
clocks = <&pll1_div2_clk>;
#clock-cells = <0>;
clock-div = <49>;
clock-mult = <1>;
};
zg_clk: zg {
compatible = "fixed-factor-clock";
clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
#clock-cells = <0>;
clock-div = <5>;
clock-mult = <1>;
};
/* Gate clocks */
mstp0_clks: mstp0_clks@e6150130 {
compatible = "renesas,r8a7792-mstp-clocks",
"renesas,cpg-mstp-clocks";
reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
clocks = <&mp_clk>;
#clock-cells = <1>;
clock-indices = <R8A7792_CLK_MSIOF0>;
clock-output-names = "msiof0";
};
mstp1_clks: mstp1_clks@e6150134 {
compatible = "renesas,r8a7792-mstp-clocks",
"renesas,cpg-mstp-clocks";
reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
clocks = <&m2_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>;
#clock-cells = <1>;
clock-indices = <
R8A7792_CLK_JPU
R8A7792_CLK_VSP1DU1 R8A7792_CLK_VSP1DU0
R8A7792_CLK_VSP1_SY
>;
clock-output-names = "jpu", "vsp1du1", "vsp1du0",
"vsp1-sy";
};
mstp2_clks: mstp2_clks@e6150138 {
compatible = "renesas,r8a7792-mstp-clocks",
"renesas,cpg-mstp-clocks";
reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
clocks = <&mp_clk>, <&zs_clk>, <&zs_clk>;
#clock-cells = <1>;
clock-indices = <
R8A7792_CLK_MSIOF1
R8A7792_CLK_SYS_DMAC1 R8A7792_CLK_SYS_DMAC0
>;
clock-output-names = "msiof1", "sys-dmac1", "sys-dmac0";
};
mstp3_clks: mstp3_clks@e615013c {
compatible = "renesas,r8a7792-mstp-clocks",
"renesas,cpg-mstp-clocks";
reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
clocks = <&sd_clk>;
#clock-cells = <1>;
renesas,clock-indices = <R8A7792_CLK_SDHI0>;
clock-output-names = "sdhi0";
};
mstp4_clks: mstp4_clks@e6150140 {
compatible = "renesas,r8a7792-mstp-clocks",
"renesas,cpg-mstp-clocks";
reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
clocks = <&cp_clk>, <&zs_clk>;
#clock-cells = <1>;
clock-indices = <
R8A7792_CLK_IRQC R8A7792_CLK_INTC_SYS
>;
clock-output-names = "irqc", "intc-sys";
};
mstp7_clks: mstp7_clks@e615014c {
compatible = "renesas,r8a7792-mstp-clocks",
"renesas,cpg-mstp-clocks";
reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
clocks = <&zs_clk>, <&zs_clk>, <&p_clk>, <&p_clk>,
<&p_clk>, <&p_clk>, <&zx_clk>, <&zx_clk>;
#clock-cells = <1>;
clock-indices = <
R8A7792_CLK_HSCIF1 R8A7792_CLK_HSCIF0
R8A7792_CLK_SCIF3 R8A7792_CLK_SCIF2
R8A7792_CLK_SCIF1 R8A7792_CLK_SCIF0
R8A7792_CLK_DU1 R8A7792_CLK_DU0
>;
clock-output-names = "hscif1", "hscif0", "scif3",
"scif2", "scif1", "scif0",
"du1", "du0";
};
mstp8_clks: mstp8_clks@e6150990 {
compatible = "renesas,r8a7792-mstp-clocks",
"renesas,cpg-mstp-clocks";
reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
clocks = <&zg_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>,
<&zg_clk>, <&zg_clk>, <&hp_clk>;
#clock-cells = <1>;
clock-indices = <
R8A7792_CLK_VIN5 R8A7792_CLK_VIN4
R8A7792_CLK_VIN3 R8A7792_CLK_VIN2
R8A7792_CLK_VIN1 R8A7792_CLK_VIN0
R8A7792_CLK_ETHERAVB
>;
clock-output-names = "vin5", "vin4", "vin3", "vin2",
"vin1", "vin0", "etheravb";
};
mstp9_clks: mstp9_clks@e6150994 {
compatible = "renesas,r8a7792-mstp-clocks",
"renesas,cpg-mstp-clocks";
reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
<&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
<&cp_clk>, <&cp_clk>, <&p_clk>, <&p_clk>,
<&cpg_clocks R8A7792_CLK_QSPI>,
<&cp_clk>, <&cp_clk>, <&hp_clk>, <&hp_clk>,
<&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>;
#clock-cells = <1>;
clock-indices = <
R8A7792_CLK_GPIO7 R8A7792_CLK_GPIO6
R8A7792_CLK_GPIO5 R8A7792_CLK_GPIO4
R8A7792_CLK_GPIO3 R8A7792_CLK_GPIO2
R8A7792_CLK_GPIO1 R8A7792_CLK_GPIO0
R8A7792_CLK_GPIO11 R8A7792_CLK_GPIO10
R8A7792_CLK_CAN1 R8A7792_CLK_CAN0
R8A7792_CLK_QSPI_MOD
R8A7792_CLK_GPIO9 R8A7792_CLK_GPIO8
R8A7792_CLK_I2C5 R8A7792_CLK_I2C4
R8A7792_CLK_I2C3 R8A7792_CLK_I2C2
R8A7792_CLK_I2C1 R8A7792_CLK_I2C0
>;
clock-output-names =
"gpio7", "gpio6", "gpio5", "gpio4",
"gpio3", "gpio2", "gpio1", "gpio0",
"gpio11", "gpio10", "can1", "can0",
"qspi_mod", "gpio9", "gpio8",
"i2c5", "i2c4", "i2c3", "i2c2",
"i2c1", "i2c0";
};
};
/* External root clock */

4
arch/arm/boot/dts/r8a7793-gose.dts
View File

@@ -303,9 +303,7 @@ &du {
pinctrl-names = "default";
status = "okay";
clocks = <&mstp7_clks R8A7793_CLK_DU0>,
<&mstp7_clks R8A7793_CLK_DU1>,
<&mstp7_clks R8A7793_CLK_LVDS0>,
clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&cpg CPG_MOD 726>,
<&x13_clk>, <&x2_clk>;
clock-names = "du.0", "du.1", "lvds.0",
"dclkin.0", "dclkin.1";

626
arch/arm/boot/dts/r8a7793.dtsi
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File diff suppressed because it is too large Load Diff

7
arch/arm/boot/dts/r8a7794-alt.dts
View File

@@ -167,8 +167,7 @@ &du {
pinctrl-names = "default";
status = "okay";
clocks = <&mstp7_clks R8A7794_CLK_DU0>,
<&mstp7_clks R8A7794_CLK_DU1>,
clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>,
<&x13_clk>, <&x2_clk>;
clock-names = "du.0", "du.1", "dclkin.0", "dclkin.1";
@@ -305,7 +304,7 @@ &sdhi0 {
vmmc-supply = <&vcc_sdhi0>;
vqmmc-supply = <&vccq_sdhi0>;
cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio6 7 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>;
sd-uhs-sdr50;
sd-uhs-sdr104;
status = "okay";
@@ -319,7 +318,7 @@ &sdhi1 {
vmmc-supply = <&vcc_sdhi1>;
vqmmc-supply = <&vccq_sdhi1>;
cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio6 15 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>;
sd-uhs-sdr50;
status = "okay";
};

3
arch/arm/boot/dts/r8a7794-silk.dts
View File

@@ -423,8 +423,7 @@ &du {
pinctrl-names = "default";
status = "okay";
clocks = <&mstp7_clks R8A7794_CLK_DU0>,
<&mstp7_clks R8A7794_CLK_DU1>,
clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>,
<&x2_clk>, <&x3_clk>;
clock-names = "du.0", "du.1", "dclkin.0", "dclkin.1";

696
arch/arm/boot/dts/r8a7794.dtsi
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File diff suppressed because it is too large Load Diff