From 5802c420636559ffd37095d2886f6964d9b55b11 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 18 Aug 2017 11:11:34 +0200 Subject: [PATCH 01/48] ARM: dts: r8a7790: Convert to new CPG/MSSR bindings Convert the R-Car H2 SoC from the old "Renesas R-Car Gen2 Clock Pulse Generator (CPG)", "Renesas CPG DIV6 Clock", and "Renesas CPG Module Stop (MSTP) Clocks" DT bindings to the new unified "Renesas Clock Pulse Generator / Module Standby and Software Reset" DT bindings. This simplifies the DTS files, and allows to add support for reset control later. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7790-lager.dts | 7 +- arch/arm/boot/dts/r8a7790.dtsi | 557 +++++----------------------- 2 files changed, 99 insertions(+), 465 deletions(-) diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts index ba100a6f67ca..e3d27783b6b5 100644 --- a/arch/arm/boot/dts/r8a7790-lager.dts +++ b/arch/arm/boot/dts/r8a7790-lager.dts @@ -316,11 +316,8 @@ &du { pinctrl-names = "default"; status = "okay"; - clocks = <&mstp7_clks R8A7790_CLK_DU0>, - <&mstp7_clks R8A7790_CLK_DU1>, - <&mstp7_clks R8A7790_CLK_DU2>, - <&mstp7_clks R8A7790_CLK_LVDS0>, - <&mstp7_clks R8A7790_CLK_LVDS1>, + clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&cpg CPG_MOD 722>, + <&cpg CPG_MOD 726>, <&cpg CPG_MOD 725>, <&x13_clk>, <&x2_clk>; clock-names = "du.0", "du.1", "du.2", "lvds.0", "lvds.1", "dclkin.0", "dclkin.1"; diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index 16358bf8d1db..5a31dfc0c316 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -10,7 +10,7 @@ * kind, whether express or implied. */ -#include +#include #include #include #include @@ -52,7 +52,7 @@ cpu0: cpu@0 { reg = <0>; clock-frequency = <1300000000>; voltage-tolerance = <1>; /* 1% */ - clocks = <&cpg_clocks R8A7790_CLK_Z>; + clocks = <&cpg CPG_CORE R8A7790_CLK_Z>; clock-latency = <300000>; /* 300 us */ power-domains = <&sysc R8A7790_PD_CA15_CPU0>; next-level-cache = <&L2_CA15>; @@ -185,7 +185,7 @@ gic: interrupt-controller@f1001000 { <0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>; interrupts = ; - clocks = <&mstp4_clks R8A7790_CLK_INTC_SYS>; + clocks = <&cpg CPG_MOD 408>; clock-names = "clk"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; }; @@ -199,7 +199,7 @@ gpio0: gpio@e6050000 { gpio-ranges = <&pfc 0 0 32>; #interrupt-cells = <2>; interrupt-controller; - clocks = <&mstp9_clks R8A7790_CLK_GPIO0>; + clocks = <&cpg CPG_MOD 912>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; }; @@ -212,7 +212,7 @@ gpio1: gpio@e6051000 { gpio-ranges = <&pfc 0 32 30>; #interrupt-cells = <2>; interrupt-controller; - clocks = <&mstp9_clks R8A7790_CLK_GPIO1>; + clocks = <&cpg CPG_MOD 911>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; }; @@ -225,7 +225,7 @@ gpio2: gpio@e6052000 { gpio-ranges = <&pfc 0 64 30>; #interrupt-cells = <2>; interrupt-controller; - clocks = <&mstp9_clks R8A7790_CLK_GPIO2>; + clocks = <&cpg CPG_MOD 910>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; }; @@ -238,7 +238,7 @@ gpio3: gpio@e6053000 { gpio-ranges = <&pfc 0 96 32>; #interrupt-cells = <2>; interrupt-controller; - clocks = <&mstp9_clks R8A7790_CLK_GPIO3>; + clocks = <&cpg CPG_MOD 909>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; }; @@ -251,7 +251,7 @@ gpio4: gpio@e6054000 { gpio-ranges = <&pfc 0 128 32>; #interrupt-cells = <2>; interrupt-controller; - clocks = <&mstp9_clks R8A7790_CLK_GPIO4>; + clocks = <&cpg CPG_MOD 908>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; }; @@ -264,7 +264,7 @@ gpio5: gpio@e6055000 { gpio-ranges = <&pfc 0 160 32>; #interrupt-cells = <2>; interrupt-controller; - clocks = <&mstp9_clks R8A7790_CLK_GPIO5>; + clocks = <&cpg CPG_MOD 907>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; }; @@ -274,7 +274,7 @@ thermal: thermal@e61f0000 { "renesas,rcar-thermal"; reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>; interrupts = ; - clocks = <&mstp5_clks R8A7790_CLK_THERMAL>; + clocks = <&cpg CPG_MOD 522>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; #thermal-sensor-cells = <0>; }; @@ -292,7 +292,7 @@ cmt0: timer@ffca0000 { reg = <0 0xffca0000 0 0x1004>; interrupts = , ; - clocks = <&mstp1_clks R8A7790_CLK_CMT0>; + clocks = <&cpg CPG_MOD 124>; clock-names = "fck"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; @@ -312,7 +312,7 @@ cmt1: timer@e6130000 { , , ; - clocks = <&mstp3_clks R8A7790_CLK_CMT1>; + clocks = <&cpg CPG_MOD 329>; clock-names = "fck"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; @@ -330,7 +330,7 @@ irqc0: interrupt-controller@e61c0000 { , , ; - clocks = <&mstp4_clks R8A7790_CLK_IRQC>; + clocks = <&cpg CPG_MOD 407>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; }; @@ -358,7 +358,7 @@ GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10", "ch11", "ch12", "ch13", "ch14"; - clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC0>; + clocks = <&cpg CPG_MOD 219>; clock-names = "fck"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; #dma-cells = <1>; @@ -389,7 +389,7 @@ GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10", "ch11", "ch12", "ch13", "ch14"; - clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC1>; + clocks = <&cpg CPG_MOD 218>; clock-names = "fck"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; #dma-cells = <1>; @@ -418,7 +418,7 @@ GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10", "ch11", "ch12"; - clocks = <&mstp5_clks R8A7790_CLK_AUDIO_DMAC0>; + clocks = <&cpg CPG_MOD 502>; clock-names = "fck"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; #dma-cells = <1>; @@ -447,7 +447,7 @@ GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10", "ch11", "ch12"; - clocks = <&mstp5_clks R8A7790_CLK_AUDIO_DMAC1>; + clocks = <&cpg CPG_MOD 501>; clock-names = "fck"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; #dma-cells = <1>; @@ -460,7 +460,7 @@ usb_dmac0: dma-controller@e65a0000 { interrupts = ; interrupt-names = "ch0", "ch1"; - clocks = <&mstp3_clks R8A7790_CLK_USBDMAC0>; + clocks = <&cpg CPG_MOD 330>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; #dma-cells = <1>; dma-channels = <2>; @@ -472,7 +472,7 @@ usb_dmac1: dma-controller@e65b0000 { interrupts = ; interrupt-names = "ch0", "ch1"; - clocks = <&mstp3_clks R8A7790_CLK_USBDMAC1>; + clocks = <&cpg CPG_MOD 331>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; #dma-cells = <1>; dma-channels = <2>; @@ -484,7 +484,7 @@ i2c0: i2c@e6508000 { compatible = "renesas,i2c-r8a7790", "renesas,rcar-gen2-i2c"; reg = <0 0xe6508000 0 0x40>; interrupts = ; - clocks = <&mstp9_clks R8A7790_CLK_I2C0>; + clocks = <&cpg CPG_MOD 931>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; i2c-scl-internal-delay-ns = <110>; status = "disabled"; @@ -496,7 +496,7 @@ i2c1: i2c@e6518000 { compatible = "renesas,i2c-r8a7790", "renesas,rcar-gen2-i2c"; reg = <0 0xe6518000 0 0x40>; interrupts = ; - clocks = <&mstp9_clks R8A7790_CLK_I2C1>; + clocks = <&cpg CPG_MOD 930>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; i2c-scl-internal-delay-ns = <6>; status = "disabled"; @@ -508,7 +508,7 @@ i2c2: i2c@e6530000 { compatible = "renesas,i2c-r8a7790", "renesas,rcar-gen2-i2c"; reg = <0 0xe6530000 0 0x40>; interrupts = ; - clocks = <&mstp9_clks R8A7790_CLK_I2C2>; + clocks = <&cpg CPG_MOD 929>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; i2c-scl-internal-delay-ns = <6>; status = "disabled"; @@ -520,7 +520,7 @@ i2c3: i2c@e6540000 { compatible = "renesas,i2c-r8a7790", "renesas,rcar-gen2-i2c"; reg = <0 0xe6540000 0 0x40>; interrupts = ; - clocks = <&mstp9_clks R8A7790_CLK_I2C3>; + clocks = <&cpg CPG_MOD 928>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; i2c-scl-internal-delay-ns = <110>; status = "disabled"; @@ -533,7 +533,7 @@ iic0: i2c@e6500000 { "renesas,rmobile-iic"; reg = <0 0xe6500000 0 0x425>; interrupts = ; - clocks = <&mstp3_clks R8A7790_CLK_IIC0>; + clocks = <&cpg CPG_MOD 318>; dmas = <&dmac0 0x61>, <&dmac0 0x62>, <&dmac1 0x61>, <&dmac1 0x62>; dma-names = "tx", "rx", "tx", "rx"; @@ -548,7 +548,7 @@ iic1: i2c@e6510000 { "renesas,rmobile-iic"; reg = <0 0xe6510000 0 0x425>; interrupts = ; - clocks = <&mstp3_clks R8A7790_CLK_IIC1>; + clocks = <&cpg CPG_MOD 323>; dmas = <&dmac0 0x65>, <&dmac0 0x66>, <&dmac1 0x65>, <&dmac1 0x66>; dma-names = "tx", "rx", "tx", "rx"; @@ -563,7 +563,7 @@ iic2: i2c@e6520000 { "renesas,rmobile-iic"; reg = <0 0xe6520000 0 0x425>; interrupts = ; - clocks = <&mstp3_clks R8A7790_CLK_IIC2>; + clocks = <&cpg CPG_MOD 300>; dmas = <&dmac0 0x69>, <&dmac0 0x6a>, <&dmac1 0x69>, <&dmac1 0x6a>; dma-names = "tx", "rx", "tx", "rx"; @@ -578,7 +578,7 @@ iic3: i2c@e60b0000 { "renesas,rmobile-iic"; reg = <0 0xe60b0000 0 0x425>; interrupts = ; - clocks = <&mstp9_clks R8A7790_CLK_IICDVFS>; + clocks = <&cpg CPG_MOD 926>; dmas = <&dmac0 0x77>, <&dmac0 0x78>, <&dmac1 0x77>, <&dmac1 0x78>; dma-names = "tx", "rx", "tx", "rx"; @@ -590,7 +590,7 @@ mmcif0: mmc@ee200000 { compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif"; reg = <0 0xee200000 0 0x80>; interrupts = ; - clocks = <&mstp3_clks R8A7790_CLK_MMCIF0>; + clocks = <&cpg CPG_MOD 315>; dmas = <&dmac0 0xd1>, <&dmac0 0xd2>, <&dmac1 0xd1>, <&dmac1 0xd2>; dma-names = "tx", "rx", "tx", "rx"; @@ -604,7 +604,7 @@ mmcif1: mmc@ee220000 { compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif"; reg = <0 0xee220000 0 0x80>; interrupts = ; - clocks = <&mstp3_clks R8A7790_CLK_MMCIF1>; + clocks = <&cpg CPG_MOD 305>; dmas = <&dmac0 0xe1>, <&dmac0 0xe2>, <&dmac1 0xe1>, <&dmac1 0xe2>; dma-names = "tx", "rx", "tx", "rx"; @@ -623,7 +623,7 @@ sdhi0: sd@ee100000 { compatible = "renesas,sdhi-r8a7790"; reg = <0 0xee100000 0 0x328>; interrupts = ; - clocks = <&mstp3_clks R8A7790_CLK_SDHI0>; + clocks = <&cpg CPG_MOD 314>; dmas = <&dmac0 0xcd>, <&dmac0 0xce>, <&dmac1 0xcd>, <&dmac1 0xce>; dma-names = "tx", "rx", "tx", "rx"; @@ -636,7 +636,7 @@ sdhi1: sd@ee120000 { compatible = "renesas,sdhi-r8a7790"; reg = <0 0xee120000 0 0x328>; interrupts = ; - clocks = <&mstp3_clks R8A7790_CLK_SDHI1>; + clocks = <&cpg CPG_MOD 313>; dmas = <&dmac0 0xc9>, <&dmac0 0xca>, <&dmac1 0xc9>, <&dmac1 0xca>; dma-names = "tx", "rx", "tx", "rx"; @@ -649,7 +649,7 @@ sdhi2: sd@ee140000 { compatible = "renesas,sdhi-r8a7790"; reg = <0 0xee140000 0 0x100>; interrupts = ; - clocks = <&mstp3_clks R8A7790_CLK_SDHI2>; + clocks = <&cpg CPG_MOD 312>; dmas = <&dmac0 0xc1>, <&dmac0 0xc2>, <&dmac1 0xc1>, <&dmac1 0xc2>; dma-names = "tx", "rx", "tx", "rx"; @@ -662,7 +662,7 @@ sdhi3: sd@ee160000 { compatible = "renesas,sdhi-r8a7790"; reg = <0 0xee160000 0 0x100>; interrupts = ; - clocks = <&mstp3_clks R8A7790_CLK_SDHI3>; + clocks = <&cpg CPG_MOD 311>; dmas = <&dmac0 0xd3>, <&dmac0 0xd4>, <&dmac1 0xd3>, <&dmac1 0xd4>; dma-names = "tx", "rx", "tx", "rx"; @@ -676,7 +676,7 @@ scifa0: serial@e6c40000 { "renesas,rcar-gen2-scifa", "renesas,scifa"; reg = <0 0xe6c40000 0 64>; interrupts = ; - clocks = <&mstp2_clks R8A7790_CLK_SCIFA0>; + clocks = <&cpg CPG_MOD 204>; clock-names = "fck"; dmas = <&dmac0 0x21>, <&dmac0 0x22>, <&dmac1 0x21>, <&dmac1 0x22>; @@ -690,7 +690,7 @@ scifa1: serial@e6c50000 { "renesas,rcar-gen2-scifa", "renesas,scifa"; reg = <0 0xe6c50000 0 64>; interrupts = ; - clocks = <&mstp2_clks R8A7790_CLK_SCIFA1>; + clocks = <&cpg CPG_MOD 203>; clock-names = "fck"; dmas = <&dmac0 0x25>, <&dmac0 0x26>, <&dmac1 0x25>, <&dmac1 0x26>; @@ -704,7 +704,7 @@ scifa2: serial@e6c60000 { "renesas,rcar-gen2-scifa", "renesas,scifa"; reg = <0 0xe6c60000 0 64>; interrupts = ; - clocks = <&mstp2_clks R8A7790_CLK_SCIFA2>; + clocks = <&cpg CPG_MOD 202>; clock-names = "fck"; dmas = <&dmac0 0x27>, <&dmac0 0x28>, <&dmac1 0x27>, <&dmac1 0x28>; @@ -718,7 +718,7 @@ scifb0: serial@e6c20000 { "renesas,rcar-gen2-scifb", "renesas,scifb"; reg = <0 0xe6c20000 0 0x100>; interrupts = ; - clocks = <&mstp2_clks R8A7790_CLK_SCIFB0>; + clocks = <&cpg CPG_MOD 206>; clock-names = "fck"; dmas = <&dmac0 0x3d>, <&dmac0 0x3e>, <&dmac1 0x3d>, <&dmac1 0x3e>; @@ -732,7 +732,7 @@ scifb1: serial@e6c30000 { "renesas,rcar-gen2-scifb", "renesas,scifb"; reg = <0 0xe6c30000 0 0x100>; interrupts = ; - clocks = <&mstp2_clks R8A7790_CLK_SCIFB1>; + clocks = <&cpg CPG_MOD 207>; clock-names = "fck"; dmas = <&dmac0 0x19>, <&dmac0 0x1a>, <&dmac1 0x19>, <&dmac1 0x1a>; @@ -746,7 +746,7 @@ scifb2: serial@e6ce0000 { "renesas,rcar-gen2-scifb", "renesas,scifb"; reg = <0 0xe6ce0000 0 0x100>; interrupts = ; - clocks = <&mstp2_clks R8A7790_CLK_SCIFB2>; + clocks = <&cpg CPG_MOD 216>; clock-names = "fck"; dmas = <&dmac0 0x1d>, <&dmac0 0x1e>, <&dmac1 0x1d>, <&dmac1 0x1e>; @@ -760,7 +760,7 @@ scif0: serial@e6e60000 { "renesas,scif"; reg = <0 0xe6e60000 0 64>; interrupts = ; - clocks = <&mstp7_clks R8A7790_CLK_SCIF0>, <&zs_clk>, + clocks = <&cpg CPG_MOD 721>, <&cpg CPG_CORE R8A7790_CLK_ZS>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x29>, <&dmac0 0x2a>, @@ -775,7 +775,7 @@ scif1: serial@e6e68000 { "renesas,scif"; reg = <0 0xe6e68000 0 64>; interrupts = ; - clocks = <&mstp7_clks R8A7790_CLK_SCIF1>, <&zs_clk>, + clocks = <&cpg CPG_MOD 720>, <&cpg CPG_CORE R8A7790_CLK_ZS>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x2d>, <&dmac0 0x2e>, @@ -790,7 +790,7 @@ scif2: serial@e6e56000 { "renesas,scif"; reg = <0 0xe6e56000 0 64>; interrupts = ; - clocks = <&mstp3_clks R8A7790_CLK_SCIF2>, <&zs_clk>, + clocks = <&cpg CPG_MOD 310>, <&cpg CPG_CORE R8A7790_CLK_ZS>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x2b>, <&dmac0 0x2c>, @@ -805,7 +805,7 @@ hscif0: serial@e62c0000 { "renesas,rcar-gen2-hscif", "renesas,hscif"; reg = <0 0xe62c0000 0 96>; interrupts = ; - clocks = <&mstp7_clks R8A7790_CLK_HSCIF0>, <&zs_clk>, + clocks = <&cpg CPG_MOD 717>, <&cpg CPG_CORE R8A7790_CLK_ZS>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x39>, <&dmac0 0x3a>, @@ -820,7 +820,7 @@ hscif1: serial@e62c8000 { "renesas,rcar-gen2-hscif", "renesas,hscif"; reg = <0 0xe62c8000 0 96>; interrupts = ; - clocks = <&mstp7_clks R8A7790_CLK_HSCIF1>, <&zs_clk>, + clocks = <&cpg CPG_MOD 716>, <&cpg CPG_CORE R8A7790_CLK_ZS>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x4d>, <&dmac0 0x4e>, @@ -852,7 +852,7 @@ ether: ethernet@ee700000 { compatible = "renesas,ether-r8a7790"; reg = <0 0xee700000 0 0x400>; interrupts = ; - clocks = <&mstp8_clks R8A7790_CLK_ETHER>; + clocks = <&cpg CPG_MOD 813>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; phy-mode = "rmii"; #address-cells = <1>; @@ -865,7 +865,7 @@ avb: ethernet@e6800000 { "renesas,etheravb-rcar-gen2"; reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; interrupts = ; - clocks = <&mstp8_clks R8A7790_CLK_ETHERAVB>; + clocks = <&cpg CPG_MOD 812>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; #address-cells = <1>; #size-cells = <0>; @@ -876,7 +876,7 @@ sata0: sata@ee300000 { compatible = "renesas,sata-r8a7790", "renesas,rcar-gen2-sata"; reg = <0 0xee300000 0 0x2000>; interrupts = ; - clocks = <&mstp8_clks R8A7790_CLK_SATA0>; + clocks = <&cpg CPG_MOD 815>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; status = "disabled"; }; @@ -885,7 +885,7 @@ sata1: sata@ee500000 { compatible = "renesas,sata-r8a7790", "renesas,rcar-gen2-sata"; reg = <0 0xee500000 0 0x2000>; interrupts = ; - clocks = <&mstp8_clks R8A7790_CLK_SATA1>; + clocks = <&cpg CPG_MOD 814>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; status = "disabled"; }; @@ -894,7 +894,7 @@ hsusb: usb@e6590000 { compatible = "renesas,usbhs-r8a7790", "renesas,rcar-gen2-usbhs"; reg = <0 0xe6590000 0 0x100>; interrupts = ; - clocks = <&mstp7_clks R8A7790_CLK_HSUSB>; + clocks = <&cpg CPG_MOD 704>; dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, <&usb_dmac1 0>, <&usb_dmac1 1>; dma-names = "ch0", "ch1", "ch2", "ch3"; @@ -911,7 +911,7 @@ usbphy: usb-phy@e6590100 { reg = <0 0xe6590100 0 0x100>; #address-cells = <1>; #size-cells = <0>; - clocks = <&mstp7_clks R8A7790_CLK_HSUSB>; + clocks = <&cpg CPG_MOD 704>; clock-names = "usbhs"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; status = "disabled"; @@ -930,7 +930,7 @@ vin0: video@e6ef0000 { compatible = "renesas,vin-r8a7790", "renesas,rcar-gen2-vin"; reg = <0 0xe6ef0000 0 0x1000>; interrupts = ; - clocks = <&mstp8_clks R8A7790_CLK_VIN0>; + clocks = <&cpg CPG_MOD 811>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; status = "disabled"; }; @@ -939,7 +939,7 @@ vin1: video@e6ef1000 { compatible = "renesas,vin-r8a7790", "renesas,rcar-gen2-vin"; reg = <0 0xe6ef1000 0 0x1000>; interrupts = ; - clocks = <&mstp8_clks R8A7790_CLK_VIN1>; + clocks = <&cpg CPG_MOD 810>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; status = "disabled"; }; @@ -948,7 +948,7 @@ vin2: video@e6ef2000 { compatible = "renesas,vin-r8a7790", "renesas,rcar-gen2-vin"; reg = <0 0xe6ef2000 0 0x1000>; interrupts = ; - clocks = <&mstp8_clks R8A7790_CLK_VIN2>; + clocks = <&cpg CPG_MOD 809>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; status = "disabled"; }; @@ -957,7 +957,7 @@ vin3: video@e6ef3000 { compatible = "renesas,vin-r8a7790", "renesas,rcar-gen2-vin"; reg = <0 0xe6ef3000 0 0x1000>; interrupts = ; - clocks = <&mstp8_clks R8A7790_CLK_VIN3>; + clocks = <&cpg CPG_MOD 808>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; status = "disabled"; }; @@ -966,7 +966,7 @@ vsp1@fe920000 { compatible = "renesas,vsp1"; reg = <0 0xfe920000 0 0x8000>; interrupts = ; - clocks = <&mstp1_clks R8A7790_CLK_VSP1_R>; + clocks = <&cpg CPG_MOD 130>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; }; @@ -974,7 +974,7 @@ vsp1@fe928000 { compatible = "renesas,vsp1"; reg = <0 0xfe928000 0 0x8000>; interrupts = ; - clocks = <&mstp1_clks R8A7790_CLK_VSP1_S>; + clocks = <&cpg CPG_MOD 131>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; }; @@ -982,7 +982,7 @@ vsp1@fe930000 { compatible = "renesas,vsp1"; reg = <0 0xfe930000 0 0x8000>; interrupts = ; - clocks = <&mstp1_clks R8A7790_CLK_VSP1_DU0>; + clocks = <&cpg CPG_MOD 128>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; }; @@ -990,7 +990,7 @@ vsp1@fe938000 { compatible = "renesas,vsp1"; reg = <0 0xfe938000 0 0x8000>; interrupts = ; - clocks = <&mstp1_clks R8A7790_CLK_VSP1_DU1>; + clocks = <&cpg CPG_MOD 127>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; }; @@ -1003,11 +1003,9 @@ du: display@feb00000 { interrupts = , , ; - clocks = <&mstp7_clks R8A7790_CLK_DU0>, - <&mstp7_clks R8A7790_CLK_DU1>, - <&mstp7_clks R8A7790_CLK_DU2>, - <&mstp7_clks R8A7790_CLK_LVDS0>, - <&mstp7_clks R8A7790_CLK_LVDS1>; + clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, + <&cpg CPG_MOD 722>, <&cpg CPG_MOD 726>, + <&cpg CPG_MOD 725>; clock-names = "du.0", "du.1", "du.2", "lvds.0", "lvds.1"; status = "disabled"; @@ -1037,8 +1035,8 @@ can0: can@e6e80000 { compatible = "renesas,can-r8a7790", "renesas,rcar-gen2-can"; reg = <0 0xe6e80000 0 0x1000>; interrupts = ; - clocks = <&mstp9_clks R8A7790_CLK_RCAN0>, - <&cpg_clocks R8A7790_CLK_RCAN>, <&can_clk>; + clocks = <&cpg CPG_MOD 916>, <&cpg CPG_CORE R8A7790_CLK_RCAN>, + <&can_clk>; clock-names = "clkp1", "clkp2", "can_clk"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; status = "disabled"; @@ -1048,8 +1046,8 @@ can1: can@e6e88000 { compatible = "renesas,can-r8a7790", "renesas,rcar-gen2-can"; reg = <0 0xe6e88000 0 0x1000>; interrupts = ; - clocks = <&mstp9_clks R8A7790_CLK_RCAN1>, - <&cpg_clocks R8A7790_CLK_RCAN>, <&can_clk>; + clocks = <&cpg CPG_MOD 915>, <&cpg CPG_CORE R8A7790_CLK_RCAN>, + <&can_clk>; clock-names = "clkp1", "clkp2", "can_clk"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; status = "disabled"; @@ -1059,7 +1057,7 @@ jpu: jpeg-codec@fe980000 { compatible = "renesas,jpu-r8a7790", "renesas,rcar-gen2-jpu"; reg = <0 0xfe980000 0 0x10300>; interrupts = ; - clocks = <&mstp1_clks R8A7790_CLK_JPU>; + clocks = <&cpg CPG_MOD 106>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; }; @@ -1126,376 +1124,14 @@ can_clk: can { clock-frequency = <0>; }; - /* Special CPG clocks */ - cpg_clocks: cpg_clocks@e6150000 { - compatible = "renesas,r8a7790-cpg-clocks", - "renesas,rcar-gen2-cpg-clocks"; + cpg: clock-controller@e6150000 { + compatible = "renesas,r8a7790-cpg-mssr"; reg = <0 0xe6150000 0 0x1000>; - clocks = <&extal_clk &usb_extal_clk>; - #clock-cells = <1>; - clock-output-names = "main", "pll0", "pll1", "pll3", - "lb", "qspi", "sdh", "sd0", "sd1", - "z", "rcan", "adsp"; + clocks = <&extal_clk>, <&usb_extal_clk>; + clock-names = "extal", "usb_extal"; + #clock-cells = <2>; #power-domain-cells = <0>; }; - - /* Variable factor clocks */ - sd2_clk: sd2@e6150078 { - compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock"; - reg = <0 0xe6150078 0 4>; - clocks = <&pll1_div2_clk>; - #clock-cells = <0>; - }; - sd3_clk: sd3@e615026c { - compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock"; - reg = <0 0xe615026c 0 4>; - clocks = <&pll1_div2_clk>; - #clock-cells = <0>; - }; - mmc0_clk: mmc0@e6150240 { - compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock"; - reg = <0 0xe6150240 0 4>; - clocks = <&pll1_div2_clk>; - #clock-cells = <0>; - }; - mmc1_clk: mmc1@e6150244 { - compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock"; - reg = <0 0xe6150244 0 4>; - clocks = <&pll1_div2_clk>; - #clock-cells = <0>; - }; - ssp_clk: ssp@e6150248 { - compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock"; - reg = <0 0xe6150248 0 4>; - clocks = <&pll1_div2_clk>; - #clock-cells = <0>; - }; - ssprs_clk: ssprs@e615024c { - compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock"; - reg = <0 0xe615024c 0 4>; - clocks = <&pll1_div2_clk>; - #clock-cells = <0>; - }; - - /* Fixed factor clocks */ - pll1_div2_clk: pll1_div2 { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7790_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <2>; - clock-mult = <1>; - }; - z2_clk: z2 { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7790_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <2>; - clock-mult = <1>; - }; - zg_clk: zg { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7790_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <3>; - clock-mult = <1>; - }; - zx_clk: zx { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7790_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <3>; - clock-mult = <1>; - }; - zs_clk: zs { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7790_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <6>; - clock-mult = <1>; - }; - hp_clk: hp { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7790_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <12>; - clock-mult = <1>; - }; - i_clk: i { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7790_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <2>; - clock-mult = <1>; - }; - b_clk: b { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7790_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <12>; - clock-mult = <1>; - }; - p_clk: p { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7790_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <24>; - clock-mult = <1>; - }; - cl_clk: cl { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7790_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <48>; - clock-mult = <1>; - }; - m2_clk: m2 { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7790_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <8>; - clock-mult = <1>; - }; - imp_clk: imp { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7790_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <4>; - clock-mult = <1>; - }; - rclk_clk: rclk { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7790_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <(48 * 1024)>; - clock-mult = <1>; - }; - oscclk_clk: oscclk { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7790_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <(12 * 1024)>; - clock-mult = <1>; - }; - zb3_clk: zb3 { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7790_CLK_PLL3>; - #clock-cells = <0>; - clock-div = <4>; - clock-mult = <1>; - }; - zb3d2_clk: zb3d2 { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7790_CLK_PLL3>; - #clock-cells = <0>; - clock-div = <8>; - clock-mult = <1>; - }; - ddr_clk: ddr { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7790_CLK_PLL3>; - #clock-cells = <0>; - clock-div = <8>; - clock-mult = <1>; - }; - mp_clk: mp { - compatible = "fixed-factor-clock"; - clocks = <&pll1_div2_clk>; - #clock-cells = <0>; - clock-div = <15>; - clock-mult = <1>; - }; - cp_clk: cp { - compatible = "fixed-factor-clock"; - clocks = <&extal_clk>; - #clock-cells = <0>; - clock-div = <2>; - clock-mult = <1>; - }; - - /* Gate clocks */ - mstp0_clks: mstp0_clks@e6150130 { - compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>; - clocks = <&mp_clk>; - #clock-cells = <1>; - clock-indices = ; - clock-output-names = "msiof0"; - }; - mstp1_clks: mstp1_clks@e6150134 { - compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>; - clocks = <&zs_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, <&m2_clk>, - <&zs_clk>, <&p_clk>, <&zg_clk>, <&zs_clk>, <&zs_clk>, - <&zs_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>, - <&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7790_CLK_VCP1 R8A7790_CLK_VCP0 R8A7790_CLK_VPC1 - R8A7790_CLK_VPC0 R8A7790_CLK_JPU R8A7790_CLK_SSP1 - R8A7790_CLK_TMU1 R8A7790_CLK_3DG R8A7790_CLK_2DDMAC - R8A7790_CLK_FDP1_2 R8A7790_CLK_FDP1_1 R8A7790_CLK_FDP1_0 - R8A7790_CLK_TMU3 R8A7790_CLK_TMU2 R8A7790_CLK_CMT0 - R8A7790_CLK_TMU0 R8A7790_CLK_VSP1_DU1 R8A7790_CLK_VSP1_DU0 - R8A7790_CLK_VSP1_R R8A7790_CLK_VSP1_S - >; - clock-output-names = - "vcp1", "vcp0", "vpc1", "vpc0", "jpu", "ssp1", - "tmu1", "3dg", "2ddmac", "fdp1-2", "fdp1-1", - "fdp1-0", "tmu3", "tmu2", "cmt0", "tmu0", - "vsp1-du1", "vsp1-du0", "vsp1-rt", "vsp1-sy"; - }; - mstp2_clks: mstp2_clks@e6150138 { - compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>; - clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, - <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&zs_clk>, - <&zs_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7790_CLK_SCIFA2 R8A7790_CLK_SCIFA1 R8A7790_CLK_SCIFA0 - R8A7790_CLK_MSIOF2 R8A7790_CLK_SCIFB0 R8A7790_CLK_SCIFB1 - R8A7790_CLK_MSIOF1 R8A7790_CLK_MSIOF3 R8A7790_CLK_SCIFB2 - R8A7790_CLK_SYS_DMAC1 R8A7790_CLK_SYS_DMAC0 - >; - clock-output-names = - "scifa2", "scifa1", "scifa0", "msiof2", "scifb0", - "scifb1", "msiof1", "msiof3", "scifb2", - "sys-dmac1", "sys-dmac0"; - }; - mstp3_clks: mstp3_clks@e615013c { - compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; - clocks = <&hp_clk>, <&cp_clk>, <&mmc1_clk>, <&p_clk>, <&sd3_clk>, - <&sd2_clk>, <&cpg_clocks R8A7790_CLK_SD1>, <&cpg_clocks R8A7790_CLK_SD0>, <&mmc0_clk>, - <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>, - <&hp_clk>, <&hp_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7790_CLK_IIC2 R8A7790_CLK_TPU0 R8A7790_CLK_MMCIF1 R8A7790_CLK_SCIF2 R8A7790_CLK_SDHI3 - R8A7790_CLK_SDHI2 R8A7790_CLK_SDHI1 R8A7790_CLK_SDHI0 R8A7790_CLK_MMCIF0 - R8A7790_CLK_IIC0 R8A7790_CLK_PCIEC R8A7790_CLK_IIC1 R8A7790_CLK_SSUSB R8A7790_CLK_CMT1 - R8A7790_CLK_USBDMAC0 R8A7790_CLK_USBDMAC1 - >; - clock-output-names = - "iic2", "tpu0", "mmcif1", "scif2", "sdhi3", - "sdhi2", "sdhi1", "sdhi0", "mmcif0", - "iic0", "pciec", "iic1", "ssusb", "cmt1", - "usbdmac0", "usbdmac1"; - }; - mstp4_clks: mstp4_clks@e6150140 { - compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>; - clocks = <&cp_clk>, <&zs_clk>; - #clock-cells = <1>; - clock-indices = ; - clock-output-names = "irqc", "intc-sys"; - }; - mstp5_clks: mstp5_clks@e6150144 { - compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>; - clocks = <&hp_clk>, <&hp_clk>, <&cpg_clocks R8A7790_CLK_ADSP>, - <&extal_clk>, <&p_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7790_CLK_AUDIO_DMAC0 R8A7790_CLK_AUDIO_DMAC1 - R8A7790_CLK_ADSP_MOD R8A7790_CLK_THERMAL - R8A7790_CLK_PWM - >; - clock-output-names = "audmac0", "audmac1", "adsp_mod", - "thermal", "pwm"; - }; - mstp7_clks: mstp7_clks@e615014c { - compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>; - clocks = <&mp_clk>, <&hp_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>, - <&p_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>, - <&zx_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7790_CLK_EHCI R8A7790_CLK_HSUSB R8A7790_CLK_HSCIF1 - R8A7790_CLK_HSCIF0 R8A7790_CLK_SCIF1 R8A7790_CLK_SCIF0 - R8A7790_CLK_DU2 R8A7790_CLK_DU1 R8A7790_CLK_DU0 - R8A7790_CLK_LVDS1 R8A7790_CLK_LVDS0 - >; - clock-output-names = - "ehci", "hsusb", "hscif1", "hscif0", "scif1", - "scif0", "du2", "du1", "du0", "lvds1", "lvds0"; - }; - mstp8_clks: mstp8_clks@e6150990 { - compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>; - clocks = <&hp_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>, - <&zg_clk>, <&hp_clk>, <&p_clk>, <&zs_clk>, - <&zs_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7790_CLK_MLB R8A7790_CLK_VIN3 R8A7790_CLK_VIN2 - R8A7790_CLK_VIN1 R8A7790_CLK_VIN0 - R8A7790_CLK_ETHERAVB R8A7790_CLK_ETHER - R8A7790_CLK_SATA1 R8A7790_CLK_SATA0 - >; - clock-output-names = - "mlb", "vin3", "vin2", "vin1", "vin0", - "etheravb", "ether", "sata1", "sata0"; - }; - mstp9_clks: mstp9_clks@e6150994 { - compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>; - clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, - <&cp_clk>, <&cp_clk>, <&cp_clk>, - <&p_clk>, <&p_clk>, <&cpg_clocks R8A7790_CLK_QSPI>, <&cp_clk>, - <&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7790_CLK_GPIO5 R8A7790_CLK_GPIO4 R8A7790_CLK_GPIO3 - R8A7790_CLK_GPIO2 R8A7790_CLK_GPIO1 R8A7790_CLK_GPIO0 - R8A7790_CLK_RCAN1 R8A7790_CLK_RCAN0 R8A7790_CLK_QSPI_MOD R8A7790_CLK_IICDVFS - R8A7790_CLK_I2C3 R8A7790_CLK_I2C2 R8A7790_CLK_I2C1 R8A7790_CLK_I2C0 - >; - clock-output-names = - "gpio5", "gpio4", "gpio3", "gpio2", "gpio1", "gpio0", - "rcan1", "rcan0", "qspi_mod", "iic3", - "i2c3", "i2c2", "i2c1", "i2c0"; - }; - mstp10_clks: mstp10_clks@e6150998 { - compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>; - clocks = <&p_clk>, - <&mstp10_clks R8A7790_CLK_SSI_ALL>, <&mstp10_clks R8A7790_CLK_SSI_ALL>, - <&mstp10_clks R8A7790_CLK_SSI_ALL>, <&mstp10_clks R8A7790_CLK_SSI_ALL>, - <&mstp10_clks R8A7790_CLK_SSI_ALL>, <&mstp10_clks R8A7790_CLK_SSI_ALL>, - <&mstp10_clks R8A7790_CLK_SSI_ALL>, <&mstp10_clks R8A7790_CLK_SSI_ALL>, - <&mstp10_clks R8A7790_CLK_SSI_ALL>, <&mstp10_clks R8A7790_CLK_SSI_ALL>, - <&p_clk>, - <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>, - <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>, - <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>, - <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>, - <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>, - <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>, - <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>; - - #clock-cells = <1>; - clock-indices = < - R8A7790_CLK_SSI_ALL - R8A7790_CLK_SSI9 R8A7790_CLK_SSI8 R8A7790_CLK_SSI7 R8A7790_CLK_SSI6 R8A7790_CLK_SSI5 - R8A7790_CLK_SSI4 R8A7790_CLK_SSI3 R8A7790_CLK_SSI2 R8A7790_CLK_SSI1 R8A7790_CLK_SSI0 - R8A7790_CLK_SCU_ALL - R8A7790_CLK_SCU_DVC1 R8A7790_CLK_SCU_DVC0 - R8A7790_CLK_SCU_CTU1_MIX1 R8A7790_CLK_SCU_CTU0_MIX0 - R8A7790_CLK_SCU_SRC9 R8A7790_CLK_SCU_SRC8 R8A7790_CLK_SCU_SRC7 R8A7790_CLK_SCU_SRC6 R8A7790_CLK_SCU_SRC5 - R8A7790_CLK_SCU_SRC4 R8A7790_CLK_SCU_SRC3 R8A7790_CLK_SCU_SRC2 R8A7790_CLK_SCU_SRC1 R8A7790_CLK_SCU_SRC0 - >; - clock-output-names = - "ssi-all", - "ssi9", "ssi8", "ssi7", "ssi6", "ssi5", - "ssi4", "ssi3", "ssi2", "ssi1", "ssi0", - "scu-all", - "scu-dvc1", "scu-dvc0", - "scu-ctu1-mix1", "scu-ctu0-mix0", - "scu-src9", "scu-src8", "scu-src7", "scu-src6", "scu-src5", - "scu-src4", "scu-src3", "scu-src2", "scu-src1", "scu-src0"; - }; }; prr: chipid@ff000044 { @@ -1518,7 +1154,7 @@ qspi: spi@e6b10000 { compatible = "renesas,qspi-r8a7790", "renesas,qspi"; reg = <0 0xe6b10000 0 0x2c>; interrupts = ; - clocks = <&mstp9_clks R8A7790_CLK_QSPI_MOD>; + clocks = <&cpg CPG_MOD 917>; dmas = <&dmac0 0x17>, <&dmac0 0x18>, <&dmac1 0x17>, <&dmac1 0x18>; dma-names = "tx", "rx", "tx", "rx"; @@ -1534,7 +1170,7 @@ msiof0: spi@e6e20000 { "renesas,rcar-gen2-msiof"; reg = <0 0xe6e20000 0 0x0064>; interrupts = ; - clocks = <&mstp0_clks R8A7790_CLK_MSIOF0>; + clocks = <&cpg CPG_MOD 0>; dmas = <&dmac0 0x51>, <&dmac0 0x52>, <&dmac1 0x51>, <&dmac1 0x52>; dma-names = "tx", "rx", "tx", "rx"; @@ -1549,7 +1185,7 @@ msiof1: spi@e6e10000 { "renesas,rcar-gen2-msiof"; reg = <0 0xe6e10000 0 0x0064>; interrupts = ; - clocks = <&mstp2_clks R8A7790_CLK_MSIOF1>; + clocks = <&cpg CPG_MOD 208>; dmas = <&dmac0 0x55>, <&dmac0 0x56>, <&dmac1 0x55>, <&dmac1 0x56>; dma-names = "tx", "rx", "tx", "rx"; @@ -1564,7 +1200,7 @@ msiof2: spi@e6e00000 { "renesas,rcar-gen2-msiof"; reg = <0 0xe6e00000 0 0x0064>; interrupts = ; - clocks = <&mstp2_clks R8A7790_CLK_MSIOF2>; + clocks = <&cpg CPG_MOD 205>; dmas = <&dmac0 0x41>, <&dmac0 0x42>, <&dmac1 0x41>, <&dmac1 0x42>; dma-names = "tx", "rx", "tx", "rx"; @@ -1579,7 +1215,7 @@ msiof3: spi@e6c90000 { "renesas,rcar-gen2-msiof"; reg = <0 0xe6c90000 0 0x0064>; interrupts = ; - clocks = <&mstp2_clks R8A7790_CLK_MSIOF3>; + clocks = <&cpg CPG_MOD 215>; dmas = <&dmac0 0x45>, <&dmac0 0x46>, <&dmac1 0x45>, <&dmac1 0x46>; dma-names = "tx", "rx", "tx", "rx"; @@ -1593,7 +1229,7 @@ xhci: usb@ee000000 { compatible = "renesas,xhci-r8a7790", "renesas,rcar-gen2-xhci"; reg = <0 0xee000000 0 0xc00>; interrupts = ; - clocks = <&mstp3_clks R8A7790_CLK_SSUSB>; + clocks = <&cpg CPG_MOD 328>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; phys = <&usb2 1>; phy-names = "usb"; @@ -1606,7 +1242,7 @@ pci0: pci@ee090000 { reg = <0 0xee090000 0 0xc00>, <0 0xee080000 0 0x1100>; interrupts = ; - clocks = <&mstp7_clks R8A7790_CLK_EHCI>; + clocks = <&cpg CPG_MOD 703>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; status = "disabled"; @@ -1639,7 +1275,7 @@ pci1: pci@ee0b0000 { reg = <0 0xee0b0000 0 0xc00>, <0 0xee0a0000 0 0x1100>; interrupts = ; - clocks = <&mstp7_clks R8A7790_CLK_EHCI>; + clocks = <&cpg CPG_MOD 703>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; status = "disabled"; @@ -1657,7 +1293,7 @@ pci1: pci@ee0b0000 { pci2: pci@ee0d0000 { compatible = "renesas,pci-r8a7790", "renesas,pci-rcar-gen2"; device_type = "pci"; - clocks = <&mstp7_clks R8A7790_CLK_EHCI>; + clocks = <&cpg CPG_MOD 703>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; reg = <0 0xee0d0000 0 0xc00>, <0 0xee0c0000 0 0x1100>; @@ -1707,7 +1343,7 @@ pciec: pcie@fe000000 { #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp3_clks R8A7790_CLK_PCIEC>, <&pcie_bus_clk>; + clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; clock-names = "pcie", "pcie_bus"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; status = "disabled"; @@ -1728,21 +1364,22 @@ rcar_sound: sound@ec500000 { <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/ reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; - clocks = <&mstp10_clks R8A7790_CLK_SSI_ALL>, - <&mstp10_clks R8A7790_CLK_SSI9>, <&mstp10_clks R8A7790_CLK_SSI8>, - <&mstp10_clks R8A7790_CLK_SSI7>, <&mstp10_clks R8A7790_CLK_SSI6>, - <&mstp10_clks R8A7790_CLK_SSI5>, <&mstp10_clks R8A7790_CLK_SSI4>, - <&mstp10_clks R8A7790_CLK_SSI3>, <&mstp10_clks R8A7790_CLK_SSI2>, - <&mstp10_clks R8A7790_CLK_SSI1>, <&mstp10_clks R8A7790_CLK_SSI0>, - <&mstp10_clks R8A7790_CLK_SCU_SRC9>, <&mstp10_clks R8A7790_CLK_SCU_SRC8>, - <&mstp10_clks R8A7790_CLK_SCU_SRC7>, <&mstp10_clks R8A7790_CLK_SCU_SRC6>, - <&mstp10_clks R8A7790_CLK_SCU_SRC5>, <&mstp10_clks R8A7790_CLK_SCU_SRC4>, - <&mstp10_clks R8A7790_CLK_SCU_SRC3>, <&mstp10_clks R8A7790_CLK_SCU_SRC2>, - <&mstp10_clks R8A7790_CLK_SCU_SRC1>, <&mstp10_clks R8A7790_CLK_SCU_SRC0>, - <&mstp10_clks R8A7790_CLK_SCU_CTU0_MIX0>, <&mstp10_clks R8A7790_CLK_SCU_CTU1_MIX1>, - <&mstp10_clks R8A7790_CLK_SCU_CTU0_MIX0>, <&mstp10_clks R8A7790_CLK_SCU_CTU1_MIX1>, - <&mstp10_clks R8A7790_CLK_SCU_DVC0>, <&mstp10_clks R8A7790_CLK_SCU_DVC1>, - <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, <&m2_clk>; + clocks = <&cpg CPG_MOD 1005>, + <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, + <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, + <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, + <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, + <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, + <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, + <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, + <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, + <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, + <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, + <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>, + <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>, + <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, + <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, + <&cpg CPG_CORE R8A7790_CLK_M2>; clock-names = "ssi-all", "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5", "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0", From 762dbc444ca240580f7eda5b9152d147cca608b3 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 18 Aug 2017 11:11:36 +0200 Subject: [PATCH 02/48] ARM: dts: r8a7792: Convert to new CPG/MSSR bindings Convert the R-Car V2H SoC from the old "Renesas R-Car Gen2 Clock Pulse Generator (CPG)" and "Renesas CPG Module Stop (MSTP) Clocks" DT bindings to the new unified "Renesas Clock Pulse Generator / Module Standby and Software Reset" DT bindings. This simplifies the DTS files, and allows to add support for reset control later. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7792-blanche.dts | 3 +- arch/arm/boot/dts/r8a7792-wheat.dts | 3 +- arch/arm/boot/dts/r8a7792.dtsi | 333 +++++--------------------- 3 files changed, 63 insertions(+), 276 deletions(-) diff --git a/arch/arm/boot/dts/r8a7792-blanche.dts b/arch/arm/boot/dts/r8a7792-blanche.dts index f3ea43b7b724..9b67dca6c9ef 100644 --- a/arch/arm/boot/dts/r8a7792-blanche.dts +++ b/arch/arm/boot/dts/r8a7792-blanche.dts @@ -310,8 +310,7 @@ &du { pinctrl-0 = <&du0_pins &du1_pins>; pinctrl-names = "default"; - clocks = <&mstp7_clks R8A7792_CLK_DU0>, <&mstp7_clks R8A7792_CLK_DU1>, - <&x1_clk>, <&x2_clk>; + clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&x1_clk>, <&x2_clk>; clock-names = "du.0", "du.1", "dclkin.0", "dclkin.1"; status = "okay"; diff --git a/arch/arm/boot/dts/r8a7792-wheat.dts b/arch/arm/boot/dts/r8a7792-wheat.dts index c24f26fdab1f..b9471b67b728 100644 --- a/arch/arm/boot/dts/r8a7792-wheat.dts +++ b/arch/arm/boot/dts/r8a7792-wheat.dts @@ -305,8 +305,7 @@ &du { pinctrl-0 = <&du0_pins &du1_pins>; pinctrl-names = "default"; - clocks = <&mstp7_clks R8A7792_CLK_DU0>, <&mstp7_clks R8A7792_CLK_DU1>, - <&osc2_clk>; + clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&osc2_clk>; clock-names = "du.0", "du.1", "dclkin.0"; status = "okay"; diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi index 2623f39bed2b..a209787d899a 100644 --- a/arch/arm/boot/dts/r8a7792.dtsi +++ b/arch/arm/boot/dts/r8a7792.dtsi @@ -8,7 +8,7 @@ * kind, whether express or implied. */ -#include +#include #include #include #include @@ -46,7 +46,7 @@ cpu0: cpu@0 { compatible = "arm,cortex-a15"; reg = <0>; clock-frequency = <1000000000>; - clocks = <&z_clk>; + clocks = <&cpg CPG_CORE R8A7792_CLK_Z>; power-domains = <&sysc R8A7792_PD_CA15_CPU0>; next-level-cache = <&L2_CA15>; }; @@ -92,7 +92,7 @@ gic: interrupt-controller@f1001000 { <0 0xf1006000 0 0x2000>; interrupts = ; - clocks = <&mstp4_clks R8A7792_CLK_INTC_SYS>; + clocks = <&cpg CPG_MOD 408>; clock-names = "clk"; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; }; @@ -106,7 +106,7 @@ irqc: interrupt-controller@e61c0000 { , , ; - clocks = <&mstp4_clks R8A7792_CLK_IRQC>; + clocks = <&cpg CPG_MOD 407>; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; }; @@ -153,7 +153,7 @@ gpio0: gpio@e6050000 { gpio-ranges = <&pfc 0 0 29>; #interrupt-cells = <2>; interrupt-controller; - clocks = <&mstp9_clks R8A7792_CLK_GPIO0>; + clocks = <&cpg CPG_MOD 912>; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; }; @@ -167,7 +167,7 @@ gpio1: gpio@e6051000 { gpio-ranges = <&pfc 0 32 23>; #interrupt-cells = <2>; interrupt-controller; - clocks = <&mstp9_clks R8A7792_CLK_GPIO1>; + clocks = <&cpg CPG_MOD 911>; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; }; @@ -181,7 +181,7 @@ gpio2: gpio@e6052000 { gpio-ranges = <&pfc 0 64 32>; #interrupt-cells = <2>; interrupt-controller; - clocks = <&mstp9_clks R8A7792_CLK_GPIO2>; + clocks = <&cpg CPG_MOD 910>; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; }; @@ -195,7 +195,7 @@ gpio3: gpio@e6053000 { gpio-ranges = <&pfc 0 96 28>; #interrupt-cells = <2>; interrupt-controller; - clocks = <&mstp9_clks R8A7792_CLK_GPIO3>; + clocks = <&cpg CPG_MOD 909>; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; }; @@ -209,7 +209,7 @@ gpio4: gpio@e6054000 { gpio-ranges = <&pfc 0 128 17>; #interrupt-cells = <2>; interrupt-controller; - clocks = <&mstp9_clks R8A7792_CLK_GPIO4>; + clocks = <&cpg CPG_MOD 908>; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; }; @@ -223,7 +223,7 @@ gpio5: gpio@e6055000 { gpio-ranges = <&pfc 0 160 17>; #interrupt-cells = <2>; interrupt-controller; - clocks = <&mstp9_clks R8A7792_CLK_GPIO5>; + clocks = <&cpg CPG_MOD 907>; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; }; @@ -237,7 +237,7 @@ gpio6: gpio@e6055100 { gpio-ranges = <&pfc 0 192 17>; #interrupt-cells = <2>; interrupt-controller; - clocks = <&mstp9_clks R8A7792_CLK_GPIO6>; + clocks = <&cpg CPG_MOD 905>; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; }; @@ -251,7 +251,7 @@ gpio7: gpio@e6055200 { gpio-ranges = <&pfc 0 224 17>; #interrupt-cells = <2>; interrupt-controller; - clocks = <&mstp9_clks R8A7792_CLK_GPIO7>; + clocks = <&cpg CPG_MOD 904>; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; }; @@ -265,7 +265,7 @@ gpio8: gpio@e6055300 { gpio-ranges = <&pfc 0 256 17>; #interrupt-cells = <2>; interrupt-controller; - clocks = <&mstp9_clks R8A7792_CLK_GPIO8>; + clocks = <&cpg CPG_MOD 921>; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; }; @@ -279,7 +279,7 @@ gpio9: gpio@e6055400 { gpio-ranges = <&pfc 0 288 17>; #interrupt-cells = <2>; interrupt-controller; - clocks = <&mstp9_clks R8A7792_CLK_GPIO9>; + clocks = <&cpg CPG_MOD 919>; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; }; @@ -293,7 +293,7 @@ gpio10: gpio@e6055500 { gpio-ranges = <&pfc 0 320 32>; #interrupt-cells = <2>; interrupt-controller; - clocks = <&mstp9_clks R8A7792_CLK_GPIO10>; + clocks = <&cpg CPG_MOD 914>; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; }; @@ -307,7 +307,7 @@ gpio11: gpio@e6055600 { gpio-ranges = <&pfc 0 352 30>; #interrupt-cells = <2>; interrupt-controller; - clocks = <&mstp9_clks R8A7792_CLK_GPIO11>; + clocks = <&cpg CPG_MOD 913>; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; }; @@ -336,7 +336,7 @@ GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10", "ch11", "ch12", "ch13", "ch14"; - clocks = <&mstp2_clks R8A7792_CLK_SYS_DMAC0>; + clocks = <&cpg CPG_MOD 219>; clock-names = "fck"; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; #dma-cells = <1>; @@ -368,7 +368,7 @@ GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10", "ch11", "ch12", "ch13", "ch14"; - clocks = <&mstp2_clks R8A7792_CLK_SYS_DMAC1>; + clocks = <&cpg CPG_MOD 218>; clock-names = "fck"; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; #dma-cells = <1>; @@ -380,8 +380,8 @@ scif0: serial@e6e60000 { "renesas,rcar-gen2-scif", "renesas,scif"; reg = <0 0xe6e60000 0 64>; interrupts = ; - clocks = <&mstp7_clks R8A7792_CLK_SCIF0>, <&zs_clk>, - <&scif_clk>; + clocks = <&cpg CPG_MOD 721>, + <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x29>, <&dmac0 0x2a>, <&dmac1 0x29>, <&dmac1 0x2a>; @@ -395,8 +395,8 @@ scif1: serial@e6e68000 { "renesas,rcar-gen2-scif", "renesas,scif"; reg = <0 0xe6e68000 0 64>; interrupts = ; - clocks = <&mstp7_clks R8A7792_CLK_SCIF1>, <&zs_clk>, - <&scif_clk>; + clocks = <&cpg CPG_MOD 720>, + <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x2d>, <&dmac0 0x2e>, <&dmac1 0x2d>, <&dmac1 0x2e>; @@ -410,8 +410,8 @@ scif2: serial@e6e58000 { "renesas,rcar-gen2-scif", "renesas,scif"; reg = <0 0xe6e58000 0 64>; interrupts = ; - clocks = <&mstp7_clks R8A7792_CLK_SCIF2>, <&zs_clk>, - <&scif_clk>; + clocks = <&cpg CPG_MOD 719>, + <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x2b>, <&dmac0 0x2c>, <&dmac1 0x2b>, <&dmac1 0x2c>; @@ -425,8 +425,8 @@ scif3: serial@e6ea8000 { "renesas,rcar-gen2-scif", "renesas,scif"; reg = <0 0xe6ea8000 0 64>; interrupts = ; - clocks = <&mstp7_clks R8A7792_CLK_SCIF3>, <&zs_clk>, - <&scif_clk>; + clocks = <&cpg CPG_MOD 718>, + <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x2f>, <&dmac0 0x30>, <&dmac1 0x2f>, <&dmac1 0x30>; @@ -440,8 +440,8 @@ hscif0: serial@e62c0000 { "renesas,rcar-gen2-hscif", "renesas,hscif"; reg = <0 0xe62c0000 0 96>; interrupts = ; - clocks = <&mstp7_clks R8A7792_CLK_HSCIF0>, <&zs_clk>, - <&scif_clk>; + clocks = <&cpg CPG_MOD 717>, + <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x39>, <&dmac0 0x3a>, <&dmac1 0x39>, <&dmac1 0x3a>; @@ -455,8 +455,8 @@ hscif1: serial@e62c8000 { "renesas,rcar-gen2-hscif", "renesas,hscif"; reg = <0 0xe62c8000 0 96>; interrupts = ; - clocks = <&mstp7_clks R8A7792_CLK_HSCIF1>, <&zs_clk>, - <&scif_clk>; + clocks = <&cpg CPG_MOD 716>, + <&cpg CPG_CORE R8A7792_CLK_ZS>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x4d>, <&dmac0 0x4e>, <&dmac1 0x4d>, <&dmac1 0x4e>; @@ -490,7 +490,7 @@ sdhi0: sd@ee100000 { dmas = <&dmac0 0xcd>, <&dmac0 0xce>, <&dmac1 0xcd>, <&dmac1 0xce>; dma-names = "tx", "rx", "tx", "rx"; - clocks = <&mstp3_clks R8A7792_CLK_SDHI0>; + clocks = <&cpg CPG_MOD 314>; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; status = "disabled"; }; @@ -500,7 +500,7 @@ jpu: jpeg-codec@fe980000 { "renesas,rcar-gen2-jpu"; reg = <0 0xfe980000 0 0x10300>; interrupts = ; - clocks = <&mstp1_clks R8A7792_CLK_JPU>; + clocks = <&cpg CPG_MOD 106>; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; }; @@ -509,7 +509,7 @@ avb: ethernet@e6800000 { "renesas,etheravb-rcar-gen2"; reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; interrupts = ; - clocks = <&mstp8_clks R8A7792_CLK_ETHERAVB>; + clocks = <&cpg CPG_MOD 812>; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; #address-cells = <1>; #size-cells = <0>; @@ -522,7 +522,7 @@ i2c0: i2c@e6508000 { "renesas,rcar-gen2-i2c"; reg = <0 0xe6508000 0 0x40>; interrupts = ; - clocks = <&mstp9_clks R8A7792_CLK_I2C0>; + clocks = <&cpg CPG_MOD 931>; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; i2c-scl-internal-delay-ns = <6>; #address-cells = <1>; @@ -535,7 +535,7 @@ i2c1: i2c@e6518000 { "renesas,rcar-gen2-i2c"; reg = <0 0xe6518000 0 0x40>; interrupts = ; - clocks = <&mstp9_clks R8A7792_CLK_I2C1>; + clocks = <&cpg CPG_MOD 930>; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; i2c-scl-internal-delay-ns = <6>; #address-cells = <1>; @@ -548,7 +548,7 @@ i2c2: i2c@e6530000 { "renesas,rcar-gen2-i2c"; reg = <0 0xe6530000 0 0x40>; interrupts = ; - clocks = <&mstp9_clks R8A7792_CLK_I2C2>; + clocks = <&cpg CPG_MOD 929>; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; i2c-scl-internal-delay-ns = <6>; #address-cells = <1>; @@ -561,7 +561,7 @@ i2c3: i2c@e6540000 { "renesas,rcar-gen2-i2c"; reg = <0 0xe6540000 0 0x40>; interrupts = ; - clocks = <&mstp9_clks R8A7792_CLK_I2C3>; + clocks = <&cpg CPG_MOD 928>; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; i2c-scl-internal-delay-ns = <6>; #address-cells = <1>; @@ -574,7 +574,7 @@ i2c4: i2c@e6520000 { "renesas,rcar-gen2-i2c"; reg = <0 0xe6520000 0 0x40>; interrupts = ; - clocks = <&mstp9_clks R8A7792_CLK_I2C4>; + clocks = <&cpg CPG_MOD 927>; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; i2c-scl-internal-delay-ns = <6>; #address-cells = <1>; @@ -587,7 +587,7 @@ i2c5: i2c@e6528000 { "renesas,rcar-gen2-i2c"; reg = <0 0xe6528000 0 0x40>; interrupts = ; - clocks = <&mstp9_clks R8A7792_CLK_I2C5>; + clocks = <&cpg CPG_MOD 925>; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; i2c-scl-internal-delay-ns = <110>; #address-cells = <1>; @@ -599,7 +599,7 @@ qspi: spi@e6b10000 { compatible = "renesas,qspi-r8a7792", "renesas,qspi"; reg = <0 0xe6b10000 0 0x2c>; interrupts = ; - clocks = <&mstp9_clks R8A7792_CLK_QSPI_MOD>; + clocks = <&cpg CPG_MOD 917>; dmas = <&dmac0 0x17>, <&dmac0 0x18>, <&dmac1 0x17>, <&dmac1 0x18>; dma-names = "tx", "rx", "tx", "rx"; @@ -615,7 +615,7 @@ msiof0: spi@e6e20000 { "renesas,rcar-gen2-msiof"; reg = <0 0xe6e20000 0 0x0064>; interrupts = ; - clocks = <&mstp0_clks R8A7792_CLK_MSIOF0>; + clocks = <&cpg CPG_MOD 000>; dmas = <&dmac0 0x51>, <&dmac0 0x52>, <&dmac1 0x51>, <&dmac1 0x52>; dma-names = "tx", "rx", "tx", "rx"; @@ -630,7 +630,7 @@ msiof1: spi@e6e10000 { "renesas,rcar-gen2-msiof"; reg = <0 0xe6e10000 0 0x0064>; interrupts = ; - clocks = <&mstp2_clks R8A7792_CLK_MSIOF1>; + clocks = <&cpg CPG_MOD 208>; dmas = <&dmac0 0x55>, <&dmac0 0x56>, <&dmac1 0x55>, <&dmac1 0x56>; dma-names = "tx", "rx", "tx", "rx"; @@ -646,8 +646,8 @@ du: display@feb00000 { reg-names = "du"; interrupts = , ; - clocks = <&mstp7_clks R8A7792_CLK_DU0>, - <&mstp7_clks R8A7792_CLK_DU1>; + clocks = <&cpg CPG_MOD 724>, + <&cpg CPG_MOD 723>; clock-names = "du.0", "du.1"; status = "disabled"; @@ -673,8 +673,8 @@ can0: can@e6e80000 { "renesas,rcar-gen2-can"; reg = <0 0xe6e80000 0 0x1000>; interrupts = ; - clocks = <&mstp9_clks R8A7792_CLK_CAN0>, - <&rcan_clk>, <&can_clk>; + clocks = <&cpg CPG_MOD 916>, + <&cpg CPG_CORE R8A7792_CLK_RCAN>, <&can_clk>; clock-names = "clkp1", "clkp2", "can_clk"; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; status = "disabled"; @@ -685,8 +685,8 @@ can1: can@e6e88000 { "renesas,rcar-gen2-can"; reg = <0 0xe6e88000 0 0x1000>; interrupts = ; - clocks = <&mstp9_clks R8A7792_CLK_CAN1>, - <&rcan_clk>, <&can_clk>; + clocks = <&cpg CPG_MOD 915>, + <&cpg CPG_CORE R8A7792_CLK_RCAN>, <&can_clk>; clock-names = "clkp1", "clkp2", "can_clk"; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; status = "disabled"; @@ -697,7 +697,7 @@ vin0: video@e6ef0000 { "renesas,rcar-gen2-vin"; reg = <0 0xe6ef0000 0 0x1000>; interrupts = ; - clocks = <&mstp8_clks R8A7792_CLK_VIN0>; + clocks = <&cpg CPG_MOD 811>; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; status = "disabled"; }; @@ -707,7 +707,7 @@ vin1: video@e6ef1000 { "renesas,rcar-gen2-vin"; reg = <0 0xe6ef1000 0 0x1000>; interrupts = ; - clocks = <&mstp8_clks R8A7792_CLK_VIN1>; + clocks = <&cpg CPG_MOD 810>; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; status = "disabled"; }; @@ -717,7 +717,7 @@ vin2: video@e6ef2000 { "renesas,rcar-gen2-vin"; reg = <0 0xe6ef2000 0 0x1000>; interrupts = ; - clocks = <&mstp8_clks R8A7792_CLK_VIN2>; + clocks = <&cpg CPG_MOD 809>; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; status = "disabled"; }; @@ -727,7 +727,7 @@ vin3: video@e6ef3000 { "renesas,rcar-gen2-vin"; reg = <0 0xe6ef3000 0 0x1000>; interrupts = ; - clocks = <&mstp8_clks R8A7792_CLK_VIN3>; + clocks = <&cpg CPG_MOD 808>; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; status = "disabled"; }; @@ -737,7 +737,7 @@ vin4: video@e6ef4000 { "renesas,rcar-gen2-vin"; reg = <0 0xe6ef4000 0 0x1000>; interrupts = ; - clocks = <&mstp8_clks R8A7792_CLK_VIN4>; + clocks = <&cpg CPG_MOD 805>; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; status = "disabled"; }; @@ -747,7 +747,7 @@ vin5: video@e6ef5000 { "renesas,rcar-gen2-vin"; reg = <0 0xe6ef5000 0 0x1000>; interrupts = ; - clocks = <&mstp8_clks R8A7792_CLK_VIN5>; + clocks = <&cpg CPG_MOD 804>; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; status = "disabled"; }; @@ -756,7 +756,7 @@ vsp1@fe928000 { compatible = "renesas,vsp1"; reg = <0 0xfe928000 0 0x8000>; interrupts = ; - clocks = <&mstp1_clks R8A7792_CLK_VSP1_SY>; + clocks = <&cpg CPG_MOD 131>; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; }; @@ -764,7 +764,7 @@ vsp1@fe930000 { compatible = "renesas,vsp1"; reg = <0 0xfe930000 0 0x8000>; interrupts = ; - clocks = <&mstp1_clks R8A7792_CLK_VSP1DU0>; + clocks = <&cpg CPG_MOD 128>; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; }; @@ -772,229 +772,18 @@ vsp1@fe938000 { compatible = "renesas,vsp1"; reg = <0 0xfe938000 0 0x8000>; interrupts = ; - clocks = <&mstp1_clks R8A7792_CLK_VSP1DU1>; + clocks = <&cpg CPG_MOD 127>; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; }; - /* Special CPG clocks */ - cpg_clocks: cpg_clocks@e6150000 { - compatible = "renesas,r8a7792-cpg-clocks", - "renesas,rcar-gen2-cpg-clocks"; + cpg: clock-controller@e6150000 { + compatible = "renesas,r8a7792-cpg-mssr"; reg = <0 0xe6150000 0 0x1000>; clocks = <&extal_clk>; - #clock-cells = <1>; - clock-output-names = "main", "pll0", "pll1", "pll3", - "lb", "qspi"; + clock-names = "extal"; + #clock-cells = <2>; #power-domain-cells = <0>; }; - - /* Fixed factor clocks */ - pll1_div2_clk: pll1_div2 { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7792_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <2>; - clock-mult = <1>; - }; - z_clk: z { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7792_CLK_PLL0>; - #clock-cells = <0>; - clock-div = <1>; - clock-mult = <1>; - }; - zx_clk: zx { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7792_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <3>; - clock-mult = <1>; - }; - zs_clk: zs { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7792_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <6>; - clock-mult = <1>; - }; - hp_clk: hp { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7792_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <12>; - clock-mult = <1>; - }; - p_clk: p { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7792_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <24>; - clock-mult = <1>; - }; - cp_clk: cp { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7792_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <48>; - clock-mult = <1>; - }; - mp_clk: mp { - compatible = "fixed-factor-clock"; - clocks = <&pll1_div2_clk>; - #clock-cells = <0>; - clock-div = <15>; - clock-mult = <1>; - }; - m2_clk: m2 { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7792_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <8>; - clock-mult = <1>; - }; - sd_clk: sd { - compatible = "fixed-factor-clock"; - clocks = <&pll1_div2_clk>; - #clock-cells = <0>; - clock-div = <8>; - clock-mult = <1>; - }; - rcan_clk: rcan { - compatible = "fixed-factor-clock"; - clocks = <&pll1_div2_clk>; - #clock-cells = <0>; - clock-div = <49>; - clock-mult = <1>; - }; - zg_clk: zg { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7792_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <5>; - clock-mult = <1>; - }; - - /* Gate clocks */ - mstp0_clks: mstp0_clks@e6150130 { - compatible = "renesas,r8a7792-mstp-clocks", - "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>; - clocks = <&mp_clk>; - #clock-cells = <1>; - clock-indices = ; - clock-output-names = "msiof0"; - }; - mstp1_clks: mstp1_clks@e6150134 { - compatible = "renesas,r8a7792-mstp-clocks", - "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>; - clocks = <&m2_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7792_CLK_JPU - R8A7792_CLK_VSP1DU1 R8A7792_CLK_VSP1DU0 - R8A7792_CLK_VSP1_SY - >; - clock-output-names = "jpu", "vsp1du1", "vsp1du0", - "vsp1-sy"; - }; - mstp2_clks: mstp2_clks@e6150138 { - compatible = "renesas,r8a7792-mstp-clocks", - "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>; - clocks = <&mp_clk>, <&zs_clk>, <&zs_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7792_CLK_MSIOF1 - R8A7792_CLK_SYS_DMAC1 R8A7792_CLK_SYS_DMAC0 - >; - clock-output-names = "msiof1", "sys-dmac1", "sys-dmac0"; - }; - mstp3_clks: mstp3_clks@e615013c { - compatible = "renesas,r8a7792-mstp-clocks", - "renesas,cpg-mstp-clocks"; - reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; - clocks = <&sd_clk>; - #clock-cells = <1>; - renesas,clock-indices = ; - clock-output-names = "sdhi0"; - }; - mstp4_clks: mstp4_clks@e6150140 { - compatible = "renesas,r8a7792-mstp-clocks", - "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>; - clocks = <&cp_clk>, <&zs_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7792_CLK_IRQC R8A7792_CLK_INTC_SYS - >; - clock-output-names = "irqc", "intc-sys"; - }; - mstp7_clks: mstp7_clks@e615014c { - compatible = "renesas,r8a7792-mstp-clocks", - "renesas,cpg-mstp-clocks"; - reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>; - clocks = <&zs_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, - <&p_clk>, <&p_clk>, <&zx_clk>, <&zx_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7792_CLK_HSCIF1 R8A7792_CLK_HSCIF0 - R8A7792_CLK_SCIF3 R8A7792_CLK_SCIF2 - R8A7792_CLK_SCIF1 R8A7792_CLK_SCIF0 - R8A7792_CLK_DU1 R8A7792_CLK_DU0 - >; - clock-output-names = "hscif1", "hscif0", "scif3", - "scif2", "scif1", "scif0", - "du1", "du0"; - }; - mstp8_clks: mstp8_clks@e6150990 { - compatible = "renesas,r8a7792-mstp-clocks", - "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>; - clocks = <&zg_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>, - <&zg_clk>, <&zg_clk>, <&hp_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7792_CLK_VIN5 R8A7792_CLK_VIN4 - R8A7792_CLK_VIN3 R8A7792_CLK_VIN2 - R8A7792_CLK_VIN1 R8A7792_CLK_VIN0 - R8A7792_CLK_ETHERAVB - >; - clock-output-names = "vin5", "vin4", "vin3", "vin2", - "vin1", "vin0", "etheravb"; - }; - mstp9_clks: mstp9_clks@e6150994 { - compatible = "renesas,r8a7792-mstp-clocks", - "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>; - clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>, - <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>, - <&cp_clk>, <&cp_clk>, <&p_clk>, <&p_clk>, - <&cpg_clocks R8A7792_CLK_QSPI>, - <&cp_clk>, <&cp_clk>, <&hp_clk>, <&hp_clk>, - <&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7792_CLK_GPIO7 R8A7792_CLK_GPIO6 - R8A7792_CLK_GPIO5 R8A7792_CLK_GPIO4 - R8A7792_CLK_GPIO3 R8A7792_CLK_GPIO2 - R8A7792_CLK_GPIO1 R8A7792_CLK_GPIO0 - R8A7792_CLK_GPIO11 R8A7792_CLK_GPIO10 - R8A7792_CLK_CAN1 R8A7792_CLK_CAN0 - R8A7792_CLK_QSPI_MOD - R8A7792_CLK_GPIO9 R8A7792_CLK_GPIO8 - R8A7792_CLK_I2C5 R8A7792_CLK_I2C4 - R8A7792_CLK_I2C3 R8A7792_CLK_I2C2 - R8A7792_CLK_I2C1 R8A7792_CLK_I2C0 - >; - clock-output-names = - "gpio7", "gpio6", "gpio5", "gpio4", - "gpio3", "gpio2", "gpio1", "gpio0", - "gpio11", "gpio10", "can1", "can0", - "qspi_mod", "gpio9", "gpio8", - "i2c5", "i2c4", "i2c3", "i2c2", - "i2c1", "i2c0"; - }; }; /* External root clock */ From d77fe953768850557a1851d2c933b76b2083e4d5 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 18 Aug 2017 11:11:37 +0200 Subject: [PATCH 03/48] ARM: dts: r8a7793: Convert to new CPG/MSSR bindings Convert the R-Car M2-N SoC from the old "Renesas R-Car Gen2 Clock Pulse Generator (CPG)", "Renesas CPG DIV6 Clock", and "Renesas CPG Module Stop (MSTP) Clocks" DT bindings to the new unified "Renesas Clock Pulse Generator / Module Standby and Software Reset" DT bindings. This simplifies the DTS files, and allows to add support for reset control later. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7793-gose.dts | 4 +- arch/arm/boot/dts/r8a7793.dtsi | 459 +++++------------------------ 2 files changed, 82 insertions(+), 381 deletions(-) diff --git a/arch/arm/boot/dts/r8a7793-gose.dts b/arch/arm/boot/dts/r8a7793-gose.dts index 76e3aca2029e..51b3ffac8efa 100644 --- a/arch/arm/boot/dts/r8a7793-gose.dts +++ b/arch/arm/boot/dts/r8a7793-gose.dts @@ -303,9 +303,7 @@ &du { pinctrl-names = "default"; status = "okay"; - clocks = <&mstp7_clks R8A7793_CLK_DU0>, - <&mstp7_clks R8A7793_CLK_DU1>, - <&mstp7_clks R8A7793_CLK_LVDS0>, + clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&cpg CPG_MOD 726>, <&x13_clk>, <&x2_clk>; clock-names = "du.0", "du.1", "lvds.0", "dclkin.0", "dclkin.1"; diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi index 497716b6fbe2..ef8009c01e66 100644 --- a/arch/arm/boot/dts/r8a7793.dtsi +++ b/arch/arm/boot/dts/r8a7793.dtsi @@ -8,7 +8,7 @@ * kind, whether express or implied. */ -#include +#include #include #include #include @@ -43,7 +43,7 @@ cpu0: cpu@0 { reg = <0>; clock-frequency = <1500000000>; voltage-tolerance = <1>; /* 1% */ - clocks = <&cpg_clocks R8A7793_CLK_Z>; + clocks = <&cpg CPG_CORE R8A7793_CLK_Z>; clock-latency = <300000>; /* 300 us */ power-domains = <&sysc R8A7793_PD_CA15_CPU0>; @@ -108,7 +108,7 @@ gic: interrupt-controller@f1001000 { <0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>; interrupts = ; - clocks = <&mstp4_clks R8A7793_CLK_INTC_SYS>; + clocks = <&cpg CPG_MOD 408>; clock-names = "clk"; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; }; @@ -122,7 +122,7 @@ gpio0: gpio@e6050000 { gpio-ranges = <&pfc 0 0 32>; #interrupt-cells = <2>; interrupt-controller; - clocks = <&mstp9_clks R8A7793_CLK_GPIO0>; + clocks = <&cpg CPG_MOD 912>; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; }; @@ -135,7 +135,7 @@ gpio1: gpio@e6051000 { gpio-ranges = <&pfc 0 32 26>; #interrupt-cells = <2>; interrupt-controller; - clocks = <&mstp9_clks R8A7793_CLK_GPIO1>; + clocks = <&cpg CPG_MOD 911>; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; }; @@ -148,7 +148,7 @@ gpio2: gpio@e6052000 { gpio-ranges = <&pfc 0 64 32>; #interrupt-cells = <2>; interrupt-controller; - clocks = <&mstp9_clks R8A7793_CLK_GPIO2>; + clocks = <&cpg CPG_MOD 910>; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; }; @@ -161,7 +161,7 @@ gpio3: gpio@e6053000 { gpio-ranges = <&pfc 0 96 32>; #interrupt-cells = <2>; interrupt-controller; - clocks = <&mstp9_clks R8A7793_CLK_GPIO3>; + clocks = <&cpg CPG_MOD 909>; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; }; @@ -174,7 +174,7 @@ gpio4: gpio@e6054000 { gpio-ranges = <&pfc 0 128 32>; #interrupt-cells = <2>; interrupt-controller; - clocks = <&mstp9_clks R8A7793_CLK_GPIO4>; + clocks = <&cpg CPG_MOD 908>; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; }; @@ -187,7 +187,7 @@ gpio5: gpio@e6055000 { gpio-ranges = <&pfc 0 160 32>; #interrupt-cells = <2>; interrupt-controller; - clocks = <&mstp9_clks R8A7793_CLK_GPIO5>; + clocks = <&cpg CPG_MOD 907>; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; }; @@ -200,7 +200,7 @@ gpio6: gpio@e6055400 { gpio-ranges = <&pfc 0 192 32>; #interrupt-cells = <2>; interrupt-controller; - clocks = <&mstp9_clks R8A7793_CLK_GPIO6>; + clocks = <&cpg CPG_MOD 905>; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; }; @@ -213,7 +213,7 @@ gpio7: gpio@e6055800 { gpio-ranges = <&pfc 0 224 26>; #interrupt-cells = <2>; interrupt-controller; - clocks = <&mstp9_clks R8A7793_CLK_GPIO7>; + clocks = <&cpg CPG_MOD 904>; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; }; @@ -223,7 +223,7 @@ thermal: thermal@e61f0000 { "renesas,rcar-thermal"; reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>; interrupts = ; - clocks = <&mstp5_clks R8A7793_CLK_THERMAL>; + clocks = <&cpg CPG_MOD 522>; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; #thermal-sensor-cells = <0>; }; @@ -241,7 +241,7 @@ cmt0: timer@ffca0000 { reg = <0 0xffca0000 0 0x1004>; interrupts = , ; - clocks = <&mstp1_clks R8A7793_CLK_CMT0>; + clocks = <&cpg CPG_MOD 124>; clock-names = "fck"; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; @@ -261,7 +261,7 @@ cmt1: timer@e6130000 { , , ; - clocks = <&mstp3_clks R8A7793_CLK_CMT1>; + clocks = <&cpg CPG_MOD 329>; clock-names = "fck"; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; @@ -285,7 +285,7 @@ irqc0: interrupt-controller@e61c0000 { , , ; - clocks = <&mstp4_clks R8A7793_CLK_IRQC>; + clocks = <&cpg CPG_MOD 407>; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; }; @@ -313,7 +313,7 @@ GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10", "ch11", "ch12", "ch13", "ch14"; - clocks = <&mstp2_clks R8A7793_CLK_SYS_DMAC0>; + clocks = <&cpg CPG_MOD 219>; clock-names = "fck"; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; #dma-cells = <1>; @@ -344,7 +344,7 @@ GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10", "ch11", "ch12", "ch13", "ch14"; - clocks = <&mstp2_clks R8A7793_CLK_SYS_DMAC1>; + clocks = <&cpg CPG_MOD 218>; clock-names = "fck"; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; #dma-cells = <1>; @@ -373,7 +373,7 @@ GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10", "ch11", "ch12"; - clocks = <&mstp5_clks R8A7793_CLK_AUDIO_DMAC0>; + clocks = <&cpg CPG_MOD 502>; clock-names = "fck"; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; #dma-cells = <1>; @@ -402,7 +402,7 @@ GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10", "ch11", "ch12"; - clocks = <&mstp5_clks R8A7793_CLK_AUDIO_DMAC1>; + clocks = <&cpg CPG_MOD 501>; clock-names = "fck"; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; #dma-cells = <1>; @@ -416,7 +416,7 @@ i2c0: i2c@e6508000 { compatible = "renesas,i2c-r8a7793", "renesas,rcar-gen2-i2c"; reg = <0 0xe6508000 0 0x40>; interrupts = ; - clocks = <&mstp9_clks R8A7793_CLK_I2C0>; + clocks = <&cpg CPG_MOD 931>; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; i2c-scl-internal-delay-ns = <6>; status = "disabled"; @@ -428,7 +428,7 @@ i2c1: i2c@e6518000 { compatible = "renesas,i2c-r8a7793", "renesas,rcar-gen2-i2c"; reg = <0 0xe6518000 0 0x40>; interrupts = ; - clocks = <&mstp9_clks R8A7793_CLK_I2C1>; + clocks = <&cpg CPG_MOD 930>; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; i2c-scl-internal-delay-ns = <6>; status = "disabled"; @@ -440,7 +440,7 @@ i2c2: i2c@e6530000 { compatible = "renesas,i2c-r8a7793", "renesas,rcar-gen2-i2c"; reg = <0 0xe6530000 0 0x40>; interrupts = ; - clocks = <&mstp9_clks R8A7793_CLK_I2C2>; + clocks = <&cpg CPG_MOD 929>; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; i2c-scl-internal-delay-ns = <6>; status = "disabled"; @@ -452,7 +452,7 @@ i2c3: i2c@e6540000 { compatible = "renesas,i2c-r8a7793", "renesas,rcar-gen2-i2c"; reg = <0 0xe6540000 0 0x40>; interrupts = ; - clocks = <&mstp9_clks R8A7793_CLK_I2C3>; + clocks = <&cpg CPG_MOD 928>; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; i2c-scl-internal-delay-ns = <6>; status = "disabled"; @@ -464,7 +464,7 @@ i2c4: i2c@e6520000 { compatible = "renesas,i2c-r8a7793", "renesas,rcar-gen2-i2c"; reg = <0 0xe6520000 0 0x40>; interrupts = ; - clocks = <&mstp9_clks R8A7793_CLK_I2C4>; + clocks = <&cpg CPG_MOD 927>; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; i2c-scl-internal-delay-ns = <6>; status = "disabled"; @@ -477,7 +477,7 @@ i2c5: i2c@e6528000 { compatible = "renesas,i2c-r8a7793", "renesas,rcar-gen2-i2c"; reg = <0 0xe6528000 0 0x40>; interrupts = ; - clocks = <&mstp9_clks R8A7793_CLK_I2C5>; + clocks = <&cpg CPG_MOD 925>; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; i2c-scl-internal-delay-ns = <110>; status = "disabled"; @@ -491,7 +491,7 @@ i2c6: i2c@e60b0000 { "renesas,rmobile-iic"; reg = <0 0xe60b0000 0 0x425>; interrupts = ; - clocks = <&mstp9_clks R8A7793_CLK_IICDVFS>; + clocks = <&cpg CPG_MOD 926>; dmas = <&dmac0 0x77>, <&dmac0 0x78>, <&dmac1 0x77>, <&dmac1 0x78>; dma-names = "tx", "rx", "tx", "rx"; @@ -506,7 +506,7 @@ i2c7: i2c@e6500000 { "renesas,rmobile-iic"; reg = <0 0xe6500000 0 0x425>; interrupts = ; - clocks = <&mstp3_clks R8A7793_CLK_IIC0>; + clocks = <&cpg CPG_MOD 318>; dmas = <&dmac0 0x61>, <&dmac0 0x62>, <&dmac1 0x61>, <&dmac1 0x62>; dma-names = "tx", "rx", "tx", "rx"; @@ -521,7 +521,7 @@ i2c8: i2c@e6510000 { "renesas,rmobile-iic"; reg = <0 0xe6510000 0 0x425>; interrupts = ; - clocks = <&mstp3_clks R8A7793_CLK_IIC1>; + clocks = <&cpg CPG_MOD 323>; dmas = <&dmac0 0x65>, <&dmac0 0x66>, <&dmac1 0x65>, <&dmac1 0x66>; dma-names = "tx", "rx", "tx", "rx"; @@ -538,7 +538,7 @@ sdhi0: sd@ee100000 { compatible = "renesas,sdhi-r8a7793"; reg = <0 0xee100000 0 0x328>; interrupts = ; - clocks = <&mstp3_clks R8A7793_CLK_SDHI0>; + clocks = <&cpg CPG_MOD 314>; dmas = <&dmac0 0xcd>, <&dmac0 0xce>, <&dmac1 0xcd>, <&dmac1 0xce>; dma-names = "tx", "rx", "tx", "rx"; @@ -551,7 +551,7 @@ sdhi1: sd@ee140000 { compatible = "renesas,sdhi-r8a7793"; reg = <0 0xee140000 0 0x100>; interrupts = ; - clocks = <&mstp3_clks R8A7793_CLK_SDHI1>; + clocks = <&cpg CPG_MOD 312>; dmas = <&dmac0 0xc1>, <&dmac0 0xc2>, <&dmac1 0xc1>, <&dmac1 0xc2>; dma-names = "tx", "rx", "tx", "rx"; @@ -564,7 +564,7 @@ sdhi2: sd@ee160000 { compatible = "renesas,sdhi-r8a7793"; reg = <0 0xee160000 0 0x100>; interrupts = ; - clocks = <&mstp3_clks R8A7793_CLK_SDHI2>; + clocks = <&cpg CPG_MOD 311>; dmas = <&dmac0 0xd3>, <&dmac0 0xd4>, <&dmac1 0xd3>, <&dmac1 0xd4>; dma-names = "tx", "rx", "tx", "rx"; @@ -577,7 +577,7 @@ mmcif0: mmc@ee200000 { compatible = "renesas,mmcif-r8a7793", "renesas,sh-mmcif"; reg = <0 0xee200000 0 0x80>; interrupts = ; - clocks = <&mstp3_clks R8A7793_CLK_MMCIF0>; + clocks = <&cpg CPG_MOD 315>; dmas = <&dmac0 0xd1>, <&dmac0 0xd2>, <&dmac1 0xd1>, <&dmac1 0xd2>; dma-names = "tx", "rx", "tx", "rx"; @@ -592,7 +592,7 @@ scifa0: serial@e6c40000 { "renesas,rcar-gen2-scifa", "renesas,scifa"; reg = <0 0xe6c40000 0 64>; interrupts = ; - clocks = <&mstp2_clks R8A7793_CLK_SCIFA0>; + clocks = <&cpg CPG_MOD 204>; clock-names = "fck"; dmas = <&dmac0 0x21>, <&dmac0 0x22>, <&dmac1 0x21>, <&dmac1 0x22>; @@ -606,7 +606,7 @@ scifa1: serial@e6c50000 { "renesas,rcar-gen2-scifa", "renesas,scifa"; reg = <0 0xe6c50000 0 64>; interrupts = ; - clocks = <&mstp2_clks R8A7793_CLK_SCIFA1>; + clocks = <&cpg CPG_MOD 203>; clock-names = "fck"; dmas = <&dmac0 0x25>, <&dmac0 0x26>, <&dmac1 0x25>, <&dmac1 0x26>; @@ -620,7 +620,7 @@ scifa2: serial@e6c60000 { "renesas,rcar-gen2-scifa", "renesas,scifa"; reg = <0 0xe6c60000 0 64>; interrupts = ; - clocks = <&mstp2_clks R8A7793_CLK_SCIFA2>; + clocks = <&cpg CPG_MOD 202>; clock-names = "fck"; dmas = <&dmac0 0x27>, <&dmac0 0x28>, <&dmac1 0x27>, <&dmac1 0x28>; @@ -634,7 +634,7 @@ scifa3: serial@e6c70000 { "renesas,rcar-gen2-scifa", "renesas,scifa"; reg = <0 0xe6c70000 0 64>; interrupts = ; - clocks = <&mstp11_clks R8A7793_CLK_SCIFA3>; + clocks = <&cpg CPG_MOD 1106>; clock-names = "fck"; dmas = <&dmac0 0x1b>, <&dmac0 0x1c>, <&dmac1 0x1b>, <&dmac1 0x1c>; @@ -648,7 +648,7 @@ scifa4: serial@e6c78000 { "renesas,rcar-gen2-scifa", "renesas,scifa"; reg = <0 0xe6c78000 0 64>; interrupts = ; - clocks = <&mstp11_clks R8A7793_CLK_SCIFA4>; + clocks = <&cpg CPG_MOD 1107>; clock-names = "fck"; dmas = <&dmac0 0x1f>, <&dmac0 0x20>, <&dmac1 0x1f>, <&dmac1 0x20>; @@ -662,7 +662,7 @@ scifa5: serial@e6c80000 { "renesas,rcar-gen2-scifa", "renesas,scifa"; reg = <0 0xe6c80000 0 64>; interrupts = ; - clocks = <&mstp11_clks R8A7793_CLK_SCIFA5>; + clocks = <&cpg CPG_MOD 1108>; clock-names = "fck"; dmas = <&dmac0 0x23>, <&dmac0 0x24>, <&dmac1 0x23>, <&dmac1 0x24>; @@ -676,7 +676,7 @@ scifb0: serial@e6c20000 { "renesas,rcar-gen2-scifb", "renesas,scifb"; reg = <0 0xe6c20000 0 0x100>; interrupts = ; - clocks = <&mstp2_clks R8A7793_CLK_SCIFB0>; + clocks = <&cpg CPG_MOD 206>; clock-names = "fck"; dmas = <&dmac0 0x3d>, <&dmac0 0x3e>, <&dmac1 0x3d>, <&dmac1 0x3e>; @@ -690,7 +690,7 @@ scifb1: serial@e6c30000 { "renesas,rcar-gen2-scifb", "renesas,scifb"; reg = <0 0xe6c30000 0 0x100>; interrupts = ; - clocks = <&mstp2_clks R8A7793_CLK_SCIFB1>; + clocks = <&cpg CPG_MOD 207>; clock-names = "fck"; dmas = <&dmac0 0x19>, <&dmac0 0x1a>, <&dmac1 0x19>, <&dmac1 0x1a>; @@ -704,7 +704,7 @@ scifb2: serial@e6ce0000 { "renesas,rcar-gen2-scifb", "renesas,scifb"; reg = <0 0xe6ce0000 0 0x100>; interrupts = ; - clocks = <&mstp2_clks R8A7793_CLK_SCIFB2>; + clocks = <&cpg CPG_MOD 216>; clock-names = "fck"; dmas = <&dmac0 0x1d>, <&dmac0 0x1e>, <&dmac1 0x1d>, <&dmac1 0x1e>; @@ -718,7 +718,7 @@ scif0: serial@e6e60000 { "renesas,scif"; reg = <0 0xe6e60000 0 64>; interrupts = ; - clocks = <&mstp7_clks R8A7793_CLK_SCIF0>, <&zs_clk>, + clocks = <&cpg CPG_MOD 721>, <&cpg CPG_CORE R8A7793_CLK_ZS>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x29>, <&dmac0 0x2a>, @@ -733,7 +733,7 @@ scif1: serial@e6e68000 { "renesas,scif"; reg = <0 0xe6e68000 0 64>; interrupts = ; - clocks = <&mstp7_clks R8A7793_CLK_SCIF1>, <&zs_clk>, + clocks = <&cpg CPG_MOD 720>, <&cpg CPG_CORE R8A7793_CLK_ZS>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x2d>, <&dmac0 0x2e>, @@ -748,7 +748,7 @@ scif2: serial@e6e58000 { "renesas,scif"; reg = <0 0xe6e58000 0 64>; interrupts = ; - clocks = <&mstp7_clks R8A7793_CLK_SCIF2>, <&zs_clk>, + clocks = <&cpg CPG_MOD 719>, <&cpg CPG_CORE R8A7793_CLK_ZS>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x2b>, <&dmac0 0x2c>, @@ -763,7 +763,7 @@ scif3: serial@e6ea8000 { "renesas,scif"; reg = <0 0xe6ea8000 0 64>; interrupts = ; - clocks = <&mstp7_clks R8A7793_CLK_SCIF3>, <&zs_clk>, + clocks = <&cpg CPG_MOD 718>, <&cpg CPG_CORE R8A7793_CLK_ZS>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x2f>, <&dmac0 0x30>, @@ -778,7 +778,7 @@ scif4: serial@e6ee0000 { "renesas,scif"; reg = <0 0xe6ee0000 0 64>; interrupts = ; - clocks = <&mstp7_clks R8A7793_CLK_SCIF4>, <&zs_clk>, + clocks = <&cpg CPG_MOD 715>, <&cpg CPG_CORE R8A7793_CLK_ZS>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0xfb>, <&dmac0 0xfc>, @@ -793,7 +793,7 @@ scif5: serial@e6ee8000 { "renesas,scif"; reg = <0 0xe6ee8000 0 64>; interrupts = ; - clocks = <&mstp7_clks R8A7793_CLK_SCIF5>, <&zs_clk>, + clocks = <&cpg CPG_MOD 714>, <&cpg CPG_CORE R8A7793_CLK_ZS>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0xfd>, <&dmac0 0xfe>, @@ -808,7 +808,7 @@ hscif0: serial@e62c0000 { "renesas,rcar-gen2-hscif", "renesas,hscif"; reg = <0 0xe62c0000 0 96>; interrupts = ; - clocks = <&mstp7_clks R8A7793_CLK_HSCIF0>, <&zs_clk>, + clocks = <&cpg CPG_MOD 717>, <&cpg CPG_CORE R8A7793_CLK_ZS>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x39>, <&dmac0 0x3a>, @@ -823,7 +823,7 @@ hscif1: serial@e62c8000 { "renesas,rcar-gen2-hscif", "renesas,hscif"; reg = <0 0xe62c8000 0 96>; interrupts = ; - clocks = <&mstp7_clks R8A7793_CLK_HSCIF1>, <&zs_clk>, + clocks = <&cpg CPG_MOD 716>, <&cpg CPG_CORE R8A7793_CLK_ZS>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x4d>, <&dmac0 0x4e>, @@ -838,7 +838,7 @@ hscif2: serial@e62d0000 { "renesas,rcar-gen2-hscif", "renesas,hscif"; reg = <0 0xe62d0000 0 96>; interrupts = ; - clocks = <&mstp7_clks R8A7793_CLK_HSCIF2>, <&zs_clk>, + clocks = <&cpg CPG_MOD 713>, <&cpg CPG_CORE R8A7793_CLK_ZS>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x3b>, <&dmac0 0x3c>, @@ -870,7 +870,7 @@ ether: ethernet@ee700000 { compatible = "renesas,ether-r8a7793"; reg = <0 0xee700000 0 0x400>; interrupts = ; - clocks = <&mstp8_clks R8A7793_CLK_ETHER>; + clocks = <&cpg CPG_MOD 813>; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; phy-mode = "rmii"; #address-cells = <1>; @@ -882,7 +882,7 @@ vin0: video@e6ef0000 { compatible = "renesas,vin-r8a7793", "renesas,rcar-gen2-vin"; reg = <0 0xe6ef0000 0 0x1000>; interrupts = ; - clocks = <&mstp8_clks R8A7793_CLK_VIN0>; + clocks = <&cpg CPG_MOD 811>; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; status = "disabled"; }; @@ -891,7 +891,7 @@ vin1: video@e6ef1000 { compatible = "renesas,vin-r8a7793", "renesas,rcar-gen2-vin"; reg = <0 0xe6ef1000 0 0x1000>; interrupts = ; - clocks = <&mstp8_clks R8A7793_CLK_VIN1>; + clocks = <&cpg CPG_MOD 810>; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; status = "disabled"; }; @@ -900,7 +900,7 @@ vin2: video@e6ef2000 { compatible = "renesas,vin-r8a7793", "renesas,rcar-gen2-vin"; reg = <0 0xe6ef2000 0 0x1000>; interrupts = ; - clocks = <&mstp8_clks R8A7793_CLK_VIN2>; + clocks = <&cpg CPG_MOD 809>; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; status = "disabled"; }; @@ -909,7 +909,7 @@ qspi: spi@e6b10000 { compatible = "renesas,qspi-r8a7793", "renesas,qspi"; reg = <0 0xe6b10000 0 0x2c>; interrupts = ; - clocks = <&mstp9_clks R8A7793_CLK_QSPI_MOD>; + clocks = <&cpg CPG_MOD 917>; dmas = <&dmac0 0x17>, <&dmac0 0x18>, <&dmac1 0x17>, <&dmac1 0x18>; dma-names = "tx", "rx", "tx", "rx"; @@ -927,9 +927,9 @@ du: display@feb00000 { reg-names = "du", "lvds.0"; interrupts = , ; - clocks = <&mstp7_clks R8A7793_CLK_DU0>, - <&mstp7_clks R8A7793_CLK_DU1>, - <&mstp7_clks R8A7793_CLK_LVDS0>; + clocks = <&cpg CPG_MOD 724>, + <&cpg CPG_MOD 723>, + <&cpg CPG_MOD 726>; clock-names = "du.0", "du.1", "lvds.0"; status = "disabled"; @@ -954,8 +954,8 @@ can0: can@e6e80000 { compatible = "renesas,can-r8a7793", "renesas,rcar-gen2-can"; reg = <0 0xe6e80000 0 0x1000>; interrupts = ; - clocks = <&mstp9_clks R8A7793_CLK_RCAN0>, - <&cpg_clocks R8A7793_CLK_RCAN>, <&can_clk>; + clocks = <&cpg CPG_MOD 916>, <&cpg CPG_CORE R8A7793_CLK_RCAN>, + <&can_clk>; clock-names = "clkp1", "clkp2", "can_clk"; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; status = "disabled"; @@ -965,8 +965,8 @@ can1: can@e6e88000 { compatible = "renesas,can-r8a7793", "renesas,rcar-gen2-can"; reg = <0 0xe6e88000 0 0x1000>; interrupts = ; - clocks = <&mstp9_clks R8A7793_CLK_RCAN1>, - <&cpg_clocks R8A7793_CLK_RCAN>, <&can_clk>; + clocks = <&cpg CPG_MOD 915>, <&cpg CPG_CORE R8A7793_CLK_RCAN>, + <&can_clk>; clock-names = "clkp1", "clkp2", "can_clk"; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; status = "disabled"; @@ -1029,312 +1029,14 @@ scif_clk: scif { }; /* Special CPG clocks */ - cpg_clocks: cpg_clocks@e6150000 { - compatible = "renesas,r8a7793-cpg-clocks", - "renesas,rcar-gen2-cpg-clocks"; + cpg: clock-controller@e6150000 { + compatible = "renesas,r8a7793-cpg-mssr"; reg = <0 0xe6150000 0 0x1000>; - clocks = <&extal_clk &usb_extal_clk>; - #clock-cells = <1>; - clock-output-names = "main", "pll0", "pll1", "pll3", - "lb", "qspi", "sdh", "sd0", "z", - "rcan", "adsp"; + clocks = <&extal_clk>, <&usb_extal_clk>; + clock-names = "extal", "usb_extal"; + #clock-cells = <2>; #power-domain-cells = <0>; }; - - /* Variable factor clocks */ - sd2_clk: sd2@e6150078 { - compatible = "renesas,r8a7793-div6-clock", - "renesas,cpg-div6-clock"; - reg = <0 0xe6150078 0 4>; - clocks = <&pll1_div2_clk>; - #clock-cells = <0>; - }; - sd3_clk: sd3@e615026c { - compatible = "renesas,r8a7793-div6-clock", - "renesas,cpg-div6-clock"; - reg = <0 0xe615026c 0 4>; - clocks = <&pll1_div2_clk>; - #clock-cells = <0>; - }; - mmc0_clk: mmc0@e6150240 { - compatible = "renesas,r8a7793-div6-clock", - "renesas,cpg-div6-clock"; - reg = <0 0xe6150240 0 4>; - clocks = <&pll1_div2_clk>; - #clock-cells = <0>; - }; - - /* Fixed factor clocks */ - pll1_div2_clk: pll1_div2 { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7793_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <2>; - clock-mult = <1>; - }; - zg_clk: zg { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7793_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <5>; - clock-mult = <1>; - }; - zx_clk: zx { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7793_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <3>; - clock-mult = <1>; - }; - zs_clk: zs { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7793_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <6>; - clock-mult = <1>; - }; - hp_clk: hp { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7793_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <12>; - clock-mult = <1>; - }; - p_clk: p { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7793_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <24>; - clock-mult = <1>; - }; - m2_clk: m2 { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7793_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <8>; - clock-mult = <1>; - }; - rclk_clk: rclk { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7793_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <(48 * 1024)>; - clock-mult = <1>; - }; - mp_clk: mp { - compatible = "fixed-factor-clock"; - clocks = <&pll1_div2_clk>; - #clock-cells = <0>; - clock-div = <15>; - clock-mult = <1>; - }; - cp_clk: cp { - compatible = "fixed-factor-clock"; - clocks = <&extal_clk>; - #clock-cells = <0>; - clock-div = <2>; - clock-mult = <1>; - }; - - /* Gate clocks */ - mstp1_clks: mstp1_clks@e6150134 { - compatible = "renesas,r8a7793-mstp-clocks", - "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>; - clocks = <&zs_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>, - <&zg_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, - <&p_clk>, <&p_clk>, <&rclk_clk>, <&cp_clk>, - <&zs_clk>, <&zs_clk>, <&zs_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7793_CLK_VCP0 R8A7793_CLK_VPC0 - R8A7793_CLK_SSP1 R8A7793_CLK_TMU1 - R8A7793_CLK_3DG R8A7793_CLK_2DDMAC - R8A7793_CLK_FDP1_1 R8A7793_CLK_FDP1_0 - R8A7793_CLK_TMU3 R8A7793_CLK_TMU2 - R8A7793_CLK_CMT0 R8A7793_CLK_TMU0 - R8A7793_CLK_VSP1_DU1 R8A7793_CLK_VSP1_DU0 - R8A7793_CLK_VSP1_S - >; - clock-output-names = - "vcp0", "vpc0", "ssp_dev", "tmu1", - "pvrsrvkm", "tddmac", "fdp1", "fdp0", - "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1", - "vsp1-du0", "vsps"; - }; - mstp2_clks: mstp2_clks@e6150138 { - compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>; - clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, - <&mp_clk>, <&mp_clk>, <&zs_clk>, <&zs_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7793_CLK_SCIFA2 R8A7793_CLK_SCIFA1 R8A7793_CLK_SCIFA0 - R8A7793_CLK_SCIFB0 R8A7793_CLK_SCIFB1 R8A7793_CLK_SCIFB2 - R8A7793_CLK_SYS_DMAC1 R8A7793_CLK_SYS_DMAC0 - >; - clock-output-names = - "scifa2", "scifa1", "scifa0", "scifb0", - "scifb1", "scifb2", "sys-dmac1", "sys-dmac0"; - }; - mstp3_clks: mstp3_clks@e615013c { - compatible = "renesas,r8a7793-mstp-clocks", - "renesas,cpg-mstp-clocks"; - reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; - clocks = <&cp_clk>, <&sd3_clk>, <&sd2_clk>, - <&cpg_clocks R8A7793_CLK_SD0>, <&mmc0_clk>, - <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, - <&rclk_clk>, <&hp_clk>, <&hp_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7793_CLK_TPU0 R8A7793_CLK_SDHI2 - R8A7793_CLK_SDHI1 R8A7793_CLK_SDHI0 - R8A7793_CLK_MMCIF0 R8A7793_CLK_IIC0 - R8A7793_CLK_PCIEC R8A7793_CLK_IIC1 - R8A7793_CLK_SSUSB R8A7793_CLK_CMT1 - R8A7793_CLK_USBDMAC0 R8A7793_CLK_USBDMAC1 - >; - clock-output-names = - "tpu0", "sdhi2", "sdhi1", "sdhi0", "mmcif0", - "i2c7", "pciec", "i2c8", "ssusb", "cmt1", - "usbdmac0", "usbdmac1"; - }; - mstp4_clks: mstp4_clks@e6150140 { - compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>; - clocks = <&cp_clk>, <&zs_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7793_CLK_IRQC R8A7793_CLK_INTC_SYS - >; - clock-output-names = "irqc", "intc-sys"; - }; - mstp5_clks: mstp5_clks@e6150144 { - compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>; - clocks = <&hp_clk>, <&hp_clk>, <&extal_clk>; - #clock-cells = <1>; - clock-indices = ; - clock-output-names = "audmac0", "audmac1", "thermal"; - }; - mstp7_clks: mstp7_clks@e615014c { - compatible = "renesas,r8a7793-mstp-clocks", - "renesas,cpg-mstp-clocks"; - reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>; - clocks = <&mp_clk>, <&hp_clk>, <&zs_clk>, <&p_clk>, - <&p_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>, - <&p_clk>, <&p_clk>, <&p_clk>, <&zx_clk>, - <&zx_clk>, <&zx_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7793_CLK_EHCI R8A7793_CLK_HSUSB - R8A7793_CLK_HSCIF2 R8A7793_CLK_SCIF5 - R8A7793_CLK_SCIF4 R8A7793_CLK_HSCIF1 - R8A7793_CLK_HSCIF0 R8A7793_CLK_SCIF3 - R8A7793_CLK_SCIF2 R8A7793_CLK_SCIF1 - R8A7793_CLK_SCIF0 R8A7793_CLK_DU1 - R8A7793_CLK_DU0 R8A7793_CLK_LVDS0 - >; - clock-output-names = - "ehci", "hsusb", "hscif2", "scif5", "scif4", - "hscif1", "hscif0", "scif3", "scif2", - "scif1", "scif0", "du1", "du0", "lvds0"; - }; - mstp8_clks: mstp8_clks@e6150990 { - compatible = "renesas,r8a7793-mstp-clocks", - "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>; - clocks = <&zx_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>, - <&p_clk>, <&zs_clk>, <&zs_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7793_CLK_IPMMU_SGX R8A7793_CLK_VIN2 - R8A7793_CLK_VIN1 R8A7793_CLK_VIN0 - R8A7793_CLK_ETHER R8A7793_CLK_SATA1 - R8A7793_CLK_SATA0 - >; - clock-output-names = - "ipmmu_sgx", "vin2", "vin1", "vin0", "ether", - "sata1", "sata0"; - }; - mstp9_clks: mstp9_clks@e6150994 { - compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>; - clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>, - <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>, - <&p_clk>, <&p_clk>, - <&cpg_clocks R8A7793_CLK_QSPI>, <&hp_clk>, - <&cp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>, - <&hp_clk>, <&hp_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7793_CLK_GPIO7 R8A7793_CLK_GPIO6 - R8A7793_CLK_GPIO5 R8A7793_CLK_GPIO4 - R8A7793_CLK_GPIO3 R8A7793_CLK_GPIO2 - R8A7793_CLK_GPIO1 R8A7793_CLK_GPIO0 - R8A7793_CLK_QSPI_MOD R8A7793_CLK_RCAN1 - R8A7793_CLK_RCAN0 R8A7793_CLK_I2C5 - R8A7793_CLK_IICDVFS R8A7793_CLK_I2C4 - R8A7793_CLK_I2C3 R8A7793_CLK_I2C2 - R8A7793_CLK_I2C1 R8A7793_CLK_I2C0 - >; - clock-output-names = - "gpio7", "gpio6", "gpio5", "gpio4", - "gpio3", "gpio2", "gpio1", "gpio0", - "rcan1", "rcan0", "qspi_mod", "i2c5", - "i2c6", "i2c4", "i2c3", "i2c2", "i2c1", - "i2c0"; - }; - mstp10_clks: mstp10_clks@e6150998 { - compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>; - clocks = <&p_clk>, - <&mstp10_clks R8A7793_CLK_SSI_ALL>, <&mstp10_clks R8A7793_CLK_SSI_ALL>, - <&mstp10_clks R8A7793_CLK_SSI_ALL>, <&mstp10_clks R8A7793_CLK_SSI_ALL>, - <&mstp10_clks R8A7793_CLK_SSI_ALL>, <&mstp10_clks R8A7793_CLK_SSI_ALL>, - <&mstp10_clks R8A7793_CLK_SSI_ALL>, <&mstp10_clks R8A7793_CLK_SSI_ALL>, - <&mstp10_clks R8A7793_CLK_SSI_ALL>, <&mstp10_clks R8A7793_CLK_SSI_ALL>, - <&p_clk>, - <&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>, - <&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>, - <&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>, - <&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>, - <&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>, - <&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>, - <&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>; - - #clock-cells = <1>; - clock-indices = < - R8A7793_CLK_SSI_ALL - R8A7793_CLK_SSI9 R8A7793_CLK_SSI8 R8A7793_CLK_SSI7 R8A7793_CLK_SSI6 R8A7793_CLK_SSI5 - R8A7793_CLK_SSI4 R8A7793_CLK_SSI3 R8A7793_CLK_SSI2 R8A7793_CLK_SSI1 R8A7793_CLK_SSI0 - R8A7793_CLK_SCU_ALL - R8A7793_CLK_SCU_DVC1 R8A7793_CLK_SCU_DVC0 - R8A7793_CLK_SCU_CTU1_MIX1 R8A7793_CLK_SCU_CTU0_MIX0 - R8A7793_CLK_SCU_SRC9 R8A7793_CLK_SCU_SRC8 R8A7793_CLK_SCU_SRC7 R8A7793_CLK_SCU_SRC6 R8A7793_CLK_SCU_SRC5 - R8A7793_CLK_SCU_SRC4 R8A7793_CLK_SCU_SRC3 R8A7793_CLK_SCU_SRC2 R8A7793_CLK_SCU_SRC1 R8A7793_CLK_SCU_SRC0 - >; - clock-output-names = - "ssi-all", - "ssi9", "ssi8", "ssi7", "ssi6", "ssi5", - "ssi4", "ssi3", "ssi2", "ssi1", "ssi0", - "scu-all", - "scu-dvc1", "scu-dvc0", - "scu-ctu1-mix1", "scu-ctu0-mix0", - "scu-src9", "scu-src8", "scu-src7", "scu-src6", "scu-src5", - "scu-src4", "scu-src3", "scu-src2", "scu-src1", "scu-src0"; - }; - mstp11_clks: mstp11_clks@e615099c { - compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>; - clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7793_CLK_SCIFA3 R8A7793_CLK_SCIFA4 R8A7793_CLK_SCIFA5 - >; - clock-output-names = "scifa3", "scifa4", "scifa5"; - }; }; rst: reset-controller@e6160000 { @@ -1428,19 +1130,20 @@ rcar_sound: sound@ec500000 { <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/ reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; - clocks = <&mstp10_clks R8A7793_CLK_SSI_ALL>, - <&mstp10_clks R8A7793_CLK_SSI9>, <&mstp10_clks R8A7793_CLK_SSI8>, - <&mstp10_clks R8A7793_CLK_SSI7>, <&mstp10_clks R8A7793_CLK_SSI6>, - <&mstp10_clks R8A7793_CLK_SSI5>, <&mstp10_clks R8A7793_CLK_SSI4>, - <&mstp10_clks R8A7793_CLK_SSI3>, <&mstp10_clks R8A7793_CLK_SSI2>, - <&mstp10_clks R8A7793_CLK_SSI1>, <&mstp10_clks R8A7793_CLK_SSI0>, - <&mstp10_clks R8A7793_CLK_SCU_SRC9>, <&mstp10_clks R8A7793_CLK_SCU_SRC8>, - <&mstp10_clks R8A7793_CLK_SCU_SRC7>, <&mstp10_clks R8A7793_CLK_SCU_SRC6>, - <&mstp10_clks R8A7793_CLK_SCU_SRC5>, <&mstp10_clks R8A7793_CLK_SCU_SRC4>, - <&mstp10_clks R8A7793_CLK_SCU_SRC3>, <&mstp10_clks R8A7793_CLK_SCU_SRC2>, - <&mstp10_clks R8A7793_CLK_SCU_SRC1>, <&mstp10_clks R8A7793_CLK_SCU_SRC0>, - <&mstp10_clks R8A7793_CLK_SCU_DVC0>, <&mstp10_clks R8A7793_CLK_SCU_DVC1>, - <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, <&m2_clk>; + clocks = <&cpg CPG_MOD 1005>, + <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, + <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, + <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, + <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, + <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, + <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, + <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, + <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, + <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, + <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, + <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, + <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, + <&cpg CPG_CORE R8A7793_CLK_M2>; clock-names = "ssi-all", "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5", "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0", From 58d6c357b1f7851d632bb70de3a9ada219f201c2 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 18 Aug 2017 11:11:38 +0200 Subject: [PATCH 04/48] ARM: dts: r8a7794: Convert to new CPG/MSSR bindings Convert the R-Car E2 SoC from the old "Renesas R-Car Gen2 Clock Pulse Generator (CPG)", "Renesas CPG DIV6 Clock", and "Renesas CPG Module Stop (MSTP) Clocks" DT bindings to the new unified "Renesas Clock Pulse Generator / Module Standby and Software Reset" DT bindings. This simplifies the DTS files, and allows to add support for reset control later. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7794-alt.dts | 3 +- arch/arm/boot/dts/r8a7794-silk.dts | 3 +- arch/arm/boot/dts/r8a7794.dtsi | 528 +++++------------------------ 3 files changed, 82 insertions(+), 452 deletions(-) diff --git a/arch/arm/boot/dts/r8a7794-alt.dts b/arch/arm/boot/dts/r8a7794-alt.dts index f1eea13cdf44..e45f92b5eb11 100644 --- a/arch/arm/boot/dts/r8a7794-alt.dts +++ b/arch/arm/boot/dts/r8a7794-alt.dts @@ -167,8 +167,7 @@ &du { pinctrl-names = "default"; status = "okay"; - clocks = <&mstp7_clks R8A7794_CLK_DU0>, - <&mstp7_clks R8A7794_CLK_DU1>, + clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&x13_clk>, <&x2_clk>; clock-names = "du.0", "du.1", "dclkin.0", "dclkin.1"; diff --git a/arch/arm/boot/dts/r8a7794-silk.dts b/arch/arm/boot/dts/r8a7794-silk.dts index 4cb5278d104d..edfad0e5ac53 100644 --- a/arch/arm/boot/dts/r8a7794-silk.dts +++ b/arch/arm/boot/dts/r8a7794-silk.dts @@ -423,8 +423,7 @@ &du { pinctrl-names = "default"; status = "okay"; - clocks = <&mstp7_clks R8A7794_CLK_DU0>, - <&mstp7_clks R8A7794_CLK_DU1>, + clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&x2_clk>, <&x3_clk>; clock-names = "du.0", "du.1", "dclkin.0", "dclkin.1"; diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi index 26535414203a..ebd44d9982be 100644 --- a/arch/arm/boot/dts/r8a7794.dtsi +++ b/arch/arm/boot/dts/r8a7794.dtsi @@ -9,7 +9,7 @@ * kind, whether express or implied. */ -#include +#include #include #include #include @@ -43,7 +43,7 @@ cpu0: cpu@0 { compatible = "arm,cortex-a7"; reg = <0>; clock-frequency = <1000000000>; - clocks = <&z2_clk>; + clocks = <&cpg CPG_CORE R8A7794_CLK_Z2>; power-domains = <&sysc R8A7794_PD_CA7_CPU0>; next-level-cache = <&L2_CA7>; }; @@ -75,7 +75,7 @@ gic: interrupt-controller@f1001000 { <0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>; interrupts = ; - clocks = <&mstp4_clks R8A7794_CLK_INTC_SYS>; + clocks = <&cpg CPG_MOD 408>; clock-names = "clk"; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; }; @@ -89,7 +89,7 @@ gpio0: gpio@e6050000 { gpio-ranges = <&pfc 0 0 32>; #interrupt-cells = <2>; interrupt-controller; - clocks = <&mstp9_clks R8A7794_CLK_GPIO0>; + clocks = <&cpg CPG_MOD 912>; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; }; @@ -102,7 +102,7 @@ gpio1: gpio@e6051000 { gpio-ranges = <&pfc 0 32 26>; #interrupt-cells = <2>; interrupt-controller; - clocks = <&mstp9_clks R8A7794_CLK_GPIO1>; + clocks = <&cpg CPG_MOD 911>; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; }; @@ -115,7 +115,7 @@ gpio2: gpio@e6052000 { gpio-ranges = <&pfc 0 64 32>; #interrupt-cells = <2>; interrupt-controller; - clocks = <&mstp9_clks R8A7794_CLK_GPIO2>; + clocks = <&cpg CPG_MOD 910>; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; }; @@ -128,7 +128,7 @@ gpio3: gpio@e6053000 { gpio-ranges = <&pfc 0 96 32>; #interrupt-cells = <2>; interrupt-controller; - clocks = <&mstp9_clks R8A7794_CLK_GPIO3>; + clocks = <&cpg CPG_MOD 909>; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; }; @@ -141,7 +141,7 @@ gpio4: gpio@e6054000 { gpio-ranges = <&pfc 0 128 32>; #interrupt-cells = <2>; interrupt-controller; - clocks = <&mstp9_clks R8A7794_CLK_GPIO4>; + clocks = <&cpg CPG_MOD 908>; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; }; @@ -154,7 +154,7 @@ gpio5: gpio@e6055000 { gpio-ranges = <&pfc 0 160 28>; #interrupt-cells = <2>; interrupt-controller; - clocks = <&mstp9_clks R8A7794_CLK_GPIO5>; + clocks = <&cpg CPG_MOD 907>; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; }; @@ -167,7 +167,7 @@ gpio6: gpio@e6055400 { gpio-ranges = <&pfc 0 192 26>; #interrupt-cells = <2>; interrupt-controller; - clocks = <&mstp9_clks R8A7794_CLK_GPIO6>; + clocks = <&cpg CPG_MOD 905>; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; }; @@ -176,7 +176,7 @@ cmt0: timer@ffca0000 { reg = <0 0xffca0000 0 0x1004>; interrupts = , ; - clocks = <&mstp1_clks R8A7794_CLK_CMT0>; + clocks = <&cpg CPG_MOD 124>; clock-names = "fck"; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; @@ -196,7 +196,7 @@ cmt1: timer@e6130000 { , , ; - clocks = <&mstp3_clks R8A7794_CLK_CMT1>; + clocks = <&cpg CPG_MOD 329>; clock-names = "fck"; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; @@ -228,7 +228,7 @@ irqc0: interrupt-controller@e61c0000 { , , ; - clocks = <&mstp4_clks R8A7794_CLK_IRQC>; + clocks = <&cpg CPG_MOD 407>; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; }; @@ -261,7 +261,7 @@ GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10", "ch11", "ch12", "ch13", "ch14"; - clocks = <&mstp2_clks R8A7794_CLK_SYS_DMAC0>; + clocks = <&cpg CPG_MOD 219>; clock-names = "fck"; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; #dma-cells = <1>; @@ -292,7 +292,7 @@ GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10", "ch11", "ch12", "ch13", "ch14"; - clocks = <&mstp2_clks R8A7794_CLK_SYS_DMAC1>; + clocks = <&cpg CPG_MOD 218>; clock-names = "fck"; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; #dma-cells = <1>; @@ -320,7 +320,7 @@ GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH "ch0", "ch1", "ch2", "ch3", "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10", "ch11", "ch12"; - clocks = <&mstp5_clks R8A7794_CLK_AUDIO_DMAC0>; + clocks = <&cpg CPG_MOD 502>; clock-names = "fck"; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; #dma-cells = <1>; @@ -332,7 +332,7 @@ scifa0: serial@e6c40000 { "renesas,rcar-gen2-scifa", "renesas,scifa"; reg = <0 0xe6c40000 0 64>; interrupts = ; - clocks = <&mstp2_clks R8A7794_CLK_SCIFA0>; + clocks = <&cpg CPG_MOD 204>; clock-names = "fck"; dmas = <&dmac0 0x21>, <&dmac0 0x22>, <&dmac1 0x21>, <&dmac1 0x22>; @@ -346,7 +346,7 @@ scifa1: serial@e6c50000 { "renesas,rcar-gen2-scifa", "renesas,scifa"; reg = <0 0xe6c50000 0 64>; interrupts = ; - clocks = <&mstp2_clks R8A7794_CLK_SCIFA1>; + clocks = <&cpg CPG_MOD 203>; clock-names = "fck"; dmas = <&dmac0 0x25>, <&dmac0 0x26>, <&dmac1 0x25>, <&dmac1 0x26>; @@ -360,7 +360,7 @@ scifa2: serial@e6c60000 { "renesas,rcar-gen2-scifa", "renesas,scifa"; reg = <0 0xe6c60000 0 64>; interrupts = ; - clocks = <&mstp2_clks R8A7794_CLK_SCIFA2>; + clocks = <&cpg CPG_MOD 202>; clock-names = "fck"; dmas = <&dmac0 0x27>, <&dmac0 0x28>, <&dmac1 0x27>, <&dmac1 0x28>; @@ -374,7 +374,7 @@ scifa3: serial@e6c70000 { "renesas,rcar-gen2-scifa", "renesas,scifa"; reg = <0 0xe6c70000 0 64>; interrupts = ; - clocks = <&mstp11_clks R8A7794_CLK_SCIFA3>; + clocks = <&cpg CPG_MOD 1106>; clock-names = "fck"; dmas = <&dmac0 0x1b>, <&dmac0 0x1c>, <&dmac1 0x1b>, <&dmac1 0x1c>; @@ -388,7 +388,7 @@ scifa4: serial@e6c78000 { "renesas,rcar-gen2-scifa", "renesas,scifa"; reg = <0 0xe6c78000 0 64>; interrupts = ; - clocks = <&mstp11_clks R8A7794_CLK_SCIFA4>; + clocks = <&cpg CPG_MOD 1107>; clock-names = "fck"; dmas = <&dmac0 0x1f>, <&dmac0 0x20>, <&dmac1 0x1f>, <&dmac1 0x20>; @@ -402,7 +402,7 @@ scifa5: serial@e6c80000 { "renesas,rcar-gen2-scifa", "renesas,scifa"; reg = <0 0xe6c80000 0 64>; interrupts = ; - clocks = <&mstp11_clks R8A7794_CLK_SCIFA5>; + clocks = <&cpg CPG_MOD 1108>; clock-names = "fck"; dmas = <&dmac0 0x23>, <&dmac0 0x24>, <&dmac1 0x23>, <&dmac1 0x24>; @@ -416,7 +416,7 @@ scifb0: serial@e6c20000 { "renesas,rcar-gen2-scifb", "renesas,scifb"; reg = <0 0xe6c20000 0 0x100>; interrupts = ; - clocks = <&mstp2_clks R8A7794_CLK_SCIFB0>; + clocks = <&cpg CPG_MOD 206>; clock-names = "fck"; dmas = <&dmac0 0x3d>, <&dmac0 0x3e>, <&dmac1 0x3d>, <&dmac1 0x3e>; @@ -430,7 +430,7 @@ scifb1: serial@e6c30000 { "renesas,rcar-gen2-scifb", "renesas,scifb"; reg = <0 0xe6c30000 0 0x100>; interrupts = ; - clocks = <&mstp2_clks R8A7794_CLK_SCIFB1>; + clocks = <&cpg CPG_MOD 207>; clock-names = "fck"; dmas = <&dmac0 0x19>, <&dmac0 0x1a>, <&dmac1 0x19>, <&dmac1 0x1a>; @@ -444,7 +444,7 @@ scifb2: serial@e6ce0000 { "renesas,rcar-gen2-scifb", "renesas,scifb"; reg = <0 0xe6ce0000 0 0x100>; interrupts = ; - clocks = <&mstp2_clks R8A7794_CLK_SCIFB2>; + clocks = <&cpg CPG_MOD 216>; clock-names = "fck"; dmas = <&dmac0 0x1d>, <&dmac0 0x1e>, <&dmac1 0x1d>, <&dmac1 0x1e>; @@ -458,7 +458,7 @@ scif0: serial@e6e60000 { "renesas,scif"; reg = <0 0xe6e60000 0 64>; interrupts = ; - clocks = <&mstp7_clks R8A7794_CLK_SCIF0>, <&zs_clk>, + clocks = <&cpg CPG_MOD 721>, <&cpg CPG_CORE R8A7794_CLK_ZS>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x29>, <&dmac0 0x2a>, @@ -473,7 +473,7 @@ scif1: serial@e6e68000 { "renesas,scif"; reg = <0 0xe6e68000 0 64>; interrupts = ; - clocks = <&mstp7_clks R8A7794_CLK_SCIF1>, <&zs_clk>, + clocks = <&cpg CPG_MOD 720>, <&cpg CPG_CORE R8A7794_CLK_ZS>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x2d>, <&dmac0 0x2e>, @@ -488,7 +488,7 @@ scif2: serial@e6e58000 { "renesas,scif"; reg = <0 0xe6e58000 0 64>; interrupts = ; - clocks = <&mstp7_clks R8A7794_CLK_SCIF2>, <&zs_clk>, + clocks = <&cpg CPG_MOD 719>, <&cpg CPG_CORE R8A7794_CLK_ZS>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x2b>, <&dmac0 0x2c>, @@ -503,7 +503,7 @@ scif3: serial@e6ea8000 { "renesas,scif"; reg = <0 0xe6ea8000 0 64>; interrupts = ; - clocks = <&mstp7_clks R8A7794_CLK_SCIF3>, <&zs_clk>, + clocks = <&cpg CPG_MOD 718>, <&cpg CPG_CORE R8A7794_CLK_ZS>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x2f>, <&dmac0 0x30>, @@ -518,7 +518,7 @@ scif4: serial@e6ee0000 { "renesas,scif"; reg = <0 0xe6ee0000 0 64>; interrupts = ; - clocks = <&mstp7_clks R8A7794_CLK_SCIF4>, <&zs_clk>, + clocks = <&cpg CPG_MOD 715>, <&cpg CPG_CORE R8A7794_CLK_ZS>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0xfb>, <&dmac0 0xfc>, @@ -533,7 +533,7 @@ scif5: serial@e6ee8000 { "renesas,scif"; reg = <0 0xe6ee8000 0 64>; interrupts = ; - clocks = <&mstp7_clks R8A7794_CLK_SCIF5>, <&zs_clk>, + clocks = <&cpg CPG_MOD 714>, <&cpg CPG_CORE R8A7794_CLK_ZS>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0xfd>, <&dmac0 0xfe>, @@ -548,7 +548,7 @@ hscif0: serial@e62c0000 { "renesas,rcar-gen2-hscif", "renesas,hscif"; reg = <0 0xe62c0000 0 96>; interrupts = ; - clocks = <&mstp7_clks R8A7794_CLK_HSCIF0>, <&zs_clk>, + clocks = <&cpg CPG_MOD 717>, <&cpg CPG_CORE R8A7794_CLK_ZS>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x39>, <&dmac0 0x3a>, @@ -563,7 +563,7 @@ hscif1: serial@e62c8000 { "renesas,rcar-gen2-hscif", "renesas,hscif"; reg = <0 0xe62c8000 0 96>; interrupts = ; - clocks = <&mstp7_clks R8A7794_CLK_HSCIF1>, <&zs_clk>, + clocks = <&cpg CPG_MOD 716>, <&cpg CPG_CORE R8A7794_CLK_ZS>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x4d>, <&dmac0 0x4e>, @@ -578,7 +578,7 @@ hscif2: serial@e62d0000 { "renesas,rcar-gen2-hscif", "renesas,hscif"; reg = <0 0xe62d0000 0 96>; interrupts = ; - clocks = <&mstp7_clks R8A7794_CLK_HSCIF2>, <&zs_clk>, + clocks = <&cpg CPG_MOD 713>, <&cpg CPG_CORE R8A7794_CLK_ZS>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x3b>, <&dmac0 0x3c>, @@ -610,7 +610,7 @@ ether: ethernet@ee700000 { compatible = "renesas,ether-r8a7794"; reg = <0 0xee700000 0 0x400>; interrupts = ; - clocks = <&mstp8_clks R8A7794_CLK_ETHER>; + clocks = <&cpg CPG_MOD 813>; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; phy-mode = "rmii"; #address-cells = <1>; @@ -623,7 +623,7 @@ avb: ethernet@e6800000 { "renesas,etheravb-rcar-gen2"; reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; interrupts = ; - clocks = <&mstp8_clks R8A7794_CLK_ETHERAVB>; + clocks = <&cpg CPG_MOD 812>; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; #address-cells = <1>; #size-cells = <0>; @@ -635,7 +635,7 @@ i2c0: i2c@e6508000 { compatible = "renesas,i2c-r8a7794", "renesas,rcar-gen2-i2c"; reg = <0 0xe6508000 0 0x40>; interrupts = ; - clocks = <&mstp9_clks R8A7794_CLK_I2C0>; + clocks = <&cpg CPG_MOD 931>; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; #address-cells = <1>; #size-cells = <0>; @@ -647,7 +647,7 @@ i2c1: i2c@e6518000 { compatible = "renesas,i2c-r8a7794", "renesas,rcar-gen2-i2c"; reg = <0 0xe6518000 0 0x40>; interrupts = ; - clocks = <&mstp9_clks R8A7794_CLK_I2C1>; + clocks = <&cpg CPG_MOD 930>; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; #address-cells = <1>; #size-cells = <0>; @@ -659,7 +659,7 @@ i2c2: i2c@e6530000 { compatible = "renesas,i2c-r8a7794", "renesas,rcar-gen2-i2c"; reg = <0 0xe6530000 0 0x40>; interrupts = ; - clocks = <&mstp9_clks R8A7794_CLK_I2C2>; + clocks = <&cpg CPG_MOD 929>; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; #address-cells = <1>; #size-cells = <0>; @@ -671,7 +671,7 @@ i2c3: i2c@e6540000 { compatible = "renesas,i2c-r8a7794", "renesas,rcar-gen2-i2c"; reg = <0 0xe6540000 0 0x40>; interrupts = ; - clocks = <&mstp9_clks R8A7794_CLK_I2C3>; + clocks = <&cpg CPG_MOD 928>; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; #address-cells = <1>; #size-cells = <0>; @@ -683,7 +683,7 @@ i2c4: i2c@e6520000 { compatible = "renesas,i2c-r8a7794", "renesas,rcar-gen2-i2c"; reg = <0 0xe6520000 0 0x40>; interrupts = ; - clocks = <&mstp9_clks R8A7794_CLK_I2C4>; + clocks = <&cpg CPG_MOD 927>; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; #address-cells = <1>; #size-cells = <0>; @@ -695,7 +695,7 @@ i2c5: i2c@e6528000 { compatible = "renesas,i2c-r8a7794", "renesas,rcar-gen2-i2c"; reg = <0 0xe6528000 0 0x40>; interrupts = ; - clocks = <&mstp9_clks R8A7794_CLK_I2C5>; + clocks = <&cpg CPG_MOD 925>; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; #address-cells = <1>; #size-cells = <0>; @@ -708,7 +708,7 @@ i2c6: i2c@e6500000 { "renesas,rmobile-iic"; reg = <0 0xe6500000 0 0x425>; interrupts = ; - clocks = <&mstp3_clks R8A7794_CLK_IIC0>; + clocks = <&cpg CPG_MOD 318>; dmas = <&dmac0 0x61>, <&dmac0 0x62>, <&dmac1 0x61>, <&dmac1 0x62>; dma-names = "tx", "rx", "tx", "rx"; @@ -723,7 +723,7 @@ i2c7: i2c@e6510000 { "renesas,rmobile-iic"; reg = <0 0xe6510000 0 0x425>; interrupts = ; - clocks = <&mstp3_clks R8A7794_CLK_IIC1>; + clocks = <&cpg CPG_MOD 323>; dmas = <&dmac0 0x65>, <&dmac0 0x66>, <&dmac1 0x65>, <&dmac1 0x66>; dma-names = "tx", "rx", "tx", "rx"; @@ -737,7 +737,7 @@ mmcif0: mmc@ee200000 { compatible = "renesas,mmcif-r8a7794", "renesas,sh-mmcif"; reg = <0 0xee200000 0 0x80>; interrupts = ; - clocks = <&mstp3_clks R8A7794_CLK_MMCIF0>; + clocks = <&cpg CPG_MOD 315>; dmas = <&dmac0 0xd1>, <&dmac0 0xd2>, <&dmac1 0xd1>, <&dmac1 0xd2>; dma-names = "tx", "rx", "tx", "rx"; @@ -750,7 +750,7 @@ sdhi0: sd@ee100000 { compatible = "renesas,sdhi-r8a7794"; reg = <0 0xee100000 0 0x328>; interrupts = ; - clocks = <&mstp3_clks R8A7794_CLK_SDHI0>; + clocks = <&cpg CPG_MOD 314>; dmas = <&dmac0 0xcd>, <&dmac0 0xce>, <&dmac1 0xcd>, <&dmac1 0xce>; dma-names = "tx", "rx", "tx", "rx"; @@ -763,7 +763,7 @@ sdhi1: sd@ee140000 { compatible = "renesas,sdhi-r8a7794"; reg = <0 0xee140000 0 0x100>; interrupts = ; - clocks = <&mstp3_clks R8A7794_CLK_SDHI1>; + clocks = <&cpg CPG_MOD 312>; dmas = <&dmac0 0xc1>, <&dmac0 0xc2>, <&dmac1 0xc1>, <&dmac1 0xc2>; dma-names = "tx", "rx", "tx", "rx"; @@ -776,7 +776,7 @@ sdhi2: sd@ee160000 { compatible = "renesas,sdhi-r8a7794"; reg = <0 0xee160000 0 0x100>; interrupts = ; - clocks = <&mstp3_clks R8A7794_CLK_SDHI2>; + clocks = <&cpg CPG_MOD 311>; dmas = <&dmac0 0xd3>, <&dmac0 0xd4>, <&dmac1 0xd3>, <&dmac1 0xd4>; dma-names = "tx", "rx", "tx", "rx"; @@ -789,7 +789,7 @@ qspi: spi@e6b10000 { compatible = "renesas,qspi-r8a7794", "renesas,qspi"; reg = <0 0xe6b10000 0 0x2c>; interrupts = ; - clocks = <&mstp9_clks R8A7794_CLK_QSPI_MOD>; + clocks = <&cpg CPG_MOD 917>; dmas = <&dmac0 0x17>, <&dmac0 0x18>, <&dmac1 0x17>, <&dmac1 0x18>; dma-names = "tx", "rx", "tx", "rx"; @@ -804,7 +804,7 @@ vin0: video@e6ef0000 { compatible = "renesas,vin-r8a7794", "renesas,rcar-gen2-vin"; reg = <0 0xe6ef0000 0 0x1000>; interrupts = ; - clocks = <&mstp8_clks R8A7794_CLK_VIN0>; + clocks = <&cpg CPG_MOD 811>; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; status = "disabled"; }; @@ -813,7 +813,7 @@ vin1: video@e6ef1000 { compatible = "renesas,vin-r8a7794", "renesas,rcar-gen2-vin"; reg = <0 0xe6ef1000 0 0x1000>; interrupts = ; - clocks = <&mstp8_clks R8A7794_CLK_VIN1>; + clocks = <&cpg CPG_MOD 810>; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; status = "disabled"; }; @@ -824,7 +824,7 @@ pci0: pci@ee090000 { reg = <0 0xee090000 0 0xc00>, <0 0xee080000 0 0x1100>; interrupts = ; - clocks = <&mstp7_clks R8A7794_CLK_EHCI>; + clocks = <&cpg CPG_MOD 703>; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; status = "disabled"; @@ -857,7 +857,7 @@ pci1: pci@ee0d0000 { reg = <0 0xee0d0000 0 0xc00>, <0 0xee0c0000 0 0x1100>; interrupts = ; - clocks = <&mstp7_clks R8A7794_CLK_EHCI>; + clocks = <&cpg CPG_MOD 703>; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; status = "disabled"; @@ -888,7 +888,7 @@ hsusb: usb@e6590000 { compatible = "renesas,usbhs-r8a7794", "renesas,rcar-gen2-usbhs"; reg = <0 0xe6590000 0 0x100>; interrupts = ; - clocks = <&mstp7_clks R8A7794_CLK_HSUSB>; + clocks = <&cpg CPG_MOD 704>; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; renesas,buswait = <4>; phys = <&usb0 1>; @@ -902,7 +902,7 @@ usbphy: usb-phy@e6590100 { reg = <0 0xe6590100 0 0x100>; #address-cells = <1>; #size-cells = <0>; - clocks = <&mstp7_clks R8A7794_CLK_HSUSB>; + clocks = <&cpg CPG_MOD 704>; clock-names = "usbhs"; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; status = "disabled"; @@ -921,7 +921,7 @@ vsp1@fe928000 { compatible = "renesas,vsp1"; reg = <0 0xfe928000 0 0x8000>; interrupts = ; - clocks = <&mstp1_clks R8A7794_CLK_VSP1_S>; + clocks = <&cpg CPG_MOD 131>; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; }; @@ -929,7 +929,7 @@ vsp1@fe930000 { compatible = "renesas,vsp1"; reg = <0 0xfe930000 0 0x8000>; interrupts = ; - clocks = <&mstp1_clks R8A7794_CLK_VSP1_DU0>; + clocks = <&cpg CPG_MOD 128>; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; }; @@ -939,8 +939,7 @@ du: display@feb00000 { reg-names = "du"; interrupts = , ; - clocks = <&mstp7_clks R8A7794_CLK_DU0>, - <&mstp7_clks R8A7794_CLK_DU1>; + clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>; clock-names = "du.0", "du.1"; status = "disabled"; @@ -965,8 +964,8 @@ can0: can@e6e80000 { compatible = "renesas,can-r8a7794", "renesas,rcar-gen2-can"; reg = <0 0xe6e80000 0 0x1000>; interrupts = ; - clocks = <&mstp9_clks R8A7794_CLK_RCAN0>, - <&cpg_clocks R8A7794_CLK_RCAN>, <&can_clk>; + clocks = <&cpg CPG_MOD 916>, <&cpg CPG_CORE R8A7794_CLK_RCAN>, + <&can_clk>; clock-names = "clkp1", "clkp2", "can_clk"; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; status = "disabled"; @@ -976,8 +975,8 @@ can1: can@e6e88000 { compatible = "renesas,can-r8a7794", "renesas,rcar-gen2-can"; reg = <0 0xe6e88000 0 0x1000>; interrupts = ; - clocks = <&mstp9_clks R8A7794_CLK_RCAN1>, - <&cpg_clocks R8A7794_CLK_RCAN>, <&can_clk>; + clocks = <&cpg CPG_MOD 915>, <&cpg CPG_CORE R8A7794_CLK_RCAN>, + <&can_clk>; clock-names = "clkp1", "clkp2", "can_clk"; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; status = "disabled"; @@ -1040,370 +1039,14 @@ audio_clkc: audio_clkc { clock-frequency = <0>; }; - /* Special CPG clocks */ - cpg_clocks: cpg_clocks@e6150000 { - compatible = "renesas,r8a7794-cpg-clocks", - "renesas,rcar-gen2-cpg-clocks"; + cpg: clock-controller@e6150000 { + compatible = "renesas,r8a7794-cpg-mssr"; reg = <0 0xe6150000 0 0x1000>; - clocks = <&extal_clk &usb_extal_clk>; - #clock-cells = <1>; - clock-output-names = "main", "pll0", "pll1", "pll3", - "lb", "qspi", "sdh", "sd0", "rcan"; + clocks = <&extal_clk>, <&usb_extal_clk>; + clock-names = "extal", "usb_extal"; + #clock-cells = <2>; #power-domain-cells = <0>; }; - /* Variable factor clocks */ - sd2_clk: sd2@e6150078 { - compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock"; - reg = <0 0xe6150078 0 4>; - clocks = <&pll1_div2_clk>; - #clock-cells = <0>; - }; - sd3_clk: sd3@e615026c { - compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock"; - reg = <0 0xe615026c 0 4>; - clocks = <&pll1_div2_clk>; - #clock-cells = <0>; - }; - mmc0_clk: mmc0@e6150240 { - compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock"; - reg = <0 0xe6150240 0 4>; - clocks = <&pll1_div2_clk>; - #clock-cells = <0>; - }; - - /* Fixed factor clocks */ - pll1_div2_clk: pll1_div2 { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7794_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <2>; - clock-mult = <1>; - }; - z2_clk: z2 { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7794_CLK_PLL0>; - #clock-cells = <0>; - clock-div = <1>; - clock-mult = <1>; - }; - zg_clk: zg { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7794_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <6>; - clock-mult = <1>; - }; - zx_clk: zx { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7794_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <3>; - clock-mult = <1>; - }; - zs_clk: zs { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7794_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <6>; - clock-mult = <1>; - }; - hp_clk: hp { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7794_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <12>; - clock-mult = <1>; - }; - i_clk: i { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7794_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <2>; - clock-mult = <1>; - }; - b_clk: b { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7794_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <12>; - clock-mult = <1>; - }; - p_clk: p { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7794_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <24>; - clock-mult = <1>; - }; - cl_clk: cl { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7794_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <48>; - clock-mult = <1>; - }; - m2_clk: m2 { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7794_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <8>; - clock-mult = <1>; - }; - rclk_clk: rclk { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7794_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <(48 * 1024)>; - clock-mult = <1>; - }; - oscclk_clk: oscclk { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7794_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <(12 * 1024)>; - clock-mult = <1>; - }; - zb3_clk: zb3 { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7794_CLK_PLL3>; - #clock-cells = <0>; - clock-div = <4>; - clock-mult = <1>; - }; - zb3d2_clk: zb3d2 { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7794_CLK_PLL3>; - #clock-cells = <0>; - clock-div = <8>; - clock-mult = <1>; - }; - ddr_clk: ddr { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7794_CLK_PLL3>; - #clock-cells = <0>; - clock-div = <8>; - clock-mult = <1>; - }; - mp_clk: mp { - compatible = "fixed-factor-clock"; - clocks = <&pll1_div2_clk>; - #clock-cells = <0>; - clock-div = <15>; - clock-mult = <1>; - }; - cp_clk: cp { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7794_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <48>; - clock-mult = <1>; - }; - - acp_clk: acp { - compatible = "fixed-factor-clock"; - clocks = <&extal_clk>; - #clock-cells = <0>; - clock-div = <2>; - clock-mult = <1>; - }; - - /* Gate clocks */ - mstp0_clks: mstp0_clks@e6150130 { - compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>; - clocks = <&mp_clk>; - #clock-cells = <1>; - clock-indices = ; - clock-output-names = "msiof0"; - }; - mstp1_clks: mstp1_clks@e6150134 { - compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>; - clocks = <&zs_clk>, <&zs_clk>, <&p_clk>, <&zg_clk>, <&zs_clk>, - <&zs_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>, <&cp_clk>, - <&zs_clk>, <&zs_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7794_CLK_VCP0 R8A7794_CLK_VPC0 R8A7794_CLK_TMU1 - R8A7794_CLK_3DG R8A7794_CLK_2DDMAC R8A7794_CLK_FDP1_0 - R8A7794_CLK_TMU3 R8A7794_CLK_TMU2 R8A7794_CLK_CMT0 - R8A7794_CLK_TMU0 R8A7794_CLK_VSP1_DU0 R8A7794_CLK_VSP1_S - >; - clock-output-names = - "vcp0", "vpc0", "tmu1", "3dg", "2ddmac", "fdp1-0", - "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du0", "vsps"; - }; - mstp2_clks: mstp2_clks@e6150138 { - compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>; - clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, - <&mp_clk>, <&mp_clk>, <&mp_clk>, - <&zs_clk>, <&zs_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7794_CLK_SCIFA2 R8A7794_CLK_SCIFA1 R8A7794_CLK_SCIFA0 - R8A7794_CLK_MSIOF2 R8A7794_CLK_SCIFB0 R8A7794_CLK_SCIFB1 - R8A7794_CLK_MSIOF1 R8A7794_CLK_SCIFB2 - R8A7794_CLK_SYS_DMAC1 R8A7794_CLK_SYS_DMAC0 - >; - clock-output-names = - "scifa2", "scifa1", "scifa0", "msiof2", "scifb0", - "scifb1", "msiof1", "scifb2", - "sys-dmac1", "sys-dmac0"; - }; - mstp3_clks: mstp3_clks@e615013c { - compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; - clocks = <&sd3_clk>, <&sd2_clk>, <&cpg_clocks R8A7794_CLK_SD0>, - <&mmc0_clk>, <&hp_clk>, <&hp_clk>, <&rclk_clk>, - <&hp_clk>, <&hp_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7794_CLK_SDHI2 R8A7794_CLK_SDHI1 R8A7794_CLK_SDHI0 - R8A7794_CLK_MMCIF0 R8A7794_CLK_IIC0 - R8A7794_CLK_IIC1 R8A7794_CLK_CMT1 - R8A7794_CLK_USBDMAC0 R8A7794_CLK_USBDMAC1 - >; - clock-output-names = - "sdhi2", "sdhi1", "sdhi0", - "mmcif0", "i2c6", "i2c7", - "cmt1", "usbdmac0", "usbdmac1"; - }; - mstp4_clks: mstp4_clks@e6150140 { - compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>; - clocks = <&cp_clk>, <&zs_clk>; - #clock-cells = <1>; - clock-indices = ; - clock-output-names = "irqc", "intc-sys"; - }; - mstp5_clks: mstp5_clks@e6150144 { - compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>; - clocks = <&hp_clk>, <&p_clk>; - #clock-cells = <1>; - clock-indices = ; - clock-output-names = "audmac0", "pwm"; - }; - mstp7_clks: mstp7_clks@e615014c { - compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>; - clocks = <&mp_clk>, <&hp_clk>, - <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>, - <&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, - <&zx_clk>, <&zx_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7794_CLK_EHCI R8A7794_CLK_HSUSB - R8A7794_CLK_HSCIF2 R8A7794_CLK_SCIF5 - R8A7794_CLK_SCIF4 R8A7794_CLK_HSCIF1 R8A7794_CLK_HSCIF0 - R8A7794_CLK_SCIF3 R8A7794_CLK_SCIF2 R8A7794_CLK_SCIF1 - R8A7794_CLK_SCIF0 - R8A7794_CLK_DU1 R8A7794_CLK_DU0 - >; - clock-output-names = - "ehci", "hsusb", - "hscif2", "scif5", "scif4", "hscif1", "hscif0", - "scif3", "scif2", "scif1", "scif0", - "du1", "du0"; - }; - mstp8_clks: mstp8_clks@e6150990 { - compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>; - clocks = <&zg_clk>, <&zg_clk>, <&hp_clk>, <&p_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7794_CLK_VIN1 R8A7794_CLK_VIN0 - R8A7794_CLK_ETHERAVB R8A7794_CLK_ETHER - >; - clock-output-names = - "vin1", "vin0", "etheravb", "ether"; - }; - mstp9_clks: mstp9_clks@e6150994 { - compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>; - clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>, - <&cp_clk>, <&cp_clk>, <&cp_clk>, <&p_clk>, - <&p_clk>, <&cpg_clocks R8A7794_CLK_QSPI>, - <&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>, - <&hp_clk>, <&hp_clk>; - #clock-cells = <1>; - clock-indices = ; - clock-output-names = - "gpio6", "gpio5", "gpio4", "gpio3", "gpio2", - "gpio1", "gpio0", "rcan1", "rcan0", "qspi_mod", - "i2c5", "i2c4", "i2c3", "i2c2", "i2c1", "i2c0"; - }; - mstp10_clks: mstp10_clks@e6150998 { - compatible = "renesas,r8a7794-mstp-clocks", - "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>; - clocks = <&p_clk>, - <&mstp10_clks R8A7794_CLK_SSI_ALL>, - <&mstp10_clks R8A7794_CLK_SSI_ALL>, - <&mstp10_clks R8A7794_CLK_SSI_ALL>, - <&mstp10_clks R8A7794_CLK_SSI_ALL>, - <&mstp10_clks R8A7794_CLK_SSI_ALL>, - <&mstp10_clks R8A7794_CLK_SSI_ALL>, - <&mstp10_clks R8A7794_CLK_SSI_ALL>, - <&mstp10_clks R8A7794_CLK_SSI_ALL>, - <&mstp10_clks R8A7794_CLK_SSI_ALL>, - <&mstp10_clks R8A7794_CLK_SSI_ALL>, - <&p_clk>, - <&mstp10_clks R8A7794_CLK_SCU_ALL>, - <&mstp10_clks R8A7794_CLK_SCU_ALL>, - <&mstp10_clks R8A7794_CLK_SCU_ALL>, - <&mstp10_clks R8A7794_CLK_SCU_ALL>, - <&mstp10_clks R8A7794_CLK_SCU_ALL>, - <&mstp10_clks R8A7794_CLK_SCU_ALL>, - <&mstp10_clks R8A7794_CLK_SCU_ALL>, - <&mstp10_clks R8A7794_CLK_SCU_ALL>, - <&mstp10_clks R8A7794_CLK_SCU_ALL>, - <&mstp10_clks R8A7794_CLK_SCU_ALL>; - #clock-cells = <1>; - clock-indices = ; - clock-output-names = "ssi-all", "ssi9", "ssi8", "ssi7", - "ssi6", "ssi5", "ssi4", "ssi3", - "ssi2", "ssi1", "ssi0", - "scu-all", "scu-dvc1", "scu-dvc0", - "scu-ctu1-mix1", "scu-ctu0-mix0", - "scu-src6", "scu-src5", "scu-src4", - "scu-src3", "scu-src2", "scu-src1"; - }; - mstp11_clks: mstp11_clks@e615099c { - compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>; - clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7794_CLK_SCIFA3 R8A7794_CLK_SCIFA4 R8A7794_CLK_SCIFA5 - >; - clock-output-names = "scifa3", "scifa4", "scifa5"; - }; }; rst: reset-controller@e6160000 { @@ -1490,31 +1133,20 @@ rcar_sound: sound@ec500000 { <0 0xec740000 0 0x200>; /* Audio DMAC peri peri */ reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; - clocks = <&mstp10_clks R8A7794_CLK_SSI_ALL>, - <&mstp10_clks R8A7794_CLK_SSI9>, - <&mstp10_clks R8A7794_CLK_SSI8>, - <&mstp10_clks R8A7794_CLK_SSI7>, - <&mstp10_clks R8A7794_CLK_SSI6>, - <&mstp10_clks R8A7794_CLK_SSI5>, - <&mstp10_clks R8A7794_CLK_SSI4>, - <&mstp10_clks R8A7794_CLK_SSI3>, - <&mstp10_clks R8A7794_CLK_SSI2>, - <&mstp10_clks R8A7794_CLK_SSI1>, - <&mstp10_clks R8A7794_CLK_SSI0>, - <&mstp10_clks R8A7794_CLK_SCU_SRC6>, - <&mstp10_clks R8A7794_CLK_SCU_SRC5>, - <&mstp10_clks R8A7794_CLK_SCU_SRC4>, - <&mstp10_clks R8A7794_CLK_SCU_SRC3>, - <&mstp10_clks R8A7794_CLK_SCU_SRC2>, - <&mstp10_clks R8A7794_CLK_SCU_SRC1>, - <&mstp10_clks R8A7794_CLK_SCU_CTU0_MIX0>, - <&mstp10_clks R8A7794_CLK_SCU_CTU1_MIX1>, - <&mstp10_clks R8A7794_CLK_SCU_CTU0_MIX0>, - <&mstp10_clks R8A7794_CLK_SCU_CTU1_MIX1>, - <&mstp10_clks R8A7794_CLK_SCU_DVC0>, - <&mstp10_clks R8A7794_CLK_SCU_DVC1>, + clocks = <&cpg CPG_MOD 1005>, + <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, + <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, + <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, + <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, + <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, + <&cpg CPG_MOD 1025>, <&cpg CPG_MOD 1026>, + <&cpg CPG_MOD 1027>, <&cpg CPG_MOD 1028>, + <&cpg CPG_MOD 1029>, <&cpg CPG_MOD 1030>, + <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>, + <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>, + <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, <&audio_clka>, <&audio_clkb>, <&audio_clkc>, - <&m2_clk>; + <&cpg CPG_CORE R8A7794_CLK_M2>; clock-names = "ssi-all", "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5", "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0", From 80e1a5f318850f2bbb5fa4a49fbfa9a8f3afd5f5 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 18 Aug 2017 11:16:54 +0200 Subject: [PATCH 05/48] ARM: dts: r8a7790: Stop grouping clocks under a "clocks" subnode The current practice is to not group clocks under a "clocks" subnode, but just put them together with the other on-SoC devices. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7790.dtsi | 125 ++++++++++++++++----------------- 1 file changed, 60 insertions(+), 65 deletions(-) diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index 5a31dfc0c316..70040c6c4cea 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -1061,77 +1061,72 @@ jpu: jpeg-codec@fe980000 { power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; }; - clocks { - #address-cells = <2>; - #size-cells = <2>; - ranges; + /* External root clock */ + extal_clk: extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; - /* External root clock */ - extal_clk: extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overriden by the board. */ - clock-frequency = <0>; - }; + /* External PCIe clock - can be overridden by the board */ + pcie_bus_clk: pcie_bus { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; - /* External PCIe clock - can be overridden by the board */ - pcie_bus_clk: pcie_bus { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; + /* + * The external audio clocks are configured as 0 Hz fixed frequency + * clocks by default. + * Boards that provide audio clocks should override them. + */ + audio_clk_a: audio_clk_a { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + audio_clk_b: audio_clk_b { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + audio_clk_c: audio_clk_c { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; - /* - * The external audio clocks are configured as 0 Hz fixed frequency clocks by - * default. Boards that provide audio clocks should override them. - */ - audio_clk_a: audio_clk_a { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - audio_clk_b: audio_clk_b { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - audio_clk_c: audio_clk_c { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; + /* External SCIF clock */ + scif_clk: scif { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; - /* External SCIF clock */ - scif_clk: scif { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; + /* External USB clock - can be overridden by the board */ + usb_extal_clk: usb_extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <48000000>; + }; - /* External USB clock - can be overridden by the board */ - usb_extal_clk: usb_extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <48000000>; - }; + /* External CAN clock */ + can_clk: can { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; - /* External CAN clock */ - can_clk: can { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; - - cpg: clock-controller@e6150000 { - compatible = "renesas,r8a7790-cpg-mssr"; - reg = <0 0xe6150000 0 0x1000>; - clocks = <&extal_clk>, <&usb_extal_clk>; - clock-names = "extal", "usb_extal"; - #clock-cells = <2>; - #power-domain-cells = <0>; - }; + cpg: clock-controller@e6150000 { + compatible = "renesas,r8a7790-cpg-mssr"; + reg = <0 0xe6150000 0 0x1000>; + clocks = <&extal_clk>, <&usb_extal_clk>; + clock-names = "extal", "usb_extal"; + #clock-cells = <2>; + #power-domain-cells = <0>; }; prr: chipid@ff000044 { From c67e243ccf06aec0fece59b8a1f3eb719e07b0e3 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 18 Aug 2017 11:16:56 +0200 Subject: [PATCH 06/48] ARM: dts: r8a7793: Stop grouping clocks under a "clocks" subnode The current practice is to not group clocks under a "clocks" subnode, but just put them together with the other on-SoC devices. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7793.dtsi | 115 ++++++++++++++++----------------- 1 file changed, 55 insertions(+), 60 deletions(-) diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi index ef8009c01e66..d48b97c853cd 100644 --- a/arch/arm/boot/dts/r8a7793.dtsi +++ b/arch/arm/boot/dts/r8a7793.dtsi @@ -972,71 +972,66 @@ can1: can@e6e88000 { status = "disabled"; }; - clocks { - #address-cells = <2>; - #size-cells = <2>; - ranges; + /* External root clock */ + extal_clk: extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; - /* External root clock */ - extal_clk: extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; + /* + * The external audio clocks are configured as 0 Hz fixed frequency + * clocks by default. + * Boards that provide audio clocks should override them. + */ + audio_clk_a: audio_clk_a { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + audio_clk_b: audio_clk_b { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + audio_clk_c: audio_clk_c { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; - /* - * The external audio clocks are configured as 0 Hz fixed frequency clocks by - * default. Boards that provide audio clocks should override them. - */ - audio_clk_a: audio_clk_a { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - audio_clk_b: audio_clk_b { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - audio_clk_c: audio_clk_c { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; + /* External USB clock - can be overridden by the board */ + usb_extal_clk: usb_extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <48000000>; + }; - /* External USB clock - can be overridden by the board */ - usb_extal_clk: usb_extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <48000000>; - }; + /* External CAN clock */ + can_clk: can { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; - /* External CAN clock */ - can_clk: can { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; + /* External SCIF clock */ + scif_clk: scif { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; - /* External SCIF clock */ - scif_clk: scif { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; - - /* Special CPG clocks */ - cpg: clock-controller@e6150000 { - compatible = "renesas,r8a7793-cpg-mssr"; - reg = <0 0xe6150000 0 0x1000>; - clocks = <&extal_clk>, <&usb_extal_clk>; - clock-names = "extal", "usb_extal"; - #clock-cells = <2>; - #power-domain-cells = <0>; - }; + /* Special CPG clocks */ + cpg: clock-controller@e6150000 { + compatible = "renesas,r8a7793-cpg-mssr"; + reg = <0 0xe6150000 0 0x1000>; + clocks = <&extal_clk>, <&usb_extal_clk>; + clock-names = "extal", "usb_extal"; + #clock-cells = <2>; + #power-domain-cells = <0>; }; rst: reset-controller@e6160000 { From 9fb1c8ff4ca36a13fdeb7e4161687eaf4685dc7a Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 18 Aug 2017 11:16:57 +0200 Subject: [PATCH 07/48] ARM: dts: r8a7794: Stop grouping clocks under a "clocks" subnode The current practice is to not group clocks under a "clocks" subnode, but just put them together with the other on-SoC devices. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7794.dtsi | 114 ++++++++++++++++----------------- 1 file changed, 54 insertions(+), 60 deletions(-) diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi index ebd44d9982be..a4c35d29f77c 100644 --- a/arch/arm/boot/dts/r8a7794.dtsi +++ b/arch/arm/boot/dts/r8a7794.dtsi @@ -982,71 +982,65 @@ can1: can@e6e88000 { status = "disabled"; }; - clocks { - #address-cells = <2>; - #size-cells = <2>; - ranges; + /* External root clock */ + extal_clk: extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; - /* External root clock */ - extal_clk: extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overriden by the board. */ - clock-frequency = <0>; - }; + /* External USB clock - can be overridden by the board */ + usb_extal_clk: usb_extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <48000000>; + }; - /* External USB clock - can be overridden by the board */ - usb_extal_clk: usb_extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <48000000>; - }; + /* External CAN clock */ + can_clk: can { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; - /* External CAN clock */ - can_clk: can { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; + /* External SCIF clock */ + scif_clk: scif { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; - /* External SCIF clock */ - scif_clk: scif { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; + /* + * The external audio clocks are configured as 0 Hz fixed + * frequency clocks by default. Boards that provide audio + * clocks should override them. + */ + audio_clka: audio_clka { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + audio_clkb: audio_clkb { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + audio_clkc: audio_clkc { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; - /* - * The external audio clocks are configured as 0 Hz fixed - * frequency clocks by default. Boards that provide audio - * clocks should override them. - */ - audio_clka: audio_clka { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - audio_clkb: audio_clkb { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - audio_clkc: audio_clkc { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - - cpg: clock-controller@e6150000 { - compatible = "renesas,r8a7794-cpg-mssr"; - reg = <0 0xe6150000 0 0x1000>; - clocks = <&extal_clk>, <&usb_extal_clk>; - clock-names = "extal", "usb_extal"; - #clock-cells = <2>; - #power-domain-cells = <0>; - }; + cpg: clock-controller@e6150000 { + compatible = "renesas,r8a7794-cpg-mssr"; + reg = <0 0xe6150000 0 0x1000>; + clocks = <&extal_clk>, <&usb_extal_clk>; + clock-names = "extal", "usb_extal"; + #clock-cells = <2>; + #power-domain-cells = <0>; }; rst: reset-controller@e6160000 { From 63ce8a617b5129f7cb20ed0d6d822a31ecca4696 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Mon, 14 Aug 2017 12:49:47 +0100 Subject: [PATCH 08/48] ARM: dts: r8a7743: Add SDHI controllers Add the SDHI controllers to the r8a7743 device tree. Signed-off-by: Biju Das Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7743.dtsi | 42 ++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi index 14222c72f0e0..6dd9b0b3d818 100644 --- a/arch/arm/boot/dts/r8a7743.dtsi +++ b/arch/arm/boot/dts/r8a7743.dtsi @@ -779,6 +779,48 @@ mmcif0: mmc@ee200000 { max-frequency = <97500000>; status = "disabled"; }; + + sdhi0: sd@ee100000 { + compatible = "renesas,sdhi-r8a7743"; + reg = <0 0xee100000 0 0x328>; + interrupts = ; + clocks = <&cpg CPG_MOD 314>; + dmas = <&dmac0 0xcd>, <&dmac0 0xce>, + <&dmac1 0xcd>, <&dmac1 0xce>; + dma-names = "tx", "rx", "tx", "rx"; + max-frequency = <195000000>; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 314>; + status = "disabled"; + }; + + sdhi1: sd@ee140000 { + compatible = "renesas,sdhi-r8a7743"; + reg = <0 0xee140000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 312>; + dmas = <&dmac0 0xc1>, <&dmac0 0xc2>, + <&dmac1 0xc1>, <&dmac1 0xc2>; + dma-names = "tx", "rx", "tx", "rx"; + max-frequency = <97500000>; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 312>; + status = "disabled"; + }; + + sdhi2: sd@ee160000 { + compatible = "renesas,sdhi-r8a7743"; + reg = <0 0xee160000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 311>; + dmas = <&dmac0 0xd3>, <&dmac0 0xd4>, + <&dmac1 0xd3>, <&dmac1 0xd4>; + dma-names = "tx", "rx", "tx", "rx"; + max-frequency = <97500000>; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 311>; + status = "disabled"; + }; }; /* External root clock */ From e75e71e7bcee2e04be8bbca6fb67af1a45fa128b Mon Sep 17 00:00:00 2001 From: Biju Das Date: Mon, 14 Aug 2017 12:49:48 +0100 Subject: [PATCH 09/48] ARM: dts: iwg20m: Enable SDHI0 controller Enable the SDHI0 controller on iWave RZG1M Qseven SOM. Signed-off-by: Biju Das Acked-by: Wolfram Sang Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7743-iwg20m.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm/boot/dts/r8a7743-iwg20m.dtsi b/arch/arm/boot/dts/r8a7743-iwg20m.dtsi index ff7993818637..4119737cb883 100644 --- a/arch/arm/boot/dts/r8a7743-iwg20m.dtsi +++ b/arch/arm/boot/dts/r8a7743-iwg20m.dtsi @@ -9,6 +9,7 @@ */ #include "r8a7743.dtsi" +#include / { compatible = "iwave,g20m", "renesas,r8a7743"; @@ -42,6 +43,12 @@ mmcif0_pins: mmc { groups = "mmc_data8_b", "mmc_ctrl"; function = "mmc"; }; + + sdhi0_pins: sd0 { + groups = "sdhi0_data4", "sdhi0_ctrl"; + function = "sdhi0"; + power-source = <3300>; + }; }; &mmcif0 { @@ -53,3 +60,13 @@ &mmcif0 { non-removable; status = "okay"; }; + +&sdhi0 { + pinctrl-0 = <&sdhi0_pins>; + pinctrl-names = "default"; + + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_3p3v>; + cd-gpios = <&gpio7 11 GPIO_ACTIVE_LOW>; + status = "okay"; +}; From 029efb3a03c5039902a6f1cfe266ed664cb97f20 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Mon, 14 Aug 2017 12:49:49 +0100 Subject: [PATCH 10/48] ARM: dts: iwg20d-q7: Add SDHI1 support Define the iWave RainboW-G20D-Qseven board dependent part of the SDHI1 device node. Signed-off-by: Biju Das Acked-by: Wolfram Sang Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7743-iwg20d-q7.dts | 48 +++++++++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts b/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts index 081af0192851..4ff27d23ecf0 100644 --- a/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts +++ b/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts @@ -19,6 +19,29 @@ aliases { serial0 = &scif0; ethernet0 = &avb; }; + + vcc_sdhi1: regulator-vcc-sdhi1 { + compatible = "regulator-fixed"; + + regulator-name = "SDHI1 Vcc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&gpio1 16 GPIO_ACTIVE_LOW>; + }; + + vccq_sdhi1: regulator-vccq-sdhi1 { + compatible = "regulator-gpio"; + + regulator-name = "SDHI1 VccQ"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + gpios = <&gpio2 30 GPIO_ACTIVE_LOW>; + gpios-states = <1>; + states = <3300000 1 + 1800000 0>; + }; }; &pfc { @@ -31,6 +54,18 @@ avb_pins: avb { groups = "avb_mdio", "avb_gmii"; function = "avb"; }; + + sdhi1_pins: sd1 { + groups = "sdhi1_data4", "sdhi1_ctrl"; + function = "sdhi1"; + power-source = <3300>; + }; + + sdhi1_pins_uhs: sd1_uhs { + groups = "sdhi1_data4", "sdhi1_ctrl"; + function = "sdhi1"; + power-source = <1800>; + }; }; &scif0 { @@ -54,3 +89,16 @@ phy3: ethernet-phy@3 { micrel,led-mode = <1>; }; }; + +&sdhi1 { + pinctrl-0 = <&sdhi1_pins>; + pinctrl-1 = <&sdhi1_pins_uhs>; + pinctrl-names = "default", "state_uhs"; + + vmmc-supply = <&vcc_sdhi1>; + vqmmc-supply = <&vccq_sdhi1>; + cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>; + sd-uhs-sdr50; + status = "okay"; +}; From 3163c03ec37aef502474122b857452fb948c7596 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Fri, 18 Aug 2017 15:56:01 +0100 Subject: [PATCH 11/48] ARM: dts: r8a7745: Add GPIO support Describe GPIO blocks in the R8A7745 device tree. Signed-off-by: Biju Das Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7745.dtsi | 105 +++++++++++++++++++++++++++++++++ 1 file changed, 105 insertions(+) diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi index aff90dfb8b32..18ca7ae8dd3f 100644 --- a/arch/arm/boot/dts/r8a7745.dtsi +++ b/arch/arm/boot/dts/r8a7745.dtsi @@ -65,6 +65,111 @@ gic: interrupt-controller@f1001000 { resets = <&cpg 408>; }; + gpio0: gpio@e6050000 { + compatible = "renesas,gpio-r8a7745", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6050000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 0 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 912>; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 912>; + }; + + gpio1: gpio@e6051000 { + compatible = "renesas,gpio-r8a7745", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6051000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 32 26>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 911>; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 911>; + }; + + gpio2: gpio@e6052000 { + compatible = "renesas,gpio-r8a7745", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6052000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 64 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 910>; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 910>; + }; + + gpio3: gpio@e6053000 { + compatible = "renesas,gpio-r8a7745", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6053000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 96 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 909>; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 909>; + }; + + gpio4: gpio@e6054000 { + compatible = "renesas,gpio-r8a7745", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6054000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 128 32>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 908>; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 908>; + }; + + gpio5: gpio@e6055000 { + compatible = "renesas,gpio-r8a7745", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6055000 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 160 28>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 907>; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 907>; + }; + + gpio6: gpio@e6055400 { + compatible = "renesas,gpio-r8a7745", + "renesas,rcar-gen2-gpio"; + reg = <0 0xe6055400 0 0x50>; + interrupts = ; + #gpio-cells = <2>; + gpio-controller; + gpio-ranges = <&pfc 0 192 26>; + #interrupt-cells = <2>; + interrupt-controller; + clocks = <&cpg CPG_MOD 905>; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 905>; + }; + irqc: interrupt-controller@e61c0000 { compatible = "renesas,irqc-r8a7745", "renesas,irqc"; #interrupt-cells = <2>; From c9a41f515d1e5955c44cb04926f5f5f4be4a0cd0 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Tue, 15 Aug 2017 11:54:19 +0100 Subject: [PATCH 12/48] ARM: dts: iwg22m: Add iWave RZG1E SODIMM SOM Add support for iWave RZG1E SODIMM System On Module. http://www.iwavesystems.com/rz-g1e-sodimm-module.html Signed-off-by: Biju Das Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7745-iwg22m.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) create mode 100644 arch/arm/boot/dts/r8a7745-iwg22m.dtsi diff --git a/arch/arm/boot/dts/r8a7745-iwg22m.dtsi b/arch/arm/boot/dts/r8a7745-iwg22m.dtsi new file mode 100644 index 000000000000..9dbd854aacf8 --- /dev/null +++ b/arch/arm/boot/dts/r8a7745-iwg22m.dtsi @@ -0,0 +1,24 @@ +/* + * Device Tree Source for the iWave-RZG1E-G22M SODIMM SOM + * + * Copyright (C) 2017 Renesas Electronics Corp. + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +#include "r8a7745.dtsi" + +/ { + compatible = "iwave,g22m", "renesas,r8a7745"; + + memory@40000000 { + device_type = "memory"; + reg = <0 0x40000000 0 0x20000000>; + }; +}; + +&extal_clk { + clock-frequency = <20000000>; +}; From a59eb272a4eae10eb4f7a3e7b15aa47d57b32699 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Tue, 15 Aug 2017 11:54:20 +0100 Subject: [PATCH 13/48] ARM: dts: iwg22d-sodimm: Add support for iWave G22D-SODIMM board Add support for iWave RainboW-G22D-SODIMM board based on RZ/G1E. Signed-off-by: Biju Das Signed-off-by: Simon Horman --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts | 29 +++++++++++++++++++++ 2 files changed, 30 insertions(+) create mode 100644 arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index faf46abaa4a2..e87f311ee9f2 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -725,6 +725,7 @@ dtb-$(CONFIG_ARCH_RENESAS) += \ r8a7740-armadillo800eva.dtb \ r8a7743-iwg20d-q7.dtb \ r8a7743-sk-rzg1m.dtb \ + r8a7745-iwg22d-sodimm.dtb \ r8a7745-sk-rzg1e.dtb \ r8a7778-bockw.dtb \ r8a7779-marzen.dtb \ diff --git a/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts b/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts new file mode 100644 index 000000000000..cbc19feb1565 --- /dev/null +++ b/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts @@ -0,0 +1,29 @@ +/* + * Device Tree Source for the iWave-RZG1E SODIMM carrier board + * + * Copyright (C) 2017 Renesas Electronics Corp. + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +/dts-v1/; +#include "r8a7745-iwg22m.dtsi" + +/ { + model = "iWave Systems RainboW-G22D-SODIMM board based on RZ/G1E"; + compatible = "iwave,g22d", "iwave,g22m", "renesas,r8a7745"; + + aliases { + serial0 = &scif4; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&scif4 { + status = "okay"; +}; From 282fbf4066e58b4c60683ab5cba30c5c998c7250 Mon Sep 17 00:00:00 2001 From: Fabrizio Castro Date: Tue, 22 Aug 2017 16:27:02 +0100 Subject: [PATCH 14/48] ARM: dts: r8a7745: Add I2C DT support Add I2C[0-5] devices to the r8a7745 device tree. Signed-off-by: Fabrizio Castro Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7745.dtsi | 93 ++++++++++++++++++++++++++++++++++ 1 file changed, 93 insertions(+) diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi index 18ca7ae8dd3f..2fa989f631a9 100644 --- a/arch/arm/boot/dts/r8a7745.dtsi +++ b/arch/arm/boot/dts/r8a7745.dtsi @@ -18,6 +18,15 @@ / { #address-cells = <2>; #size-cells = <2>; + aliases { + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c4 = &i2c4; + i2c5 = &i2c5; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -613,6 +622,90 @@ ether: ethernet@ee700000 { #size-cells = <0>; status = "disabled"; }; + + i2c0: i2c@e6508000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7745", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6508000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 931>; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 931>; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; + + i2c1: i2c@e6518000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7745", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6518000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 930>; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 930>; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; + + i2c2: i2c@e6530000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7745", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6530000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 929>; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 929>; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; + + i2c3: i2c@e6540000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7745", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6540000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 928>; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 928>; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; + + i2c4: i2c@e6520000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7745", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6520000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 927>; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 927>; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; + + i2c5: i2c@e6528000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,i2c-r8a7745", + "renesas,rcar-gen2-i2c"; + reg = <0 0xe6528000 0 0x40>; + interrupts = ; + clocks = <&cpg CPG_MOD 925>; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 925>; + i2c-scl-internal-delay-ns = <6>; + status = "disabled"; + }; }; /* External root clock */ From 933b16efb7be16e98a6bcd04ed59c5e91371afef Mon Sep 17 00:00:00 2001 From: Fabrizio Castro Date: Thu, 17 Aug 2017 18:31:42 +0100 Subject: [PATCH 15/48] ARM: dts: r8a7745: Add MMC interface support Add MMC interface support for r8a7745 SoC. Signed-off-by: Fabrizio Castro Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7745.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi index 2fa989f631a9..7fd2967b1f42 100644 --- a/arch/arm/boot/dts/r8a7745.dtsi +++ b/arch/arm/boot/dts/r8a7745.dtsi @@ -706,6 +706,22 @@ i2c5: i2c@e6528000 { i2c-scl-internal-delay-ns = <6>; status = "disabled"; }; + + mmcif0: mmc@ee200000 { + compatible = "renesas,mmcif-r8a7745", + "renesas,sh-mmcif"; + reg = <0 0xee200000 0 0x80>; + interrupts = ; + clocks = <&cpg CPG_MOD 315>; + dmas = <&dmac0 0xd1>, <&dmac0 0xd2>, + <&dmac1 0xd1>, <&dmac1 0xd2>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 315>; + reg-io-width = <4>; + max-frequency = <97500000>; + status = "disabled"; + }; }; /* External root clock */ From 3350ed907182049b806992f228021e7997183dda Mon Sep 17 00:00:00 2001 From: Fabrizio Castro Date: Thu, 17 Aug 2017 18:31:43 +0100 Subject: [PATCH 16/48] ARM: dts: iwg22m: Add eMMC support Add eMMC support for iW-RainboW-G22M-SM. Signed-off-by: Fabrizio Castro Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7745-iwg22m.dtsi | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm/boot/dts/r8a7745-iwg22m.dtsi b/arch/arm/boot/dts/r8a7745-iwg22m.dtsi index 9dbd854aacf8..afb1148baa2f 100644 --- a/arch/arm/boot/dts/r8a7745-iwg22m.dtsi +++ b/arch/arm/boot/dts/r8a7745-iwg22m.dtsi @@ -17,8 +17,34 @@ memory@40000000 { device_type = "memory"; reg = <0 0x40000000 0 0x20000000>; }; + + reg_3p3v: 3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; }; &extal_clk { clock-frequency = <20000000>; }; + +&pfc { + mmcif0_pins: mmc { + groups = "mmc_data8", "mmc_ctrl"; + function = "mmc"; + }; +}; + +&mmcif0 { + pinctrl-0 = <&mmcif0_pins>; + pinctrl-names = "default"; + + vmmc-supply = <®_3p3v>; + bus-width = <8>; + non-removable; + status = "okay"; +}; From a7b8f48d2fa14330a1886f7fd640187c8b4470c5 Mon Sep 17 00:00:00 2001 From: Fabrizio Castro Date: Tue, 22 Aug 2017 19:22:46 +0100 Subject: [PATCH 17/48] ARM: dts: iwg22m: Add RTC support Add support for the bq32000 RTC to the iwg22m device tree. Signed-off-by: Fabrizio Castro Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7745-iwg22m.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm/boot/dts/r8a7745-iwg22m.dtsi b/arch/arm/boot/dts/r8a7745-iwg22m.dtsi index afb1148baa2f..e306e7c5b644 100644 --- a/arch/arm/boot/dts/r8a7745-iwg22m.dtsi +++ b/arch/arm/boot/dts/r8a7745-iwg22m.dtsi @@ -37,6 +37,11 @@ mmcif0_pins: mmc { groups = "mmc_data8", "mmc_ctrl"; function = "mmc"; }; + + i2c3_pins: i2c3 { + groups = "i2c3_b"; + function = "i2c3"; + }; }; &mmcif0 { @@ -48,3 +53,16 @@ &mmcif0 { non-removable; status = "okay"; }; + +&i2c3 { + pinctrl-0 = <&i2c3_pins>; + pinctrl-names = "default"; + + status = "okay"; + clock-frequency = <400000>; + + rtc@68 { + compatible = "ti,bq32000"; + reg = <0x68>; + }; +}; From 362b334b17943d84d2878d2733f0ce695d45a2b6 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 23 Aug 2017 13:59:25 +0200 Subject: [PATCH 18/48] ARM: dts: r8a7791: Convert to new CPG/MSSR bindings Convert the R-Car M2-W SoC from the old "Renesas R-Car Gen2 Clock Pulse Generator (CPG)", "Renesas CPG DIV6 Clock", and "Renesas CPG Module Stop (MSTP) Clocks" DT bindings to the new unified "Renesas Clock Pulse Generator / Module Standby and Software Reset" DT bindings. This simplifies the DTS files, and allows to add support for reset control later. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7791-koelsch.dts | 4 +- arch/arm/boot/dts/r8a7791-porter.dts | 4 +- arch/arm/boot/dts/r8a7791.dtsi | 557 +++++--------------------- 3 files changed, 104 insertions(+), 461 deletions(-) diff --git a/arch/arm/boot/dts/r8a7791-koelsch.dts b/arch/arm/boot/dts/r8a7791-koelsch.dts index 0ce0b278e1cb..e164eda69baf 100644 --- a/arch/arm/boot/dts/r8a7791-koelsch.dts +++ b/arch/arm/boot/dts/r8a7791-koelsch.dts @@ -330,9 +330,7 @@ &du { pinctrl-names = "default"; status = "okay"; - clocks = <&mstp7_clks R8A7791_CLK_DU0>, - <&mstp7_clks R8A7791_CLK_DU1>, - <&mstp7_clks R8A7791_CLK_LVDS0>, + clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&cpg CPG_MOD 726>, <&x13_clk>, <&x2_clk>; clock-names = "du.0", "du.1", "lvds.0", "dclkin.0", "dclkin.1"; diff --git a/arch/arm/boot/dts/r8a7791-porter.dts b/arch/arm/boot/dts/r8a7791-porter.dts index 95da5cb9d37a..eb374956294f 100644 --- a/arch/arm/boot/dts/r8a7791-porter.dts +++ b/arch/arm/boot/dts/r8a7791-porter.dts @@ -419,9 +419,7 @@ &du { pinctrl-names = "default"; status = "okay"; - clocks = <&mstp7_clks R8A7791_CLK_DU0>, - <&mstp7_clks R8A7791_CLK_DU1>, - <&mstp7_clks R8A7791_CLK_LVDS0>, + clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, <&cpg CPG_MOD 726>, <&x3_clk>, <&x16_clk>; clock-names = "du.0", "du.1", "lvds.0", "dclkin.0", "dclkin.1"; diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi index f1d1a9772153..5fca397b722b 100644 --- a/arch/arm/boot/dts/r8a7791.dtsi +++ b/arch/arm/boot/dts/r8a7791.dtsi @@ -10,7 +10,7 @@ * kind, whether express or implied. */ -#include +#include #include #include #include @@ -51,7 +51,7 @@ cpu0: cpu@0 { reg = <0>; clock-frequency = <1500000000>; voltage-tolerance = <1>; /* 1% */ - clocks = <&cpg_clocks R8A7791_CLK_Z>; + clocks = <&cpg CPG_CORE R8A7791_CLK_Z>; clock-latency = <300000>; /* 300 us */ power-domains = <&sysc R8A7791_PD_CA15_CPU0>; next-level-cache = <&L2_CA15>; @@ -117,7 +117,7 @@ gic: interrupt-controller@f1001000 { <0 0xf1004000 0 0x2000>, <0 0xf1006000 0 0x2000>; interrupts = ; - clocks = <&mstp4_clks R8A7791_CLK_INTC_SYS>; + clocks = <&cpg CPG_MOD 408>; clock-names = "clk"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; }; @@ -131,7 +131,7 @@ gpio0: gpio@e6050000 { gpio-ranges = <&pfc 0 0 32>; #interrupt-cells = <2>; interrupt-controller; - clocks = <&mstp9_clks R8A7791_CLK_GPIO0>; + clocks = <&cpg CPG_MOD 912>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; }; @@ -144,7 +144,7 @@ gpio1: gpio@e6051000 { gpio-ranges = <&pfc 0 32 26>; #interrupt-cells = <2>; interrupt-controller; - clocks = <&mstp9_clks R8A7791_CLK_GPIO1>; + clocks = <&cpg CPG_MOD 911>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; }; @@ -157,7 +157,7 @@ gpio2: gpio@e6052000 { gpio-ranges = <&pfc 0 64 32>; #interrupt-cells = <2>; interrupt-controller; - clocks = <&mstp9_clks R8A7791_CLK_GPIO2>; + clocks = <&cpg CPG_MOD 910>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; }; @@ -170,7 +170,7 @@ gpio3: gpio@e6053000 { gpio-ranges = <&pfc 0 96 32>; #interrupt-cells = <2>; interrupt-controller; - clocks = <&mstp9_clks R8A7791_CLK_GPIO3>; + clocks = <&cpg CPG_MOD 909>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; }; @@ -183,7 +183,7 @@ gpio4: gpio@e6054000 { gpio-ranges = <&pfc 0 128 32>; #interrupt-cells = <2>; interrupt-controller; - clocks = <&mstp9_clks R8A7791_CLK_GPIO4>; + clocks = <&cpg CPG_MOD 908>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; }; @@ -196,7 +196,7 @@ gpio5: gpio@e6055000 { gpio-ranges = <&pfc 0 160 32>; #interrupt-cells = <2>; interrupt-controller; - clocks = <&mstp9_clks R8A7791_CLK_GPIO5>; + clocks = <&cpg CPG_MOD 907>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; }; @@ -209,7 +209,7 @@ gpio6: gpio@e6055400 { gpio-ranges = <&pfc 0 192 32>; #interrupt-cells = <2>; interrupt-controller; - clocks = <&mstp9_clks R8A7791_CLK_GPIO6>; + clocks = <&cpg CPG_MOD 905>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; }; @@ -222,7 +222,7 @@ gpio7: gpio@e6055800 { gpio-ranges = <&pfc 0 224 26>; #interrupt-cells = <2>; interrupt-controller; - clocks = <&mstp9_clks R8A7791_CLK_GPIO7>; + clocks = <&cpg CPG_MOD 904>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; }; @@ -232,7 +232,7 @@ thermal: thermal@e61f0000 { "renesas,rcar-thermal"; reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>; interrupts = ; - clocks = <&mstp5_clks R8A7791_CLK_THERMAL>; + clocks = <&cpg CPG_MOD 522>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; #thermal-sensor-cells = <0>; }; @@ -250,7 +250,7 @@ cmt0: timer@ffca0000 { reg = <0 0xffca0000 0 0x1004>; interrupts = , ; - clocks = <&mstp1_clks R8A7791_CLK_CMT0>; + clocks = <&cpg CPG_MOD 124>; clock-names = "fck"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; @@ -270,7 +270,7 @@ cmt1: timer@e6130000 { , , ; - clocks = <&mstp3_clks R8A7791_CLK_CMT1>; + clocks = <&cpg CPG_MOD 329>; clock-names = "fck"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; @@ -294,7 +294,7 @@ irqc0: interrupt-controller@e61c0000 { , , ; - clocks = <&mstp4_clks R8A7791_CLK_IRQC>; + clocks = <&cpg CPG_MOD 407>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; }; @@ -322,7 +322,7 @@ GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10", "ch11", "ch12", "ch13", "ch14"; - clocks = <&mstp2_clks R8A7791_CLK_SYS_DMAC0>; + clocks = <&cpg CPG_MOD 219>; clock-names = "fck"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; #dma-cells = <1>; @@ -353,7 +353,7 @@ GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10", "ch11", "ch12", "ch13", "ch14"; - clocks = <&mstp2_clks R8A7791_CLK_SYS_DMAC1>; + clocks = <&cpg CPG_MOD 218>; clock-names = "fck"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; #dma-cells = <1>; @@ -382,7 +382,7 @@ GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10", "ch11", "ch12"; - clocks = <&mstp5_clks R8A7791_CLK_AUDIO_DMAC0>; + clocks = <&cpg CPG_MOD 502>; clock-names = "fck"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; #dma-cells = <1>; @@ -411,7 +411,7 @@ GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10", "ch11", "ch12"; - clocks = <&mstp5_clks R8A7791_CLK_AUDIO_DMAC1>; + clocks = <&cpg CPG_MOD 501>; clock-names = "fck"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; #dma-cells = <1>; @@ -424,7 +424,7 @@ usb_dmac0: dma-controller@e65a0000 { interrupts = ; interrupt-names = "ch0", "ch1"; - clocks = <&mstp3_clks R8A7791_CLK_USBDMAC0>; + clocks = <&cpg CPG_MOD 330>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; #dma-cells = <1>; dma-channels = <2>; @@ -436,7 +436,7 @@ usb_dmac1: dma-controller@e65b0000 { interrupts = ; interrupt-names = "ch0", "ch1"; - clocks = <&mstp3_clks R8A7791_CLK_USBDMAC1>; + clocks = <&cpg CPG_MOD 331>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; #dma-cells = <1>; dma-channels = <2>; @@ -449,7 +449,7 @@ i2c0: i2c@e6508000 { compatible = "renesas,i2c-r8a7791", "renesas,rcar-gen2-i2c"; reg = <0 0xe6508000 0 0x40>; interrupts = ; - clocks = <&mstp9_clks R8A7791_CLK_I2C0>; + clocks = <&cpg CPG_MOD 931>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; i2c-scl-internal-delay-ns = <6>; status = "disabled"; @@ -461,7 +461,7 @@ i2c1: i2c@e6518000 { compatible = "renesas,i2c-r8a7791", "renesas,rcar-gen2-i2c"; reg = <0 0xe6518000 0 0x40>; interrupts = ; - clocks = <&mstp9_clks R8A7791_CLK_I2C1>; + clocks = <&cpg CPG_MOD 930>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; i2c-scl-internal-delay-ns = <6>; status = "disabled"; @@ -473,7 +473,7 @@ i2c2: i2c@e6530000 { compatible = "renesas,i2c-r8a7791", "renesas,rcar-gen2-i2c"; reg = <0 0xe6530000 0 0x40>; interrupts = ; - clocks = <&mstp9_clks R8A7791_CLK_I2C2>; + clocks = <&cpg CPG_MOD 929>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; i2c-scl-internal-delay-ns = <6>; status = "disabled"; @@ -485,7 +485,7 @@ i2c3: i2c@e6540000 { compatible = "renesas,i2c-r8a7791", "renesas,rcar-gen2-i2c"; reg = <0 0xe6540000 0 0x40>; interrupts = ; - clocks = <&mstp9_clks R8A7791_CLK_I2C3>; + clocks = <&cpg CPG_MOD 928>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; i2c-scl-internal-delay-ns = <6>; status = "disabled"; @@ -497,7 +497,7 @@ i2c4: i2c@e6520000 { compatible = "renesas,i2c-r8a7791", "renesas,rcar-gen2-i2c"; reg = <0 0xe6520000 0 0x40>; interrupts = ; - clocks = <&mstp9_clks R8A7791_CLK_I2C4>; + clocks = <&cpg CPG_MOD 927>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; i2c-scl-internal-delay-ns = <6>; status = "disabled"; @@ -510,7 +510,7 @@ i2c5: i2c@e6528000 { compatible = "renesas,i2c-r8a7791", "renesas,rcar-gen2-i2c"; reg = <0 0xe6528000 0 0x40>; interrupts = ; - clocks = <&mstp9_clks R8A7791_CLK_I2C5>; + clocks = <&cpg CPG_MOD 925>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; i2c-scl-internal-delay-ns = <110>; status = "disabled"; @@ -524,7 +524,7 @@ i2c6: i2c@e60b0000 { "renesas,rmobile-iic"; reg = <0 0xe60b0000 0 0x425>; interrupts = ; - clocks = <&mstp9_clks R8A7791_CLK_IICDVFS>; + clocks = <&cpg CPG_MOD 926>; dmas = <&dmac0 0x77>, <&dmac0 0x78>, <&dmac1 0x77>, <&dmac1 0x78>; dma-names = "tx", "rx", "tx", "rx"; @@ -539,7 +539,7 @@ i2c7: i2c@e6500000 { "renesas,rmobile-iic"; reg = <0 0xe6500000 0 0x425>; interrupts = ; - clocks = <&mstp3_clks R8A7791_CLK_IIC0>; + clocks = <&cpg CPG_MOD 318>; dmas = <&dmac0 0x61>, <&dmac0 0x62>, <&dmac1 0x61>, <&dmac1 0x62>; dma-names = "tx", "rx", "tx", "rx"; @@ -554,7 +554,7 @@ i2c8: i2c@e6510000 { "renesas,rmobile-iic"; reg = <0 0xe6510000 0 0x425>; interrupts = ; - clocks = <&mstp3_clks R8A7791_CLK_IIC1>; + clocks = <&cpg CPG_MOD 323>; dmas = <&dmac0 0x65>, <&dmac0 0x66>, <&dmac1 0x65>, <&dmac1 0x66>; dma-names = "tx", "rx", "tx", "rx"; @@ -571,7 +571,7 @@ mmcif0: mmc@ee200000 { compatible = "renesas,mmcif-r8a7791", "renesas,sh-mmcif"; reg = <0 0xee200000 0 0x80>; interrupts = ; - clocks = <&mstp3_clks R8A7791_CLK_MMCIF0>; + clocks = <&cpg CPG_MOD 315>; dmas = <&dmac0 0xd1>, <&dmac0 0xd2>, <&dmac1 0xd1>, <&dmac1 0xd2>; dma-names = "tx", "rx", "tx", "rx"; @@ -585,7 +585,7 @@ sdhi0: sd@ee100000 { compatible = "renesas,sdhi-r8a7791"; reg = <0 0xee100000 0 0x328>; interrupts = ; - clocks = <&mstp3_clks R8A7791_CLK_SDHI0>; + clocks = <&cpg CPG_MOD 314>; dmas = <&dmac0 0xcd>, <&dmac0 0xce>, <&dmac1 0xcd>, <&dmac1 0xce>; dma-names = "tx", "rx", "tx", "rx"; @@ -598,7 +598,7 @@ sdhi1: sd@ee140000 { compatible = "renesas,sdhi-r8a7791"; reg = <0 0xee140000 0 0x100>; interrupts = ; - clocks = <&mstp3_clks R8A7791_CLK_SDHI1>; + clocks = <&cpg CPG_MOD 312>; dmas = <&dmac0 0xc1>, <&dmac0 0xc2>, <&dmac1 0xc1>, <&dmac1 0xc2>; dma-names = "tx", "rx", "tx", "rx"; @@ -611,7 +611,7 @@ sdhi2: sd@ee160000 { compatible = "renesas,sdhi-r8a7791"; reg = <0 0xee160000 0 0x100>; interrupts = ; - clocks = <&mstp3_clks R8A7791_CLK_SDHI2>; + clocks = <&cpg CPG_MOD 311>; dmas = <&dmac0 0xd3>, <&dmac0 0xd4>, <&dmac1 0xd3>, <&dmac1 0xd4>; dma-names = "tx", "rx", "tx", "rx"; @@ -625,7 +625,7 @@ scifa0: serial@e6c40000 { "renesas,rcar-gen2-scifa", "renesas,scifa"; reg = <0 0xe6c40000 0 64>; interrupts = ; - clocks = <&mstp2_clks R8A7791_CLK_SCIFA0>; + clocks = <&cpg CPG_MOD 204>; clock-names = "fck"; dmas = <&dmac0 0x21>, <&dmac0 0x22>, <&dmac1 0x21>, <&dmac1 0x22>; @@ -639,7 +639,7 @@ scifa1: serial@e6c50000 { "renesas,rcar-gen2-scifa", "renesas,scifa"; reg = <0 0xe6c50000 0 64>; interrupts = ; - clocks = <&mstp2_clks R8A7791_CLK_SCIFA1>; + clocks = <&cpg CPG_MOD 203>; clock-names = "fck"; dmas = <&dmac0 0x25>, <&dmac0 0x26>, <&dmac1 0x25>, <&dmac1 0x26>; @@ -653,7 +653,7 @@ scifa2: serial@e6c60000 { "renesas,rcar-gen2-scifa", "renesas,scifa"; reg = <0 0xe6c60000 0 64>; interrupts = ; - clocks = <&mstp2_clks R8A7791_CLK_SCIFA2>; + clocks = <&cpg CPG_MOD 202>; clock-names = "fck"; dmas = <&dmac0 0x27>, <&dmac0 0x28>, <&dmac1 0x27>, <&dmac1 0x28>; @@ -667,7 +667,7 @@ scifa3: serial@e6c70000 { "renesas,rcar-gen2-scifa", "renesas,scifa"; reg = <0 0xe6c70000 0 64>; interrupts = ; - clocks = <&mstp11_clks R8A7791_CLK_SCIFA3>; + clocks = <&cpg CPG_MOD 1106>; clock-names = "fck"; dmas = <&dmac0 0x1b>, <&dmac0 0x1c>, <&dmac1 0x1b>, <&dmac1 0x1c>; @@ -681,7 +681,7 @@ scifa4: serial@e6c78000 { "renesas,rcar-gen2-scifa", "renesas,scifa"; reg = <0 0xe6c78000 0 64>; interrupts = ; - clocks = <&mstp11_clks R8A7791_CLK_SCIFA4>; + clocks = <&cpg CPG_MOD 1107>; clock-names = "fck"; dmas = <&dmac0 0x1f>, <&dmac0 0x20>, <&dmac1 0x1f>, <&dmac1 0x20>; @@ -695,7 +695,7 @@ scifa5: serial@e6c80000 { "renesas,rcar-gen2-scifa", "renesas,scifa"; reg = <0 0xe6c80000 0 64>; interrupts = ; - clocks = <&mstp11_clks R8A7791_CLK_SCIFA5>; + clocks = <&cpg CPG_MOD 1108>; clock-names = "fck"; dmas = <&dmac0 0x23>, <&dmac0 0x24>, <&dmac1 0x23>, <&dmac1 0x24>; @@ -709,7 +709,7 @@ scifb0: serial@e6c20000 { "renesas,rcar-gen2-scifb", "renesas,scifb"; reg = <0 0xe6c20000 0 0x100>; interrupts = ; - clocks = <&mstp2_clks R8A7791_CLK_SCIFB0>; + clocks = <&cpg CPG_MOD 206>; clock-names = "fck"; dmas = <&dmac0 0x3d>, <&dmac0 0x3e>, <&dmac1 0x3d>, <&dmac1 0x3e>; @@ -723,7 +723,7 @@ scifb1: serial@e6c30000 { "renesas,rcar-gen2-scifb", "renesas,scifb"; reg = <0 0xe6c30000 0 0x100>; interrupts = ; - clocks = <&mstp2_clks R8A7791_CLK_SCIFB1>; + clocks = <&cpg CPG_MOD 207>; clock-names = "fck"; dmas = <&dmac0 0x19>, <&dmac0 0x1a>, <&dmac1 0x19>, <&dmac1 0x1a>; @@ -737,7 +737,7 @@ scifb2: serial@e6ce0000 { "renesas,rcar-gen2-scifb", "renesas,scifb"; reg = <0 0xe6ce0000 0 0x100>; interrupts = ; - clocks = <&mstp2_clks R8A7791_CLK_SCIFB2>; + clocks = <&cpg CPG_MOD 216>; clock-names = "fck"; dmas = <&dmac0 0x1d>, <&dmac0 0x1e>, <&dmac1 0x1d>, <&dmac1 0x1e>; @@ -751,7 +751,7 @@ scif0: serial@e6e60000 { "renesas,scif"; reg = <0 0xe6e60000 0 64>; interrupts = ; - clocks = <&mstp7_clks R8A7791_CLK_SCIF0>, <&zs_clk>, + clocks = <&cpg CPG_MOD 721>, <&cpg CPG_CORE R8A7791_CLK_ZS>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x29>, <&dmac0 0x2a>, @@ -766,7 +766,7 @@ scif1: serial@e6e68000 { "renesas,scif"; reg = <0 0xe6e68000 0 64>; interrupts = ; - clocks = <&mstp7_clks R8A7791_CLK_SCIF1>, <&zs_clk>, + clocks = <&cpg CPG_MOD 720>, <&cpg CPG_CORE R8A7791_CLK_ZS>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x2d>, <&dmac0 0x2e>, @@ -779,7 +779,7 @@ scif1: serial@e6e68000 { adc: adc@e6e54000 { compatible = "renesas,r8a7791-gyroadc", "renesas,rcar-gyroadc"; reg = <0 0xe6e54000 0 64>; - clocks = <&mstp9_clks R8A7791_CLK_GYROADC>; + clocks = <&cpg CPG_MOD 901>; clock-names = "fck"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; status = "disabled"; @@ -790,7 +790,7 @@ scif2: serial@e6e58000 { "renesas,scif"; reg = <0 0xe6e58000 0 64>; interrupts = ; - clocks = <&mstp7_clks R8A7791_CLK_SCIF2>, <&zs_clk>, + clocks = <&cpg CPG_MOD 719>, <&cpg CPG_CORE R8A7791_CLK_ZS>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x2b>, <&dmac0 0x2c>, @@ -805,7 +805,7 @@ scif3: serial@e6ea8000 { "renesas,scif"; reg = <0 0xe6ea8000 0 64>; interrupts = ; - clocks = <&mstp7_clks R8A7791_CLK_SCIF3>, <&zs_clk>, + clocks = <&cpg CPG_MOD 718>, <&cpg CPG_CORE R8A7791_CLK_ZS>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x2f>, <&dmac0 0x30>, @@ -820,7 +820,7 @@ scif4: serial@e6ee0000 { "renesas,scif"; reg = <0 0xe6ee0000 0 64>; interrupts = ; - clocks = <&mstp7_clks R8A7791_CLK_SCIF4>, <&zs_clk>, + clocks = <&cpg CPG_MOD 715>, <&cpg CPG_CORE R8A7791_CLK_ZS>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0xfb>, <&dmac0 0xfc>, @@ -835,7 +835,7 @@ scif5: serial@e6ee8000 { "renesas,scif"; reg = <0 0xe6ee8000 0 64>; interrupts = ; - clocks = <&mstp7_clks R8A7791_CLK_SCIF5>, <&zs_clk>, + clocks = <&cpg CPG_MOD 714>, <&cpg CPG_CORE R8A7791_CLK_ZS>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0xfd>, <&dmac0 0xfe>, @@ -850,7 +850,7 @@ hscif0: serial@e62c0000 { "renesas,rcar-gen2-hscif", "renesas,hscif"; reg = <0 0xe62c0000 0 96>; interrupts = ; - clocks = <&mstp7_clks R8A7791_CLK_HSCIF0>, <&zs_clk>, + clocks = <&cpg CPG_MOD 717>, <&cpg CPG_CORE R8A7791_CLK_ZS>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x39>, <&dmac0 0x3a>, @@ -865,7 +865,7 @@ hscif1: serial@e62c8000 { "renesas,rcar-gen2-hscif", "renesas,hscif"; reg = <0 0xe62c8000 0 96>; interrupts = ; - clocks = <&mstp7_clks R8A7791_CLK_HSCIF1>, <&zs_clk>, + clocks = <&cpg CPG_MOD 716>, <&cpg CPG_CORE R8A7791_CLK_ZS>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x4d>, <&dmac0 0x4e>, @@ -880,7 +880,7 @@ hscif2: serial@e62d0000 { "renesas,rcar-gen2-hscif", "renesas,hscif"; reg = <0 0xe62d0000 0 96>; interrupts = ; - clocks = <&mstp7_clks R8A7791_CLK_HSCIF2>, <&zs_clk>, + clocks = <&cpg CPG_MOD 713>, <&cpg CPG_CORE R8A7791_CLK_ZS>, <&scif_clk>; clock-names = "fck", "brg_int", "scif_clk"; dmas = <&dmac0 0x3b>, <&dmac0 0x3c>, @@ -912,7 +912,7 @@ ether: ethernet@ee700000 { compatible = "renesas,ether-r8a7791"; reg = <0 0xee700000 0 0x400>; interrupts = ; - clocks = <&mstp8_clks R8A7791_CLK_ETHER>; + clocks = <&cpg CPG_MOD 813>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; phy-mode = "rmii"; #address-cells = <1>; @@ -925,7 +925,7 @@ avb: ethernet@e6800000 { "renesas,etheravb-rcar-gen2"; reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; interrupts = ; - clocks = <&mstp8_clks R8A7791_CLK_ETHERAVB>; + clocks = <&cpg CPG_MOD 812>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; #address-cells = <1>; #size-cells = <0>; @@ -936,7 +936,7 @@ sata0: sata@ee300000 { compatible = "renesas,sata-r8a7791", "renesas,rcar-gen2-sata"; reg = <0 0xee300000 0 0x2000>; interrupts = ; - clocks = <&mstp8_clks R8A7791_CLK_SATA0>; + clocks = <&cpg CPG_MOD 815>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; status = "disabled"; }; @@ -945,7 +945,7 @@ sata1: sata@ee500000 { compatible = "renesas,sata-r8a7791", "renesas,rcar-gen2-sata"; reg = <0 0xee500000 0 0x2000>; interrupts = ; - clocks = <&mstp8_clks R8A7791_CLK_SATA1>; + clocks = <&cpg CPG_MOD 814>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; status = "disabled"; }; @@ -954,7 +954,7 @@ hsusb: usb@e6590000 { compatible = "renesas,usbhs-r8a7791", "renesas,rcar-gen2-usbhs"; reg = <0 0xe6590000 0 0x100>; interrupts = ; - clocks = <&mstp7_clks R8A7791_CLK_HSUSB>; + clocks = <&cpg CPG_MOD 704>; dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, <&usb_dmac1 0>, <&usb_dmac1 1>; dma-names = "ch0", "ch1", "ch2", "ch3"; @@ -971,7 +971,7 @@ usbphy: usb-phy@e6590100 { reg = <0 0xe6590100 0 0x100>; #address-cells = <1>; #size-cells = <0>; - clocks = <&mstp7_clks R8A7791_CLK_HSUSB>; + clocks = <&cpg CPG_MOD 704>; clock-names = "usbhs"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; status = "disabled"; @@ -990,7 +990,7 @@ vin0: video@e6ef0000 { compatible = "renesas,vin-r8a7791", "renesas,rcar-gen2-vin"; reg = <0 0xe6ef0000 0 0x1000>; interrupts = ; - clocks = <&mstp8_clks R8A7791_CLK_VIN0>; + clocks = <&cpg CPG_MOD 811>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; status = "disabled"; }; @@ -999,7 +999,7 @@ vin1: video@e6ef1000 { compatible = "renesas,vin-r8a7791", "renesas,rcar-gen2-vin"; reg = <0 0xe6ef1000 0 0x1000>; interrupts = ; - clocks = <&mstp8_clks R8A7791_CLK_VIN1>; + clocks = <&cpg CPG_MOD 810>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; status = "disabled"; }; @@ -1008,7 +1008,7 @@ vin2: video@e6ef2000 { compatible = "renesas,vin-r8a7791", "renesas,rcar-gen2-vin"; reg = <0 0xe6ef2000 0 0x1000>; interrupts = ; - clocks = <&mstp8_clks R8A7791_CLK_VIN2>; + clocks = <&cpg CPG_MOD 809>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; status = "disabled"; }; @@ -1017,7 +1017,7 @@ vsp1@fe928000 { compatible = "renesas,vsp1"; reg = <0 0xfe928000 0 0x8000>; interrupts = ; - clocks = <&mstp1_clks R8A7791_CLK_VSP1_S>; + clocks = <&cpg CPG_MOD 131>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; }; @@ -1025,7 +1025,7 @@ vsp1@fe930000 { compatible = "renesas,vsp1"; reg = <0 0xfe930000 0 0x8000>; interrupts = ; - clocks = <&mstp1_clks R8A7791_CLK_VSP1_DU0>; + clocks = <&cpg CPG_MOD 128>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; }; @@ -1033,7 +1033,7 @@ vsp1@fe938000 { compatible = "renesas,vsp1"; reg = <0 0xfe938000 0 0x8000>; interrupts = ; - clocks = <&mstp1_clks R8A7791_CLK_VSP1_DU1>; + clocks = <&cpg CPG_MOD 127>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; }; @@ -1044,9 +1044,9 @@ du: display@feb00000 { reg-names = "du", "lvds.0"; interrupts = , ; - clocks = <&mstp7_clks R8A7791_CLK_DU0>, - <&mstp7_clks R8A7791_CLK_DU1>, - <&mstp7_clks R8A7791_CLK_LVDS0>; + clocks = <&cpg CPG_MOD 724>, + <&cpg CPG_MOD 723>, + <&cpg CPG_MOD 726>; clock-names = "du.0", "du.1", "lvds.0"; status = "disabled"; @@ -1071,8 +1071,8 @@ can0: can@e6e80000 { compatible = "renesas,can-r8a7791", "renesas,rcar-gen2-can"; reg = <0 0xe6e80000 0 0x1000>; interrupts = ; - clocks = <&mstp9_clks R8A7791_CLK_RCAN0>, - <&cpg_clocks R8A7791_CLK_RCAN>, <&can_clk>; + clocks = <&cpg CPG_MOD 916>, <&cpg CPG_CORE R8A7791_CLK_RCAN>, + <&can_clk>; clock-names = "clkp1", "clkp2", "can_clk"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; status = "disabled"; @@ -1082,8 +1082,8 @@ can1: can@e6e88000 { compatible = "renesas,can-r8a7791", "renesas,rcar-gen2-can"; reg = <0 0xe6e88000 0 0x1000>; interrupts = ; - clocks = <&mstp9_clks R8A7791_CLK_RCAN1>, - <&cpg_clocks R8A7791_CLK_RCAN>, <&can_clk>; + clocks = <&cpg CPG_MOD 915>, <&cpg CPG_CORE R8A7791_CLK_RCAN>, + <&can_clk>; clock-names = "clkp1", "clkp2", "can_clk"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; status = "disabled"; @@ -1093,7 +1093,7 @@ jpu: jpeg-codec@fe980000 { compatible = "renesas,jpu-r8a7791", "renesas,rcar-gen2-jpu"; reg = <0 0xfe980000 0 0x10300>; interrupts = ; - clocks = <&mstp1_clks R8A7791_CLK_JPU>; + clocks = <&cpg CPG_MOD 106>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; }; @@ -1160,368 +1160,14 @@ can_clk: can { clock-frequency = <0>; }; - /* Special CPG clocks */ - cpg_clocks: cpg_clocks@e6150000 { - compatible = "renesas,r8a7791-cpg-clocks", - "renesas,rcar-gen2-cpg-clocks"; + cpg: clock-controller@e6150000 { + compatible = "renesas,r8a7791-cpg-mssr"; reg = <0 0xe6150000 0 0x1000>; - clocks = <&extal_clk &usb_extal_clk>; - #clock-cells = <1>; - clock-output-names = "main", "pll0", "pll1", "pll3", - "lb", "qspi", "sdh", "sd0", "z", - "rcan", "adsp"; + clocks = <&extal_clk>, <&usb_extal_clk>; + clock-names = "extal", "usb_extal"; + #clock-cells = <2>; #power-domain-cells = <0>; }; - - /* Variable factor clocks */ - sd2_clk: sd2@e6150078 { - compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock"; - reg = <0 0xe6150078 0 4>; - clocks = <&pll1_div2_clk>; - #clock-cells = <0>; - }; - sd3_clk: sd3@e615026c { - compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock"; - reg = <0 0xe615026c 0 4>; - clocks = <&pll1_div2_clk>; - #clock-cells = <0>; - }; - mmc0_clk: mmc0@e6150240 { - compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock"; - reg = <0 0xe6150240 0 4>; - clocks = <&pll1_div2_clk>; - #clock-cells = <0>; - }; - ssp_clk: ssp@e6150248 { - compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock"; - reg = <0 0xe6150248 0 4>; - clocks = <&pll1_div2_clk>; - #clock-cells = <0>; - }; - ssprs_clk: ssprs@e615024c { - compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock"; - reg = <0 0xe615024c 0 4>; - clocks = <&pll1_div2_clk>; - #clock-cells = <0>; - }; - - /* Fixed factor clocks */ - pll1_div2_clk: pll1_div2 { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7791_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <2>; - clock-mult = <1>; - }; - zg_clk: zg { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7791_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <3>; - clock-mult = <1>; - }; - zx_clk: zx { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7791_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <3>; - clock-mult = <1>; - }; - zs_clk: zs { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7791_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <6>; - clock-mult = <1>; - }; - hp_clk: hp { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7791_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <12>; - clock-mult = <1>; - }; - i_clk: i { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7791_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <2>; - clock-mult = <1>; - }; - b_clk: b { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7791_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <12>; - clock-mult = <1>; - }; - p_clk: p { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7791_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <24>; - clock-mult = <1>; - }; - cl_clk: cl { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7791_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <48>; - clock-mult = <1>; - }; - m2_clk: m2 { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7791_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <8>; - clock-mult = <1>; - }; - rclk_clk: rclk { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7791_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <(48 * 1024)>; - clock-mult = <1>; - }; - oscclk_clk: oscclk { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7791_CLK_PLL1>; - #clock-cells = <0>; - clock-div = <(12 * 1024)>; - clock-mult = <1>; - }; - zb3_clk: zb3 { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7791_CLK_PLL3>; - #clock-cells = <0>; - clock-div = <4>; - clock-mult = <1>; - }; - zb3d2_clk: zb3d2 { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7791_CLK_PLL3>; - #clock-cells = <0>; - clock-div = <8>; - clock-mult = <1>; - }; - ddr_clk: ddr { - compatible = "fixed-factor-clock"; - clocks = <&cpg_clocks R8A7791_CLK_PLL3>; - #clock-cells = <0>; - clock-div = <8>; - clock-mult = <1>; - }; - mp_clk: mp { - compatible = "fixed-factor-clock"; - clocks = <&pll1_div2_clk>; - #clock-cells = <0>; - clock-div = <15>; - clock-mult = <1>; - }; - cp_clk: cp { - compatible = "fixed-factor-clock"; - clocks = <&extal_clk>; - #clock-cells = <0>; - clock-div = <2>; - clock-mult = <1>; - }; - - /* Gate clocks */ - mstp0_clks: mstp0_clks@e6150130 { - compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>; - clocks = <&mp_clk>; - #clock-cells = <1>; - clock-indices = ; - clock-output-names = "msiof0"; - }; - mstp1_clks: mstp1_clks@e6150134 { - compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>; - clocks = <&zs_clk>, <&zs_clk>, <&m2_clk>, <&zs_clk>, <&p_clk>, - <&zg_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>, - <&p_clk>, <&rclk_clk>, <&cp_clk>, <&zs_clk>, <&zs_clk>, - <&zs_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7791_CLK_VCP0 R8A7791_CLK_VPC0 R8A7791_CLK_JPU - R8A7791_CLK_SSP1 R8A7791_CLK_TMU1 R8A7791_CLK_3DG - R8A7791_CLK_2DDMAC R8A7791_CLK_FDP1_1 R8A7791_CLK_FDP1_0 - R8A7791_CLK_TMU3 R8A7791_CLK_TMU2 R8A7791_CLK_CMT0 - R8A7791_CLK_TMU0 R8A7791_CLK_VSP1_DU1 R8A7791_CLK_VSP1_DU0 - R8A7791_CLK_VSP1_S - >; - clock-output-names = - "vcp0", "vpc0", "jpu", "ssp1", "tmu1", "3dg", - "2ddmac", "fdp1-1", "fdp1-0", "tmu3", "tmu2", "cmt0", - "tmu0", "vsp1-du1", "vsp1-du0", "vsp1-sy"; - }; - mstp2_clks: mstp2_clks@e6150138 { - compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>; - clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, - <&mp_clk>, <&mp_clk>, <&mp_clk>, - <&zs_clk>, <&zs_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7791_CLK_SCIFA2 R8A7791_CLK_SCIFA1 R8A7791_CLK_SCIFA0 - R8A7791_CLK_MSIOF2 R8A7791_CLK_SCIFB0 R8A7791_CLK_SCIFB1 - R8A7791_CLK_MSIOF1 R8A7791_CLK_SCIFB2 - R8A7791_CLK_SYS_DMAC1 R8A7791_CLK_SYS_DMAC0 - >; - clock-output-names = - "scifa2", "scifa1", "scifa0", "msiof2", "scifb0", - "scifb1", "msiof1", "scifb2", - "sys-dmac1", "sys-dmac0"; - }; - mstp3_clks: mstp3_clks@e615013c { - compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; - clocks = <&cp_clk>, <&sd3_clk>, <&sd2_clk>, <&cpg_clocks R8A7791_CLK_SD0>, - <&mmc0_clk>, <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>, - <&hp_clk>, <&hp_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7791_CLK_TPU0 R8A7791_CLK_SDHI2 R8A7791_CLK_SDHI1 R8A7791_CLK_SDHI0 - R8A7791_CLK_MMCIF0 R8A7791_CLK_IIC0 R8A7791_CLK_PCIEC R8A7791_CLK_IIC1 - R8A7791_CLK_SSUSB R8A7791_CLK_CMT1 - R8A7791_CLK_USBDMAC0 R8A7791_CLK_USBDMAC1 - >; - clock-output-names = - "tpu0", "sdhi2", "sdhi1", "sdhi0", - "mmcif0", "i2c7", "pciec", "i2c8", "ssusb", "cmt1", - "usbdmac0", "usbdmac1"; - }; - mstp4_clks: mstp4_clks@e6150140 { - compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>; - clocks = <&cp_clk>, <&zs_clk>; - #clock-cells = <1>; - clock-indices = ; - clock-output-names = "irqc", "intc-sys"; - }; - mstp5_clks: mstp5_clks@e6150144 { - compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>; - clocks = <&hp_clk>, <&hp_clk>, <&cpg_clocks R8A7791_CLK_ADSP>, - <&extal_clk>, <&p_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7791_CLK_AUDIO_DMAC0 R8A7791_CLK_AUDIO_DMAC1 - R8A7791_CLK_ADSP_MOD R8A7791_CLK_THERMAL - R8A7791_CLK_PWM - >; - clock-output-names = "audmac0", "audmac1", "adsp_mod", - "thermal", "pwm"; - }; - mstp7_clks: mstp7_clks@e615014c { - compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>; - clocks = <&mp_clk>, <&hp_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>, - <&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, - <&zx_clk>, <&zx_clk>, <&zx_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7791_CLK_EHCI R8A7791_CLK_HSUSB R8A7791_CLK_HSCIF2 R8A7791_CLK_SCIF5 - R8A7791_CLK_SCIF4 R8A7791_CLK_HSCIF1 R8A7791_CLK_HSCIF0 - R8A7791_CLK_SCIF3 R8A7791_CLK_SCIF2 R8A7791_CLK_SCIF1 - R8A7791_CLK_SCIF0 R8A7791_CLK_DU1 R8A7791_CLK_DU0 - R8A7791_CLK_LVDS0 - >; - clock-output-names = - "ehci", "hsusb", "hscif2", "scif5", "scif4", "hscif1", "hscif0", - "scif3", "scif2", "scif1", "scif0", "du1", "du0", "lvds0"; - }; - mstp8_clks: mstp8_clks@e6150990 { - compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>; - clocks = <&zx_clk>, <&hp_clk>, <&zg_clk>, <&zg_clk>, - <&zg_clk>, <&hp_clk>, <&p_clk>, <&zs_clk>, - <&zs_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7791_CLK_IPMMU_SGX R8A7791_CLK_MLB - R8A7791_CLK_VIN2 R8A7791_CLK_VIN1 R8A7791_CLK_VIN0 - R8A7791_CLK_ETHERAVB R8A7791_CLK_ETHER - R8A7791_CLK_SATA1 R8A7791_CLK_SATA0 - >; - clock-output-names = - "ipmmu_sgx", "mlb", "vin2", "vin1", "vin0", - "etheravb", "ether", "sata1", "sata0"; - }; - mstp9_clks: mstp9_clks@e6150994 { - compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>; - clocks = <&p_clk>, - <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>, - <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>, - <&p_clk>, <&p_clk>, <&cpg_clocks R8A7791_CLK_QSPI>, <&hp_clk>, - <&cp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>, - <&hp_clk>, <&hp_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7791_CLK_GYROADC - R8A7791_CLK_GPIO7 R8A7791_CLK_GPIO6 R8A7791_CLK_GPIO5 R8A7791_CLK_GPIO4 - R8A7791_CLK_GPIO3 R8A7791_CLK_GPIO2 R8A7791_CLK_GPIO1 R8A7791_CLK_GPIO0 - R8A7791_CLK_RCAN1 R8A7791_CLK_RCAN0 R8A7791_CLK_QSPI_MOD R8A7791_CLK_I2C5 - R8A7791_CLK_IICDVFS R8A7791_CLK_I2C4 R8A7791_CLK_I2C3 R8A7791_CLK_I2C2 - R8A7791_CLK_I2C1 R8A7791_CLK_I2C0 - >; - clock-output-names = - "gyroadc", - "gpio7", "gpio6", "gpio5", "gpio4", "gpio3", "gpio2", "gpio1", "gpio0", - "rcan1", "rcan0", "qspi_mod", "i2c5", "i2c6", "i2c4", "i2c3", "i2c2", - "i2c1", "i2c0"; - }; - mstp10_clks: mstp10_clks@e6150998 { - compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>; - clocks = <&p_clk>, - <&mstp10_clks R8A7791_CLK_SSI_ALL>, <&mstp10_clks R8A7791_CLK_SSI_ALL>, - <&mstp10_clks R8A7791_CLK_SSI_ALL>, <&mstp10_clks R8A7791_CLK_SSI_ALL>, - <&mstp10_clks R8A7791_CLK_SSI_ALL>, <&mstp10_clks R8A7791_CLK_SSI_ALL>, - <&mstp10_clks R8A7791_CLK_SSI_ALL>, <&mstp10_clks R8A7791_CLK_SSI_ALL>, - <&mstp10_clks R8A7791_CLK_SSI_ALL>, <&mstp10_clks R8A7791_CLK_SSI_ALL>, - <&p_clk>, - <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>, - <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>, - <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>, - <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>, - <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>, - <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>, - <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>; - - #clock-cells = <1>; - clock-indices = < - R8A7791_CLK_SSI_ALL - R8A7791_CLK_SSI9 R8A7791_CLK_SSI8 R8A7791_CLK_SSI7 R8A7791_CLK_SSI6 R8A7791_CLK_SSI5 - R8A7791_CLK_SSI4 R8A7791_CLK_SSI3 R8A7791_CLK_SSI2 R8A7791_CLK_SSI1 R8A7791_CLK_SSI0 - R8A7791_CLK_SCU_ALL - R8A7791_CLK_SCU_DVC1 R8A7791_CLK_SCU_DVC0 - R8A7791_CLK_SCU_CTU1_MIX1 R8A7791_CLK_SCU_CTU0_MIX0 - R8A7791_CLK_SCU_SRC9 R8A7791_CLK_SCU_SRC8 R8A7791_CLK_SCU_SRC7 R8A7791_CLK_SCU_SRC6 R8A7791_CLK_SCU_SRC5 - R8A7791_CLK_SCU_SRC4 R8A7791_CLK_SCU_SRC3 R8A7791_CLK_SCU_SRC2 R8A7791_CLK_SCU_SRC1 R8A7791_CLK_SCU_SRC0 - >; - clock-output-names = - "ssi-all", - "ssi9", "ssi8", "ssi7", "ssi6", "ssi5", - "ssi4", "ssi3", "ssi2", "ssi1", "ssi0", - "scu-all", - "scu-dvc1", "scu-dvc0", - "scu-ctu1-mix1", "scu-ctu0-mix0", - "scu-src9", "scu-src8", "scu-src7", "scu-src6", "scu-src5", - "scu-src4", "scu-src3", "scu-src2", "scu-src1", "scu-src0"; - }; - mstp11_clks: mstp11_clks@e615099c { - compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; - reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>; - clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>; - #clock-cells = <1>; - clock-indices = < - R8A7791_CLK_SCIFA3 R8A7791_CLK_SCIFA4 R8A7791_CLK_SCIFA5 - >; - clock-output-names = "scifa3", "scifa4", "scifa5"; - }; }; rst: reset-controller@e6160000 { @@ -1544,7 +1190,7 @@ qspi: spi@e6b10000 { compatible = "renesas,qspi-r8a7791", "renesas,qspi"; reg = <0 0xe6b10000 0 0x2c>; interrupts = ; - clocks = <&mstp9_clks R8A7791_CLK_QSPI_MOD>; + clocks = <&cpg CPG_MOD 917>; dmas = <&dmac0 0x17>, <&dmac0 0x18>, <&dmac1 0x17>, <&dmac1 0x18>; dma-names = "tx", "rx", "tx", "rx"; @@ -1560,7 +1206,7 @@ msiof0: spi@e6e20000 { "renesas,rcar-gen2-msiof"; reg = <0 0xe6e20000 0 0x0064>; interrupts = ; - clocks = <&mstp0_clks R8A7791_CLK_MSIOF0>; + clocks = <&cpg CPG_MOD 000>; dmas = <&dmac0 0x51>, <&dmac0 0x52>, <&dmac1 0x51>, <&dmac1 0x52>; dma-names = "tx", "rx", "tx", "rx"; @@ -1575,7 +1221,7 @@ msiof1: spi@e6e10000 { "renesas,rcar-gen2-msiof"; reg = <0 0xe6e10000 0 0x0064>; interrupts = ; - clocks = <&mstp2_clks R8A7791_CLK_MSIOF1>; + clocks = <&cpg CPG_MOD 208>; dmas = <&dmac0 0x55>, <&dmac0 0x56>, <&dmac1 0x55>, <&dmac1 0x56>; dma-names = "tx", "rx", "tx", "rx"; @@ -1590,7 +1236,7 @@ msiof2: spi@e6e00000 { "renesas,rcar-gen2-msiof"; reg = <0 0xe6e00000 0 0x0064>; interrupts = ; - clocks = <&mstp2_clks R8A7791_CLK_MSIOF2>; + clocks = <&cpg CPG_MOD 205>; dmas = <&dmac0 0x41>, <&dmac0 0x42>, <&dmac1 0x41>, <&dmac1 0x42>; dma-names = "tx", "rx", "tx", "rx"; @@ -1604,7 +1250,7 @@ xhci: usb@ee000000 { compatible = "renesas,xhci-r8a7791", "renesas,rcar-gen2-xhci"; reg = <0 0xee000000 0 0xc00>; interrupts = ; - clocks = <&mstp3_clks R8A7791_CLK_SSUSB>; + clocks = <&cpg CPG_MOD 328>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; phys = <&usb2 1>; phy-names = "usb"; @@ -1617,7 +1263,7 @@ pci0: pci@ee090000 { reg = <0 0xee090000 0 0xc00>, <0 0xee080000 0 0x1100>; interrupts = ; - clocks = <&mstp7_clks R8A7791_CLK_EHCI>; + clocks = <&cpg CPG_MOD 703>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; status = "disabled"; @@ -1650,7 +1296,7 @@ pci1: pci@ee0d0000 { reg = <0 0xee0d0000 0 0xc00>, <0 0xee0c0000 0 0x1100>; interrupts = ; - clocks = <&mstp7_clks R8A7791_CLK_EHCI>; + clocks = <&cpg CPG_MOD 703>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; status = "disabled"; @@ -1697,7 +1343,7 @@ pciec: pcie@fe000000 { #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 0>; interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&mstp3_clks R8A7791_CLK_PCIEC>, <&pcie_bus_clk>; + clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; clock-names = "pcie", "pcie_bus"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; status = "disabled"; @@ -1778,21 +1424,22 @@ rcar_sound: sound@ec500000 { <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/ reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; - clocks = <&mstp10_clks R8A7791_CLK_SSI_ALL>, - <&mstp10_clks R8A7791_CLK_SSI9>, <&mstp10_clks R8A7791_CLK_SSI8>, - <&mstp10_clks R8A7791_CLK_SSI7>, <&mstp10_clks R8A7791_CLK_SSI6>, - <&mstp10_clks R8A7791_CLK_SSI5>, <&mstp10_clks R8A7791_CLK_SSI4>, - <&mstp10_clks R8A7791_CLK_SSI3>, <&mstp10_clks R8A7791_CLK_SSI2>, - <&mstp10_clks R8A7791_CLK_SSI1>, <&mstp10_clks R8A7791_CLK_SSI0>, - <&mstp10_clks R8A7791_CLK_SCU_SRC9>, <&mstp10_clks R8A7791_CLK_SCU_SRC8>, - <&mstp10_clks R8A7791_CLK_SCU_SRC7>, <&mstp10_clks R8A7791_CLK_SCU_SRC6>, - <&mstp10_clks R8A7791_CLK_SCU_SRC5>, <&mstp10_clks R8A7791_CLK_SCU_SRC4>, - <&mstp10_clks R8A7791_CLK_SCU_SRC3>, <&mstp10_clks R8A7791_CLK_SCU_SRC2>, - <&mstp10_clks R8A7791_CLK_SCU_SRC1>, <&mstp10_clks R8A7791_CLK_SCU_SRC0>, - <&mstp10_clks R8A7791_CLK_SCU_CTU0_MIX0>, <&mstp10_clks R8A7791_CLK_SCU_CTU1_MIX1>, - <&mstp10_clks R8A7791_CLK_SCU_CTU0_MIX0>, <&mstp10_clks R8A7791_CLK_SCU_CTU1_MIX1>, - <&mstp10_clks R8A7791_CLK_SCU_DVC0>, <&mstp10_clks R8A7791_CLK_SCU_DVC1>, - <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, <&m2_clk>; + clocks = <&cpg CPG_MOD 1005>, + <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, + <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, + <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, + <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, + <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, + <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, + <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, + <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, + <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, + <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, + <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>, + <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>, + <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, + <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, + <&cpg CPG_CORE R8A7791_CLK_M2>; clock-names = "ssi-all", "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5", "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0", From 580aa7cb473880213a55afdb5c34ae844fda07fb Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 23 Aug 2017 13:59:26 +0200 Subject: [PATCH 19/48] ARM: dts: r8a7791: Stop grouping clocks under a "clocks" subnode The current practice is to not group clocks under a "clocks" subnode, but just put them together with the other on-SoC devices. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7791.dtsi | 125 ++++++++++++++++----------------- 1 file changed, 60 insertions(+), 65 deletions(-) diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi index 5fca397b722b..e984b106dd1a 100644 --- a/arch/arm/boot/dts/r8a7791.dtsi +++ b/arch/arm/boot/dts/r8a7791.dtsi @@ -1097,77 +1097,72 @@ jpu: jpeg-codec@fe980000 { power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; }; - clocks { - #address-cells = <2>; - #size-cells = <2>; - ranges; + /* External root clock */ + extal_clk: extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; - /* External root clock */ - extal_clk: extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overriden by the board. */ - clock-frequency = <0>; - }; + /* + * The external audio clocks are configured as 0 Hz fixed frequency + * clocks by default. + * Boards that provide audio clocks should override them. + */ + audio_clk_a: audio_clk_a { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + audio_clk_b: audio_clk_b { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + audio_clk_c: audio_clk_c { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; - /* - * The external audio clocks are configured as 0 Hz fixed frequency clocks by - * default. Boards that provide audio clocks should override them. - */ - audio_clk_a: audio_clk_a { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - audio_clk_b: audio_clk_b { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; - audio_clk_c: audio_clk_c { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; + /* External PCIe clock - can be overridden by the board */ + pcie_bus_clk: pcie_bus { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; - /* External PCIe clock - can be overridden by the board */ - pcie_bus_clk: pcie_bus { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - }; + /* External SCIF clock */ + scif_clk: scif { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; - /* External SCIF clock */ - scif_clk: scif { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; + /* External USB clock - can be overridden by the board */ + usb_extal_clk: usb_extal { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <48000000>; + }; - /* External USB clock - can be overridden by the board */ - usb_extal_clk: usb_extal { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <48000000>; - }; + /* External CAN clock */ + can_clk: can { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; - /* External CAN clock */ - can_clk: can { - compatible = "fixed-clock"; - #clock-cells = <0>; - /* This value must be overridden by the board. */ - clock-frequency = <0>; - }; - - cpg: clock-controller@e6150000 { - compatible = "renesas,r8a7791-cpg-mssr"; - reg = <0 0xe6150000 0 0x1000>; - clocks = <&extal_clk>, <&usb_extal_clk>; - clock-names = "extal", "usb_extal"; - #clock-cells = <2>; - #power-domain-cells = <0>; - }; + cpg: clock-controller@e6150000 { + compatible = "renesas,r8a7791-cpg-mssr"; + reg = <0 0xe6150000 0 0x1000>; + clocks = <&extal_clk>, <&usb_extal_clk>; + clock-names = "extal", "usb_extal"; + #clock-cells = <2>; + #power-domain-cells = <0>; }; rst: reset-controller@e6160000 { From f7c68cdfebf6ad6b3c4d6b6c8966414219d035e3 Mon Sep 17 00:00:00 2001 From: Jacopo Mondi Date: Thu, 24 Aug 2017 10:48:40 +0200 Subject: [PATCH 20/48] ARM: dts: gr-peach: Remove empty line Remove an empty line in gr-peach device tree source file. Signed-off-by: Jacopo Mondi Acked-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r7s72100-gr-peach.dts | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm/boot/dts/r7s72100-gr-peach.dts b/arch/arm/boot/dts/r7s72100-gr-peach.dts index a1b2aef984f6..1c40a1afbd8e 100644 --- a/arch/arm/boot/dts/r7s72100-gr-peach.dts +++ b/arch/arm/boot/dts/r7s72100-gr-peach.dts @@ -28,7 +28,6 @@ chosen { memory@20000000 { device_type = "memory"; reg = <0x20000000 0x00a00000>; - }; lbsc { From 2f8be2d1dadb2b73a1c1ce244c88c509791f5cf2 Mon Sep 17 00:00:00 2001 From: Jacopo Mondi Date: Thu, 24 Aug 2017 10:48:41 +0200 Subject: [PATCH 21/48] ARM: dts: gr-peach: Add SCIF2 pin group Add pin configuration subnode for SCIF2 serial debug interface. Signed-off-by: Jacopo Mondi Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r7s72100-gr-peach.dts | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm/boot/dts/r7s72100-gr-peach.dts b/arch/arm/boot/dts/r7s72100-gr-peach.dts index 1c40a1afbd8e..bcfa6445bbaa 100644 --- a/arch/arm/boot/dts/r7s72100-gr-peach.dts +++ b/arch/arm/boot/dts/r7s72100-gr-peach.dts @@ -11,6 +11,7 @@ /dts-v1/; #include "r7s72100.dtsi" +#include / { model = "GR-Peach"; @@ -52,6 +53,13 @@ rootfs@600000 { }; }; +&pinctrl { + scif2_pins: serial2 { + /* P6_2 as RxD2; P6_3 as TxD2 */ + pinmux = , ; + }; +}; + &extal_clk { clock-frequency = <13333000>; }; @@ -61,5 +69,8 @@ &usb_x1_clk { }; &scif2 { + pinctrl-names = "default"; + pinctrl-0 = <&scif2_pins>; + status = "okay"; }; From cfce5ac1aaf08fc0920d6572779360f80e8f3489 Mon Sep 17 00:00:00 2001 From: Jacopo Mondi Date: Thu, 24 Aug 2017 10:48:43 +0200 Subject: [PATCH 22/48] ARM: dts: gr-peach: Add user led device nodes Add device nodes for user leds on gr-peach board. Signed-off-by: Jacopo Mondi Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r7s72100-gr-peach.dts | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/r7s72100-gr-peach.dts b/arch/arm/boot/dts/r7s72100-gr-peach.dts index bcfa6445bbaa..13d745bb56a5 100644 --- a/arch/arm/boot/dts/r7s72100-gr-peach.dts +++ b/arch/arm/boot/dts/r7s72100-gr-peach.dts @@ -11,6 +11,7 @@ /dts-v1/; #include "r7s72100.dtsi" +#include #include / { @@ -51,6 +52,15 @@ rootfs@600000 { reg = <0x00600000 0x00200000>; }; }; + +leds { + status = "okay"; + compatible = "gpio-leds"; + + led1 { + gpios = <&port6 12 GPIO_ACTIVE_HIGH>; + }; + }; }; &pinctrl { From 372b01369fed699c417789ad94344847e09b7a43 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Fri, 25 Aug 2017 09:31:53 +0100 Subject: [PATCH 23/48] ARM: dts: r8a7745: Add Ethernet AVB support Add Ethernet AVB support for r8a7745 SoC. Signed-off-by: Biju Das Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7745.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi index 7fd2967b1f42..6e82991b7997 100644 --- a/arch/arm/boot/dts/r8a7745.dtsi +++ b/arch/arm/boot/dts/r8a7745.dtsi @@ -623,6 +623,19 @@ ether: ethernet@ee700000 { status = "disabled"; }; + avb: ethernet@e6800000 { + compatible = "renesas,etheravb-r8a7745", + "renesas,etheravb-rcar-gen2"; + reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; + interrupts = ; + clocks = <&cpg CPG_MOD 812>; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 812>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + i2c0: i2c@e6508000 { #address-cells = <1>; #size-cells = <0>; From f9c1e87e77ca1ef1c4de2d419b0dcb42e4a47043 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Tue, 29 Aug 2017 10:56:22 +0100 Subject: [PATCH 24/48] ARM: dts: iwg20d-q7: Add chosen node Signed-off-by: Biju Das Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7743-iwg20d-q7.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts b/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts index 4ff27d23ecf0..e30c58625e65 100644 --- a/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts +++ b/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts @@ -20,6 +20,11 @@ aliases { ethernet0 = &avb; }; + chosen { + bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp"; + stdout-path = "serial0:115200n8"; + }; + vcc_sdhi1: regulator-vcc-sdhi1 { compatible = "regulator-fixed"; From e0e63658c2f291e0672fdf96df1f9f2963a6a9f6 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Tue, 29 Aug 2017 10:56:23 +0100 Subject: [PATCH 25/48] ARM: dts: iwg20d-q7: Add RTC support Define the iWave RainboW-G20D-Qseven board dependent part of the RTC device node. Signed-off-by: Biju Das Signed-off-by: Chris Paterson Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7743-iwg20d-q7.dts | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts b/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts index e30c58625e65..2b58b53aa171 100644 --- a/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts +++ b/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts @@ -50,6 +50,11 @@ vccq_sdhi1: regulator-vccq-sdhi1 { }; &pfc { + i2c2_pins: i2c2 { + groups = "i2c2"; + function = "i2c2"; + }; + scif0_pins: scif0 { groups = "scif0_data_d"; function = "scif0"; @@ -107,3 +112,16 @@ &sdhi1 { sd-uhs-sdr50; status = "okay"; }; + +&i2c2 { + pinctrl-0 = <&i2c2_pins>; + pinctrl-names = "default"; + + status = "okay"; + clock-frequency = <400000>; + + rtc@68 { + compatible = "ti,bq32000"; + reg = <0x68>; + }; +}; From 67dbb081815e013e1e7911305b43b44537a78ed2 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Thu, 17 Aug 2017 16:09:09 +0100 Subject: [PATCH 26/48] ARM: dts: iwg22d-sodimm: Add pinctl support for scif4 Adding pinctrl support for scif4 interface. Signed-off-by: Biju Das Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts b/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts index cbc19feb1565..442a5cbb0838 100644 --- a/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts +++ b/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts @@ -24,6 +24,16 @@ chosen { }; }; +&pfc { + scif4_pins: scif4 { + groups = "scif4_data_b"; + function = "scif4"; + }; +}; + &scif4 { + pinctrl-0 = <&scif4_pins>; + pinctrl-names = "default"; + status = "okay"; }; From d6ee805325b1d082fa33be3024163e5f7931ed54 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Wed, 30 Aug 2017 16:17:14 +0100 Subject: [PATCH 27/48] ARM: dts: iwg22d-sodimm: Add Ethernet AVB support Define the iWave RainboW-G22D board dependent part of the Ethernet AVB device node. On some older versions of the platform (before R4.0) the phy address may be 1 or 3. The address is fixed to 3 for R4.0 onwards (which will be the first mainstream release), hence using 3 in the dts. Signed-off-by: Biju Das Signed-off-by: Chris Paterson Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts | 26 +++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts b/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts index 442a5cbb0838..aac84c67a31d 100644 --- a/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts +++ b/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts @@ -17,9 +17,11 @@ / { aliases { serial0 = &scif4; + ethernet0 = &avb; }; chosen { + bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp"; stdout-path = "serial0:115200n8"; }; }; @@ -29,6 +31,11 @@ scif4_pins: scif4 { groups = "scif4_data_b"; function = "scif4"; }; + + avb_pins: avb { + groups = "avb_mdio", "avb_gmii"; + function = "avb"; + }; }; &scif4 { @@ -37,3 +44,22 @@ &scif4 { status = "okay"; }; + +&avb { + pinctrl-0 = <&avb_pins>; + pinctrl-names = "default"; + + phy-handle = <&phy3>; + phy-mode = "gmii"; + renesas,no-ether-link; + status = "okay"; + + phy3: ethernet-phy@3 { + /* + * On some older versions of the platform (before R4.0) the phy address + * may be 1 or 3. The address is fixed to 3 for R4.0 onwards. + */ + reg = <3>; + micrel,led-mode = <1>; + }; +}; From 46d9cf5202fd8cd266748779c1a941aaeff0dcad Mon Sep 17 00:00:00 2001 From: Biju Das Date: Wed, 30 Aug 2017 14:41:09 +0100 Subject: [PATCH 28/48] ARM: dts: r8a7743: Add internal PCI bridge nodes Add device nodes for the r8a7743 internal PCI bridge devices. Signed-off-by: Biju Das Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7743.dtsi | 46 ++++++++++++++++++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi index 6dd9b0b3d818..3f1faad7c24f 100644 --- a/arch/arm/boot/dts/r8a7743.dtsi +++ b/arch/arm/boot/dts/r8a7743.dtsi @@ -821,6 +821,52 @@ sdhi2: sd@ee160000 { resets = <&cpg 311>; status = "disabled"; }; + + pci0: pci@ee090000 { + compatible = "renesas,pci-r8a7743", + "renesas,pci-rcar-gen2"; + device_type = "pci"; + reg = <0 0xee090000 0 0xc00>, + <0 0xee080000 0 0x1100>; + interrupts = ; + clocks = <&cpg CPG_MOD 703>; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 703>; + status = "disabled"; + + bus-range = <0 0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>; + interrupt-map-mask = <0xff00 0 0 0x7>; + interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH + 0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH + 0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; + }; + + pci1: pci@ee0d0000 { + compatible = "renesas,pci-r8a7743", + "renesas,pci-rcar-gen2"; + device_type = "pci"; + reg = <0 0xee0d0000 0 0xc00>, + <0 0xee0c0000 0 0x1100>; + interrupts = ; + clocks = <&cpg CPG_MOD 703>; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 703>; + status = "disabled"; + + bus-range = <1 1>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>; + interrupt-map-mask = <0xff00 0 0 0x7>; + interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH + 0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH + 0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; + }; }; /* External root clock */ From 9412c391af67fc8aa4e2d8975ba6143cd5289296 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Wed, 30 Aug 2017 14:41:10 +0100 Subject: [PATCH 29/48] ARM: dts: r8a7743: Add USB PHY DT support Define the r8a7743 generic part of the USB PHY device node. Signed-off-by: Biju Das Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7743.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi index 3f1faad7c24f..a81d70e713ea 100644 --- a/arch/arm/boot/dts/r8a7743.dtsi +++ b/arch/arm/boot/dts/r8a7743.dtsi @@ -822,6 +822,28 @@ sdhi2: sd@ee160000 { status = "disabled"; }; + usbphy: usb-phy@e6590100 { + compatible = "renesas,usb-phy-r8a7743", + "renesas,rcar-gen2-usb-phy"; + reg = <0 0xe6590100 0 0x100>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cpg CPG_MOD 704>; + clock-names = "usbhs"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 704>; + status = "disabled"; + + usb0: usb-channel@0 { + reg = <0>; + #phy-cells = <1>; + }; + usb2: usb-channel@2 { + reg = <2>; + #phy-cells = <1>; + }; + }; + pci0: pci@ee090000 { compatible = "renesas,pci-r8a7743", "renesas,pci-rcar-gen2"; From 96963454655c10663f1bc2eea57ac734cab171a7 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Wed, 30 Aug 2017 14:41:11 +0100 Subject: [PATCH 30/48] ARM: dts: r8a7743: Link PCI USB devices to USB PHY Describe the PCI USB devices that are behind the PCI bridges, adding necessary links to the USB PHY device. Signed-off-by: Biju Das Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7743.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi index a81d70e713ea..665a5152951f 100644 --- a/arch/arm/boot/dts/r8a7743.dtsi +++ b/arch/arm/boot/dts/r8a7743.dtsi @@ -865,6 +865,18 @@ pci0: pci@ee090000 { interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; + + usb@1,0 { + reg = <0x800 0 0 0 0>; + phys = <&usb0 0>; + phy-names = "usb"; + }; + + usb@2,0 { + reg = <0x1000 0 0 0 0>; + phys = <&usb0 0>; + phy-names = "usb"; + }; }; pci1: pci@ee0d0000 { @@ -888,6 +900,18 @@ pci1: pci@ee0d0000 { interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; + + usb@1,0 { + reg = <0x10800 0 0 0 0>; + phys = <&usb2 0>; + phy-names = "usb"; + }; + + usb@2,0 { + reg = <0x11000 0 0 0 0>; + phys = <&usb2 0>; + phy-names = "usb"; + }; }; }; From 35a8eeeac89c56435277fa76f8d557bf00530320 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Wed, 30 Aug 2017 14:41:12 +0100 Subject: [PATCH 31/48] ARM: dts: iwg20d-q7: Enable internal PCI Enable internal AHB-PCI bridges for the USB EHCI/OHCI controllers attached to them. Signed-off-by: Biju Das Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7743-iwg20d-q7.dts | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts b/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts index 2b58b53aa171..63166f9bdb65 100644 --- a/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts +++ b/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts @@ -76,6 +76,16 @@ sdhi1_pins_uhs: sd1_uhs { function = "sdhi1"; power-source = <1800>; }; + + usb0_pins: usb0 { + groups = "usb0"; + function = "usb0"; + }; + + usb1_pins: usb1 { + groups = "usb1"; + function = "usb1"; + }; }; &scif0 { @@ -125,3 +135,15 @@ rtc@68 { reg = <0x68>; }; }; + +&pci0 { + status = "okay"; + pinctrl-0 = <&usb0_pins>; + pinctrl-names = "default"; +}; + +&pci1 { + status = "okay"; + pinctrl-0 = <&usb1_pins>; + pinctrl-names = "default"; +}; From 51be0086e6d2ebb3f0ddbeedab8d7c4232c1c5f6 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Wed, 30 Aug 2017 14:41:13 +0100 Subject: [PATCH 32/48] ARM: dts: iwg20d-q7: Enable USB PHY Signed-off-by: Biju Das Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7743-iwg20d-q7.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts b/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts index 63166f9bdb65..0136864bc595 100644 --- a/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts +++ b/arch/arm/boot/dts/r8a7743-iwg20d-q7.dts @@ -147,3 +147,7 @@ &pci1 { pinctrl-0 = <&usb1_pins>; pinctrl-names = "default"; }; + +&usbphy { + status = "okay"; +}; From a2f74d0e655eac78dbbd4ade88ee08b1f8ec7ec1 Mon Sep 17 00:00:00 2001 From: Wolfram Sang Date: Tue, 5 Sep 2017 19:26:31 +0200 Subject: [PATCH 33/48] ARM: dts: alt: use correct logic for SD WP pins The WP pins are ACTIVE_HIGH, fix it in the DTS. Fixes: 2b41091b896b ("ARM: dts: alt: add SDHI0 and 1 support") Signed-off-by: Wolfram Sang Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7794-alt.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/r8a7794-alt.dts b/arch/arm/boot/dts/r8a7794-alt.dts index e45f92b5eb11..bd98790d964e 100644 --- a/arch/arm/boot/dts/r8a7794-alt.dts +++ b/arch/arm/boot/dts/r8a7794-alt.dts @@ -304,7 +304,7 @@ &sdhi0 { vmmc-supply = <&vcc_sdhi0>; vqmmc-supply = <&vccq_sdhi0>; cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio6 7 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>; sd-uhs-sdr50; sd-uhs-sdr104; status = "okay"; @@ -318,7 +318,7 @@ &sdhi1 { vmmc-supply = <&vcc_sdhi1>; vqmmc-supply = <&vccq_sdhi1>; cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>; - wp-gpios = <&gpio6 15 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>; sd-uhs-sdr50; status = "okay"; }; From f523405f2a22cc0c30701ea0cb3671dc0abbcda1 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Wed, 6 Sep 2017 14:52:06 +0100 Subject: [PATCH 34/48] ARM: dts: r8a7743: Add IIC cores to dtsi Signed-off-by: Biju Das Signed-off-by: Chris Paterson Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7743.dtsi | 55 ++++++++++++++++++++++++++++++++++ 1 file changed, 55 insertions(+) diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi index 665a5152951f..266c5eca9f74 100644 --- a/arch/arm/boot/dts/r8a7743.dtsi +++ b/arch/arm/boot/dts/r8a7743.dtsi @@ -25,6 +25,9 @@ aliases { i2c3 = &i2c3; i2c4 = &i2c4; i2c5 = &i2c5; + i2c6 = &iic0; + i2c7 = &iic1; + i2c8 = &iic3; }; cpus { @@ -436,6 +439,58 @@ i2c5: i2c@e6528000 { status = "disabled"; }; + iic0: i2c@e6500000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,iic-r8a7743", + "renesas,rcar-gen2-iic", + "renesas,rmobile-iic"; + reg = <0 0xe6500000 0 0x425>; + interrupts = ; + clocks = <&cpg CPG_MOD 318>; + dmas = <&dmac0 0x61>, <&dmac0 0x62>, + <&dmac1 0x61>, <&dmac1 0x62>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 318>; + status = "disabled"; + }; + + iic1: i2c@e6510000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,iic-r8a7743", + "renesas,rcar-gen2-iic", + "renesas,rmobile-iic"; + reg = <0 0xe6510000 0 0x425>; + interrupts = ; + clocks = <&cpg CPG_MOD 323>; + dmas = <&dmac0 0x65>, <&dmac0 0x66>, + <&dmac1 0x65>, <&dmac1 0x66>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 323>; + status = "disabled"; + }; + + iic3: i2c@e60b0000 { + /* doesn't need pinmux */ + #address-cells = <1>; + #size-cells = <0>; + compatible = "renesas,iic-r8a7743", + "renesas,rcar-gen2-iic", + "renesas,rmobile-iic"; + reg = <0 0xe60b0000 0 0x425>; + interrupts = ; + clocks = <&cpg CPG_MOD 926>; + dmas = <&dmac0 0x77>, <&dmac0 0x78>, + <&dmac1 0x77>, <&dmac1 0x78>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + resets = <&cpg 926>; + status = "disabled"; + }; + scifa0: serial@e6c40000 { compatible = "renesas,scifa-r8a7743", "renesas,rcar-gen2-scifa", "renesas,scifa"; From 34fbd2b12761d11166414ca766637c7e6bbb39d7 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 11 Sep 2017 15:09:55 +0200 Subject: [PATCH 35/48] ARM: dts: r8a7790: Add reset control properties Add properties to describe the reset topology for on-SoC devices: - Add the "#reset-cells" property to the CPG/MSSR device node, - Add resets and reset-names properties to the various device nodes. This allows to reset SoC devices using the Reset Controller API. Note that resets usually match the corresponding module clocks. Exceptions are: - The audio module has resets for the Serial Sound Interfaces only, - The display module has only a single reset for all DU channels, but adding reset properties for the display is postponed. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7790.dtsi | 76 ++++++++++++++++++++++++++++++++++ 1 file changed, 76 insertions(+) diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index 70040c6c4cea..081cf5cdb13b 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -188,6 +188,7 @@ gic: interrupt-controller@f1001000 { clocks = <&cpg CPG_MOD 408>; clock-names = "clk"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 408>; }; gpio0: gpio@e6050000 { @@ -201,6 +202,7 @@ gpio0: gpio@e6050000 { interrupt-controller; clocks = <&cpg CPG_MOD 912>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 912>; }; gpio1: gpio@e6051000 { @@ -214,6 +216,7 @@ gpio1: gpio@e6051000 { interrupt-controller; clocks = <&cpg CPG_MOD 911>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 911>; }; gpio2: gpio@e6052000 { @@ -227,6 +230,7 @@ gpio2: gpio@e6052000 { interrupt-controller; clocks = <&cpg CPG_MOD 910>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 910>; }; gpio3: gpio@e6053000 { @@ -240,6 +244,7 @@ gpio3: gpio@e6053000 { interrupt-controller; clocks = <&cpg CPG_MOD 909>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 909>; }; gpio4: gpio@e6054000 { @@ -253,6 +258,7 @@ gpio4: gpio@e6054000 { interrupt-controller; clocks = <&cpg CPG_MOD 908>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 908>; }; gpio5: gpio@e6055000 { @@ -266,6 +272,7 @@ gpio5: gpio@e6055000 { interrupt-controller; clocks = <&cpg CPG_MOD 907>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 907>; }; thermal: thermal@e61f0000 { @@ -276,6 +283,7 @@ thermal: thermal@e61f0000 { interrupts = ; clocks = <&cpg CPG_MOD 522>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 522>; #thermal-sensor-cells = <0>; }; @@ -295,6 +303,7 @@ cmt0: timer@ffca0000 { clocks = <&cpg CPG_MOD 124>; clock-names = "fck"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 124>; renesas,channels-mask = <0x60>; @@ -315,6 +324,7 @@ cmt1: timer@e6130000 { clocks = <&cpg CPG_MOD 329>; clock-names = "fck"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 329>; renesas,channels-mask = <0xff>; @@ -332,6 +342,7 @@ irqc0: interrupt-controller@e61c0000 { ; clocks = <&cpg CPG_MOD 407>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 407>; }; dmac0: dma-controller@e6700000 { @@ -361,6 +372,7 @@ GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH clocks = <&cpg CPG_MOD 219>; clock-names = "fck"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 219>; #dma-cells = <1>; dma-channels = <15>; }; @@ -392,6 +404,7 @@ GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH clocks = <&cpg CPG_MOD 218>; clock-names = "fck"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 218>; #dma-cells = <1>; dma-channels = <15>; }; @@ -421,6 +434,7 @@ GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH clocks = <&cpg CPG_MOD 502>; clock-names = "fck"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 502>; #dma-cells = <1>; dma-channels = <13>; }; @@ -450,6 +464,7 @@ GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH clocks = <&cpg CPG_MOD 501>; clock-names = "fck"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 501>; #dma-cells = <1>; dma-channels = <13>; }; @@ -462,6 +477,7 @@ usb_dmac0: dma-controller@e65a0000 { interrupt-names = "ch0", "ch1"; clocks = <&cpg CPG_MOD 330>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 330>; #dma-cells = <1>; dma-channels = <2>; }; @@ -474,6 +490,7 @@ usb_dmac1: dma-controller@e65b0000 { interrupt-names = "ch0", "ch1"; clocks = <&cpg CPG_MOD 331>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 331>; #dma-cells = <1>; dma-channels = <2>; }; @@ -486,6 +503,7 @@ i2c0: i2c@e6508000 { interrupts = ; clocks = <&cpg CPG_MOD 931>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 931>; i2c-scl-internal-delay-ns = <110>; status = "disabled"; }; @@ -498,6 +516,7 @@ i2c1: i2c@e6518000 { interrupts = ; clocks = <&cpg CPG_MOD 930>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 930>; i2c-scl-internal-delay-ns = <6>; status = "disabled"; }; @@ -510,6 +529,7 @@ i2c2: i2c@e6530000 { interrupts = ; clocks = <&cpg CPG_MOD 929>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 929>; i2c-scl-internal-delay-ns = <6>; status = "disabled"; }; @@ -522,6 +542,7 @@ i2c3: i2c@e6540000 { interrupts = ; clocks = <&cpg CPG_MOD 928>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 928>; i2c-scl-internal-delay-ns = <110>; status = "disabled"; }; @@ -538,6 +559,7 @@ iic0: i2c@e6500000 { <&dmac1 0x61>, <&dmac1 0x62>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 318>; status = "disabled"; }; @@ -553,6 +575,7 @@ iic1: i2c@e6510000 { <&dmac1 0x65>, <&dmac1 0x66>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 323>; status = "disabled"; }; @@ -568,6 +591,7 @@ iic2: i2c@e6520000 { <&dmac1 0x69>, <&dmac1 0x6a>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 300>; status = "disabled"; }; @@ -583,6 +607,7 @@ iic3: i2c@e60b0000 { <&dmac1 0x77>, <&dmac1 0x78>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 926>; status = "disabled"; }; @@ -595,6 +620,7 @@ mmcif0: mmc@ee200000 { <&dmac1 0xd1>, <&dmac1 0xd2>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 315>; reg-io-width = <4>; status = "disabled"; max-frequency = <97500000>; @@ -609,6 +635,7 @@ mmcif1: mmc@ee220000 { <&dmac1 0xe1>, <&dmac1 0xe2>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 305>; reg-io-width = <4>; status = "disabled"; max-frequency = <97500000>; @@ -629,6 +656,7 @@ sdhi0: sd@ee100000 { dma-names = "tx", "rx", "tx", "rx"; max-frequency = <195000000>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 314>; status = "disabled"; }; @@ -642,6 +670,7 @@ sdhi1: sd@ee120000 { dma-names = "tx", "rx", "tx", "rx"; max-frequency = <195000000>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 313>; status = "disabled"; }; @@ -655,6 +684,7 @@ sdhi2: sd@ee140000 { dma-names = "tx", "rx", "tx", "rx"; max-frequency = <97500000>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 312>; status = "disabled"; }; @@ -668,6 +698,7 @@ sdhi3: sd@ee160000 { dma-names = "tx", "rx", "tx", "rx"; max-frequency = <97500000>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 311>; status = "disabled"; }; @@ -682,6 +713,7 @@ scifa0: serial@e6c40000 { <&dmac1 0x21>, <&dmac1 0x22>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 204>; status = "disabled"; }; @@ -696,6 +728,7 @@ scifa1: serial@e6c50000 { <&dmac1 0x25>, <&dmac1 0x26>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 203>; status = "disabled"; }; @@ -710,6 +743,7 @@ scifa2: serial@e6c60000 { <&dmac1 0x27>, <&dmac1 0x28>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 202>; status = "disabled"; }; @@ -724,6 +758,7 @@ scifb0: serial@e6c20000 { <&dmac1 0x3d>, <&dmac1 0x3e>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 206>; status = "disabled"; }; @@ -738,6 +773,7 @@ scifb1: serial@e6c30000 { <&dmac1 0x19>, <&dmac1 0x1a>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 207>; status = "disabled"; }; @@ -752,6 +788,7 @@ scifb2: serial@e6ce0000 { <&dmac1 0x1d>, <&dmac1 0x1e>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 216>; status = "disabled"; }; @@ -767,6 +804,7 @@ scif0: serial@e6e60000 { <&dmac1 0x29>, <&dmac1 0x2a>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 721>; status = "disabled"; }; @@ -782,6 +820,7 @@ scif1: serial@e6e68000 { <&dmac1 0x2d>, <&dmac1 0x2e>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 720>; status = "disabled"; }; @@ -797,6 +836,7 @@ scif2: serial@e6e56000 { <&dmac1 0x2b>, <&dmac1 0x2c>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 310>; status = "disabled"; }; @@ -812,6 +852,7 @@ hscif0: serial@e62c0000 { <&dmac1 0x39>, <&dmac1 0x3a>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 717>; status = "disabled"; }; @@ -827,6 +868,7 @@ hscif1: serial@e62c8000 { <&dmac1 0x4d>, <&dmac1 0x4e>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 716>; status = "disabled"; }; @@ -854,6 +896,7 @@ ether: ethernet@ee700000 { interrupts = ; clocks = <&cpg CPG_MOD 813>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 813>; phy-mode = "rmii"; #address-cells = <1>; #size-cells = <0>; @@ -867,6 +910,7 @@ avb: ethernet@e6800000 { interrupts = ; clocks = <&cpg CPG_MOD 812>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 812>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -878,6 +922,7 @@ sata0: sata@ee300000 { interrupts = ; clocks = <&cpg CPG_MOD 815>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 815>; status = "disabled"; }; @@ -887,6 +932,7 @@ sata1: sata@ee500000 { interrupts = ; clocks = <&cpg CPG_MOD 814>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 814>; status = "disabled"; }; @@ -899,6 +945,7 @@ hsusb: usb@e6590000 { <&usb_dmac1 0>, <&usb_dmac1 1>; dma-names = "ch0", "ch1", "ch2", "ch3"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 704>; renesas,buswait = <4>; phys = <&usb0 1>; phy-names = "usb"; @@ -914,6 +961,7 @@ usbphy: usb-phy@e6590100 { clocks = <&cpg CPG_MOD 704>; clock-names = "usbhs"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 704>; status = "disabled"; usb0: usb-channel@0 { @@ -932,6 +980,7 @@ vin0: video@e6ef0000 { interrupts = ; clocks = <&cpg CPG_MOD 811>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 811>; status = "disabled"; }; @@ -941,6 +990,7 @@ vin1: video@e6ef1000 { interrupts = ; clocks = <&cpg CPG_MOD 810>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 810>; status = "disabled"; }; @@ -950,6 +1000,7 @@ vin2: video@e6ef2000 { interrupts = ; clocks = <&cpg CPG_MOD 809>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 809>; status = "disabled"; }; @@ -959,6 +1010,7 @@ vin3: video@e6ef3000 { interrupts = ; clocks = <&cpg CPG_MOD 808>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 808>; status = "disabled"; }; @@ -968,6 +1020,7 @@ vsp1@fe920000 { interrupts = ; clocks = <&cpg CPG_MOD 130>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 130>; }; vsp1@fe928000 { @@ -976,6 +1029,7 @@ vsp1@fe928000 { interrupts = ; clocks = <&cpg CPG_MOD 131>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 131>; }; vsp1@fe930000 { @@ -984,6 +1038,7 @@ vsp1@fe930000 { interrupts = ; clocks = <&cpg CPG_MOD 128>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 128>; }; vsp1@fe938000 { @@ -992,6 +1047,7 @@ vsp1@fe938000 { interrupts = ; clocks = <&cpg CPG_MOD 127>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 127>; }; du: display@feb00000 { @@ -1039,6 +1095,7 @@ can0: can@e6e80000 { <&can_clk>; clock-names = "clkp1", "clkp2", "can_clk"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 916>; status = "disabled"; }; @@ -1050,6 +1107,7 @@ can1: can@e6e88000 { <&can_clk>; clock-names = "clkp1", "clkp2", "can_clk"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 915>; status = "disabled"; }; @@ -1059,6 +1117,7 @@ jpu: jpeg-codec@fe980000 { interrupts = ; clocks = <&cpg CPG_MOD 106>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 106>; }; /* External root clock */ @@ -1154,6 +1213,7 @@ qspi: spi@e6b10000 { <&dmac1 0x17>, <&dmac1 0x18>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 917>; num-cs = <1>; #address-cells = <1>; #size-cells = <0>; @@ -1170,6 +1230,7 @@ msiof0: spi@e6e20000 { <&dmac1 0x51>, <&dmac1 0x52>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 0>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1185,6 +1246,7 @@ msiof1: spi@e6e10000 { <&dmac1 0x55>, <&dmac1 0x56>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 208>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1200,6 +1262,7 @@ msiof2: spi@e6e00000 { <&dmac1 0x41>, <&dmac1 0x42>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 205>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1215,6 +1278,7 @@ msiof3: spi@e6c90000 { <&dmac1 0x45>, <&dmac1 0x46>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 215>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1226,6 +1290,7 @@ xhci: usb@ee000000 { interrupts = ; clocks = <&cpg CPG_MOD 328>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 328>; phys = <&usb2 1>; phy-names = "usb"; status = "disabled"; @@ -1239,6 +1304,7 @@ pci0: pci@ee090000 { interrupts = ; clocks = <&cpg CPG_MOD 703>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 703>; status = "disabled"; bus-range = <0 0>; @@ -1272,6 +1338,7 @@ pci1: pci@ee0b0000 { interrupts = ; clocks = <&cpg CPG_MOD 703>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 703>; status = "disabled"; bus-range = <1 1>; @@ -1290,6 +1357,7 @@ pci2: pci@ee0d0000 { device_type = "pci"; clocks = <&cpg CPG_MOD 703>; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 703>; reg = <0 0xee0d0000 0 0xc00>, <0 0xee0c0000 0 0x1100>; interrupts = ; @@ -1341,6 +1409,7 @@ pciec: pcie@fe000000 { clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; clock-names = "pcie", "pcie_bus"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 319>; status = "disabled"; }; @@ -1385,6 +1454,13 @@ rcar_sound: sound@ec500000 { "dvc.0", "dvc.1", "clk_a", "clk_b", "clk_c", "clk_i"; power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 1005>, + <&cpg 1006>, <&cpg 1007>, <&cpg 1008>, <&cpg 1009>, + <&cpg 1010>, <&cpg 1011>, <&cpg 1012>, <&cpg 1013>, + <&cpg 1014>, <&cpg 1015>; + reset-names = "ssi-all", + "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5", + "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0"; status = "disabled"; From be5ae56e5f2d1f4eff1c2eca3d8e7d801085a6e2 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 11 Sep 2017 15:09:56 +0200 Subject: [PATCH 36/48] ARM: dts: r8a7791: Add reset control properties Add properties to describe the reset topology for on-SoC devices: - Add the "#reset-cells" property to the CPG/MSSR device node, - Add resets and reset-names properties to the various device nodes. This allows to reset SoC devices using the Reset Controller API. Note that resets usually match the corresponding module clocks. Exceptions are: - The audio module has resets for the Serial Sound Interfaces only, - The display module has only a single reset for all DU channels, but adding reset properties for the display is postponed. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7791.dtsi | 82 ++++++++++++++++++++++++++++++++++ 1 file changed, 82 insertions(+) diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi index e984b106dd1a..5a8a15847076 100644 --- a/arch/arm/boot/dts/r8a7791.dtsi +++ b/arch/arm/boot/dts/r8a7791.dtsi @@ -120,6 +120,7 @@ gic: interrupt-controller@f1001000 { clocks = <&cpg CPG_MOD 408>; clock-names = "clk"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 408>; }; gpio0: gpio@e6050000 { @@ -133,6 +134,7 @@ gpio0: gpio@e6050000 { interrupt-controller; clocks = <&cpg CPG_MOD 912>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 912>; }; gpio1: gpio@e6051000 { @@ -146,6 +148,7 @@ gpio1: gpio@e6051000 { interrupt-controller; clocks = <&cpg CPG_MOD 911>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 911>; }; gpio2: gpio@e6052000 { @@ -159,6 +162,7 @@ gpio2: gpio@e6052000 { interrupt-controller; clocks = <&cpg CPG_MOD 910>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 910>; }; gpio3: gpio@e6053000 { @@ -172,6 +176,7 @@ gpio3: gpio@e6053000 { interrupt-controller; clocks = <&cpg CPG_MOD 909>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 909>; }; gpio4: gpio@e6054000 { @@ -185,6 +190,7 @@ gpio4: gpio@e6054000 { interrupt-controller; clocks = <&cpg CPG_MOD 908>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 908>; }; gpio5: gpio@e6055000 { @@ -198,6 +204,7 @@ gpio5: gpio@e6055000 { interrupt-controller; clocks = <&cpg CPG_MOD 907>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 907>; }; gpio6: gpio@e6055400 { @@ -211,6 +218,7 @@ gpio6: gpio@e6055400 { interrupt-controller; clocks = <&cpg CPG_MOD 905>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 905>; }; gpio7: gpio@e6055800 { @@ -224,6 +232,7 @@ gpio7: gpio@e6055800 { interrupt-controller; clocks = <&cpg CPG_MOD 904>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 904>; }; thermal: thermal@e61f0000 { @@ -234,6 +243,7 @@ thermal: thermal@e61f0000 { interrupts = ; clocks = <&cpg CPG_MOD 522>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 522>; #thermal-sensor-cells = <0>; }; @@ -253,6 +263,7 @@ cmt0: timer@ffca0000 { clocks = <&cpg CPG_MOD 124>; clock-names = "fck"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 124>; renesas,channels-mask = <0x60>; @@ -273,6 +284,7 @@ cmt1: timer@e6130000 { clocks = <&cpg CPG_MOD 329>; clock-names = "fck"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 329>; renesas,channels-mask = <0xff>; @@ -296,6 +308,7 @@ irqc0: interrupt-controller@e61c0000 { ; clocks = <&cpg CPG_MOD 407>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 407>; }; dmac0: dma-controller@e6700000 { @@ -325,6 +338,7 @@ GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH clocks = <&cpg CPG_MOD 219>; clock-names = "fck"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 219>; #dma-cells = <1>; dma-channels = <15>; }; @@ -356,6 +370,7 @@ GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH clocks = <&cpg CPG_MOD 218>; clock-names = "fck"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 218>; #dma-cells = <1>; dma-channels = <15>; }; @@ -385,6 +400,7 @@ GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH clocks = <&cpg CPG_MOD 502>; clock-names = "fck"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 502>; #dma-cells = <1>; dma-channels = <13>; }; @@ -414,6 +430,7 @@ GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH clocks = <&cpg CPG_MOD 501>; clock-names = "fck"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 501>; #dma-cells = <1>; dma-channels = <13>; }; @@ -426,6 +443,7 @@ usb_dmac0: dma-controller@e65a0000 { interrupt-names = "ch0", "ch1"; clocks = <&cpg CPG_MOD 330>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 330>; #dma-cells = <1>; dma-channels = <2>; }; @@ -438,6 +456,7 @@ usb_dmac1: dma-controller@e65b0000 { interrupt-names = "ch0", "ch1"; clocks = <&cpg CPG_MOD 331>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 331>; #dma-cells = <1>; dma-channels = <2>; }; @@ -451,6 +470,7 @@ i2c0: i2c@e6508000 { interrupts = ; clocks = <&cpg CPG_MOD 931>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 931>; i2c-scl-internal-delay-ns = <6>; status = "disabled"; }; @@ -463,6 +483,7 @@ i2c1: i2c@e6518000 { interrupts = ; clocks = <&cpg CPG_MOD 930>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 930>; i2c-scl-internal-delay-ns = <6>; status = "disabled"; }; @@ -475,6 +496,7 @@ i2c2: i2c@e6530000 { interrupts = ; clocks = <&cpg CPG_MOD 929>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 929>; i2c-scl-internal-delay-ns = <6>; status = "disabled"; }; @@ -487,6 +509,7 @@ i2c3: i2c@e6540000 { interrupts = ; clocks = <&cpg CPG_MOD 928>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 928>; i2c-scl-internal-delay-ns = <6>; status = "disabled"; }; @@ -499,6 +522,7 @@ i2c4: i2c@e6520000 { interrupts = ; clocks = <&cpg CPG_MOD 927>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 927>; i2c-scl-internal-delay-ns = <6>; status = "disabled"; }; @@ -512,6 +536,7 @@ i2c5: i2c@e6528000 { interrupts = ; clocks = <&cpg CPG_MOD 925>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 925>; i2c-scl-internal-delay-ns = <110>; status = "disabled"; }; @@ -529,6 +554,7 @@ i2c6: i2c@e60b0000 { <&dmac1 0x77>, <&dmac1 0x78>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 926>; status = "disabled"; }; @@ -544,6 +570,7 @@ i2c7: i2c@e6500000 { <&dmac1 0x61>, <&dmac1 0x62>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 318>; status = "disabled"; }; @@ -559,6 +586,7 @@ i2c8: i2c@e6510000 { <&dmac1 0x65>, <&dmac1 0x66>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 323>; status = "disabled"; }; @@ -576,6 +604,7 @@ mmcif0: mmc@ee200000 { <&dmac1 0xd1>, <&dmac1 0xd2>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 315>; reg-io-width = <4>; status = "disabled"; max-frequency = <97500000>; @@ -591,6 +620,7 @@ sdhi0: sd@ee100000 { dma-names = "tx", "rx", "tx", "rx"; max-frequency = <195000000>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 314>; status = "disabled"; }; @@ -604,6 +634,7 @@ sdhi1: sd@ee140000 { dma-names = "tx", "rx", "tx", "rx"; max-frequency = <97500000>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 312>; status = "disabled"; }; @@ -617,6 +648,7 @@ sdhi2: sd@ee160000 { dma-names = "tx", "rx", "tx", "rx"; max-frequency = <97500000>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 311>; status = "disabled"; }; @@ -631,6 +663,7 @@ scifa0: serial@e6c40000 { <&dmac1 0x21>, <&dmac1 0x22>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 204>; status = "disabled"; }; @@ -645,6 +678,7 @@ scifa1: serial@e6c50000 { <&dmac1 0x25>, <&dmac1 0x26>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 203>; status = "disabled"; }; @@ -659,6 +693,7 @@ scifa2: serial@e6c60000 { <&dmac1 0x27>, <&dmac1 0x28>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 202>; status = "disabled"; }; @@ -673,6 +708,7 @@ scifa3: serial@e6c70000 { <&dmac1 0x1b>, <&dmac1 0x1c>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 1106>; status = "disabled"; }; @@ -687,6 +723,7 @@ scifa4: serial@e6c78000 { <&dmac1 0x1f>, <&dmac1 0x20>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 1107>; status = "disabled"; }; @@ -701,6 +738,7 @@ scifa5: serial@e6c80000 { <&dmac1 0x23>, <&dmac1 0x24>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 1108>; status = "disabled"; }; @@ -715,6 +753,7 @@ scifb0: serial@e6c20000 { <&dmac1 0x3d>, <&dmac1 0x3e>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 206>; status = "disabled"; }; @@ -729,6 +768,7 @@ scifb1: serial@e6c30000 { <&dmac1 0x19>, <&dmac1 0x1a>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 207>; status = "disabled"; }; @@ -743,6 +783,7 @@ scifb2: serial@e6ce0000 { <&dmac1 0x1d>, <&dmac1 0x1e>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 216>; status = "disabled"; }; @@ -758,6 +799,7 @@ scif0: serial@e6e60000 { <&dmac1 0x29>, <&dmac1 0x2a>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 721>; status = "disabled"; }; @@ -773,6 +815,7 @@ scif1: serial@e6e68000 { <&dmac1 0x2d>, <&dmac1 0x2e>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 720>; status = "disabled"; }; @@ -782,6 +825,7 @@ adc: adc@e6e54000 { clocks = <&cpg CPG_MOD 901>; clock-names = "fck"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 901>; status = "disabled"; }; @@ -797,6 +841,7 @@ scif2: serial@e6e58000 { <&dmac1 0x2b>, <&dmac1 0x2c>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 719>; status = "disabled"; }; @@ -812,6 +857,7 @@ scif3: serial@e6ea8000 { <&dmac1 0x2f>, <&dmac1 0x30>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 718>; status = "disabled"; }; @@ -827,6 +873,7 @@ scif4: serial@e6ee0000 { <&dmac1 0xfb>, <&dmac1 0xfc>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 715>; status = "disabled"; }; @@ -842,6 +889,7 @@ scif5: serial@e6ee8000 { <&dmac1 0xfd>, <&dmac1 0xfe>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 714>; status = "disabled"; }; @@ -857,6 +905,7 @@ hscif0: serial@e62c0000 { <&dmac1 0x39>, <&dmac1 0x3a>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 717>; status = "disabled"; }; @@ -872,6 +921,7 @@ hscif1: serial@e62c8000 { <&dmac1 0x4d>, <&dmac1 0x4e>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 716>; status = "disabled"; }; @@ -887,6 +937,7 @@ hscif2: serial@e62d0000 { <&dmac1 0x3b>, <&dmac1 0x3c>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 713>; status = "disabled"; }; @@ -914,6 +965,7 @@ ether: ethernet@ee700000 { interrupts = ; clocks = <&cpg CPG_MOD 813>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 813>; phy-mode = "rmii"; #address-cells = <1>; #size-cells = <0>; @@ -927,6 +979,7 @@ avb: ethernet@e6800000 { interrupts = ; clocks = <&cpg CPG_MOD 812>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 812>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -938,6 +991,7 @@ sata0: sata@ee300000 { interrupts = ; clocks = <&cpg CPG_MOD 815>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 815>; status = "disabled"; }; @@ -947,6 +1001,7 @@ sata1: sata@ee500000 { interrupts = ; clocks = <&cpg CPG_MOD 814>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 814>; status = "disabled"; }; @@ -959,6 +1014,7 @@ hsusb: usb@e6590000 { <&usb_dmac1 0>, <&usb_dmac1 1>; dma-names = "ch0", "ch1", "ch2", "ch3"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 704>; renesas,buswait = <4>; phys = <&usb0 1>; phy-names = "usb"; @@ -974,6 +1030,7 @@ usbphy: usb-phy@e6590100 { clocks = <&cpg CPG_MOD 704>; clock-names = "usbhs"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 704>; status = "disabled"; usb0: usb-channel@0 { @@ -992,6 +1049,7 @@ vin0: video@e6ef0000 { interrupts = ; clocks = <&cpg CPG_MOD 811>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 811>; status = "disabled"; }; @@ -1001,6 +1059,7 @@ vin1: video@e6ef1000 { interrupts = ; clocks = <&cpg CPG_MOD 810>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 810>; status = "disabled"; }; @@ -1010,6 +1069,7 @@ vin2: video@e6ef2000 { interrupts = ; clocks = <&cpg CPG_MOD 809>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 809>; status = "disabled"; }; @@ -1019,6 +1079,7 @@ vsp1@fe928000 { interrupts = ; clocks = <&cpg CPG_MOD 131>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 131>; }; vsp1@fe930000 { @@ -1027,6 +1088,7 @@ vsp1@fe930000 { interrupts = ; clocks = <&cpg CPG_MOD 128>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 128>; }; vsp1@fe938000 { @@ -1035,6 +1097,7 @@ vsp1@fe938000 { interrupts = ; clocks = <&cpg CPG_MOD 127>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 127>; }; du: display@feb00000 { @@ -1075,6 +1138,7 @@ can0: can@e6e80000 { <&can_clk>; clock-names = "clkp1", "clkp2", "can_clk"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 916>; status = "disabled"; }; @@ -1086,6 +1150,7 @@ can1: can@e6e88000 { <&can_clk>; clock-names = "clkp1", "clkp2", "can_clk"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 915>; status = "disabled"; }; @@ -1095,6 +1160,7 @@ jpu: jpeg-codec@fe980000 { interrupts = ; clocks = <&cpg CPG_MOD 106>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 106>; }; /* External root clock */ @@ -1163,6 +1229,7 @@ cpg: clock-controller@e6150000 { clock-names = "extal", "usb_extal"; #clock-cells = <2>; #power-domain-cells = <0>; + #reset-cells = <1>; }; rst: reset-controller@e6160000 { @@ -1190,6 +1257,7 @@ qspi: spi@e6b10000 { <&dmac1 0x17>, <&dmac1 0x18>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 917>; num-cs = <1>; #address-cells = <1>; #size-cells = <0>; @@ -1206,6 +1274,7 @@ msiof0: spi@e6e20000 { <&dmac1 0x51>, <&dmac1 0x52>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 0>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1221,6 +1290,7 @@ msiof1: spi@e6e10000 { <&dmac1 0x55>, <&dmac1 0x56>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 208>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1236,6 +1306,7 @@ msiof2: spi@e6e00000 { <&dmac1 0x41>, <&dmac1 0x42>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 205>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1247,6 +1318,7 @@ xhci: usb@ee000000 { interrupts = ; clocks = <&cpg CPG_MOD 328>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 328>; phys = <&usb2 1>; phy-names = "usb"; status = "disabled"; @@ -1260,6 +1332,7 @@ pci0: pci@ee090000 { interrupts = ; clocks = <&cpg CPG_MOD 703>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 703>; status = "disabled"; bus-range = <0 0>; @@ -1293,6 +1366,7 @@ pci1: pci@ee0d0000 { interrupts = ; clocks = <&cpg CPG_MOD 703>; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 703>; status = "disabled"; bus-range = <1 1>; @@ -1341,6 +1415,7 @@ pciec: pcie@fe000000 { clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; clock-names = "pcie", "pcie_bus"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 319>; status = "disabled"; }; @@ -1445,6 +1520,13 @@ rcar_sound: sound@ec500000 { "dvc.0", "dvc.1", "clk_a", "clk_b", "clk_c", "clk_i"; power-domains = <&sysc R8A7791_PD_ALWAYS_ON>; + resets = <&cpg 1005>, + <&cpg 1006>, <&cpg 1007>, <&cpg 1008>, <&cpg 1009>, + <&cpg 1010>, <&cpg 1011>, <&cpg 1012>, <&cpg 1013>, + <&cpg 1014>, <&cpg 1015>; + reset-names = "ssi-all", + "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5", + "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0"; status = "disabled"; From 6e11a322f1d7505d3a1db4ae26c6c0e46082f4ae Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 11 Sep 2017 15:09:57 +0200 Subject: [PATCH 37/48] ARM: dts: r8a7792: Add reset control properties Add properties to describe the reset topology for on-SoC devices: - Add the "#reset-cells" property to the CPG/MSSR device node, - Add resets and reset-names properties to the various device nodes. This allows to reset SoC devices using the Reset Controller API. Note that resets usually match the corresponding module clocks. Exceptions are: - The audio module has resets for the Serial Sound Interfaces only, but audio is not yet enabled in r8a7792.dtsi, - The display module has only a single reset for all DU channels, but adding reset properties for the display is postponed. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7792.dtsi | 45 ++++++++++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi index a209787d899a..c332f77ebb6b 100644 --- a/arch/arm/boot/dts/r8a7792.dtsi +++ b/arch/arm/boot/dts/r8a7792.dtsi @@ -95,6 +95,7 @@ gic: interrupt-controller@f1001000 { clocks = <&cpg CPG_MOD 408>; clock-names = "clk"; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 408>; }; irqc: interrupt-controller@e61c0000 { @@ -108,6 +109,7 @@ irqc: interrupt-controller@e61c0000 { ; clocks = <&cpg CPG_MOD 407>; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 407>; }; timer { @@ -155,6 +157,7 @@ gpio0: gpio@e6050000 { interrupt-controller; clocks = <&cpg CPG_MOD 912>; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 912>; }; gpio1: gpio@e6051000 { @@ -169,6 +172,7 @@ gpio1: gpio@e6051000 { interrupt-controller; clocks = <&cpg CPG_MOD 911>; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 911>; }; gpio2: gpio@e6052000 { @@ -183,6 +187,7 @@ gpio2: gpio@e6052000 { interrupt-controller; clocks = <&cpg CPG_MOD 910>; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 910>; }; gpio3: gpio@e6053000 { @@ -197,6 +202,7 @@ gpio3: gpio@e6053000 { interrupt-controller; clocks = <&cpg CPG_MOD 909>; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 909>; }; gpio4: gpio@e6054000 { @@ -211,6 +217,7 @@ gpio4: gpio@e6054000 { interrupt-controller; clocks = <&cpg CPG_MOD 908>; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 908>; }; gpio5: gpio@e6055000 { @@ -225,6 +232,7 @@ gpio5: gpio@e6055000 { interrupt-controller; clocks = <&cpg CPG_MOD 907>; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 907>; }; gpio6: gpio@e6055100 { @@ -239,6 +247,7 @@ gpio6: gpio@e6055100 { interrupt-controller; clocks = <&cpg CPG_MOD 905>; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 905>; }; gpio7: gpio@e6055200 { @@ -253,6 +262,7 @@ gpio7: gpio@e6055200 { interrupt-controller; clocks = <&cpg CPG_MOD 904>; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 904>; }; gpio8: gpio@e6055300 { @@ -267,6 +277,7 @@ gpio8: gpio@e6055300 { interrupt-controller; clocks = <&cpg CPG_MOD 921>; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 921>; }; gpio9: gpio@e6055400 { @@ -281,6 +292,7 @@ gpio9: gpio@e6055400 { interrupt-controller; clocks = <&cpg CPG_MOD 919>; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 919>; }; gpio10: gpio@e6055500 { @@ -295,6 +307,7 @@ gpio10: gpio@e6055500 { interrupt-controller; clocks = <&cpg CPG_MOD 914>; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 914>; }; gpio11: gpio@e6055600 { @@ -309,6 +322,7 @@ gpio11: gpio@e6055600 { interrupt-controller; clocks = <&cpg CPG_MOD 913>; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 913>; }; dmac0: dma-controller@e6700000 { @@ -339,6 +353,7 @@ GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH clocks = <&cpg CPG_MOD 219>; clock-names = "fck"; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 219>; #dma-cells = <1>; dma-channels = <15>; }; @@ -371,6 +386,7 @@ GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH clocks = <&cpg CPG_MOD 218>; clock-names = "fck"; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 218>; #dma-cells = <1>; dma-channels = <15>; }; @@ -387,6 +403,7 @@ scif0: serial@e6e60000 { <&dmac1 0x29>, <&dmac1 0x2a>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 721>; status = "disabled"; }; @@ -402,6 +419,7 @@ scif1: serial@e6e68000 { <&dmac1 0x2d>, <&dmac1 0x2e>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 720>; status = "disabled"; }; @@ -417,6 +435,7 @@ scif2: serial@e6e58000 { <&dmac1 0x2b>, <&dmac1 0x2c>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 719>; status = "disabled"; }; @@ -432,6 +451,7 @@ scif3: serial@e6ea8000 { <&dmac1 0x2f>, <&dmac1 0x30>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 718>; status = "disabled"; }; @@ -447,6 +467,7 @@ hscif0: serial@e62c0000 { <&dmac1 0x39>, <&dmac1 0x3a>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 717>; status = "disabled"; }; @@ -462,6 +483,7 @@ hscif1: serial@e62c8000 { <&dmac1 0x4d>, <&dmac1 0x4e>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 716>; status = "disabled"; }; @@ -492,6 +514,7 @@ sdhi0: sd@ee100000 { dma-names = "tx", "rx", "tx", "rx"; clocks = <&cpg CPG_MOD 314>; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 314>; status = "disabled"; }; @@ -502,6 +525,7 @@ jpu: jpeg-codec@fe980000 { interrupts = ; clocks = <&cpg CPG_MOD 106>; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 106>; }; avb: ethernet@e6800000 { @@ -511,6 +535,7 @@ avb: ethernet@e6800000 { interrupts = ; clocks = <&cpg CPG_MOD 812>; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 812>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -524,6 +549,7 @@ i2c0: i2c@e6508000 { interrupts = ; clocks = <&cpg CPG_MOD 931>; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 931>; i2c-scl-internal-delay-ns = <6>; #address-cells = <1>; #size-cells = <0>; @@ -537,6 +563,7 @@ i2c1: i2c@e6518000 { interrupts = ; clocks = <&cpg CPG_MOD 930>; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 930>; i2c-scl-internal-delay-ns = <6>; #address-cells = <1>; #size-cells = <0>; @@ -550,6 +577,7 @@ i2c2: i2c@e6530000 { interrupts = ; clocks = <&cpg CPG_MOD 929>; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 929>; i2c-scl-internal-delay-ns = <6>; #address-cells = <1>; #size-cells = <0>; @@ -563,6 +591,7 @@ i2c3: i2c@e6540000 { interrupts = ; clocks = <&cpg CPG_MOD 928>; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 928>; i2c-scl-internal-delay-ns = <6>; #address-cells = <1>; #size-cells = <0>; @@ -576,6 +605,7 @@ i2c4: i2c@e6520000 { interrupts = ; clocks = <&cpg CPG_MOD 927>; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 927>; i2c-scl-internal-delay-ns = <6>; #address-cells = <1>; #size-cells = <0>; @@ -589,6 +619,7 @@ i2c5: i2c@e6528000 { interrupts = ; clocks = <&cpg CPG_MOD 925>; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 925>; i2c-scl-internal-delay-ns = <110>; #address-cells = <1>; #size-cells = <0>; @@ -604,6 +635,7 @@ qspi: spi@e6b10000 { <&dmac1 0x17>, <&dmac1 0x18>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 917>; num-cs = <1>; #address-cells = <1>; #size-cells = <0>; @@ -620,6 +652,7 @@ msiof0: spi@e6e20000 { <&dmac1 0x51>, <&dmac1 0x52>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 000>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -635,6 +668,7 @@ msiof1: spi@e6e10000 { <&dmac1 0x55>, <&dmac1 0x56>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 208>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -677,6 +711,7 @@ can0: can@e6e80000 { <&cpg CPG_CORE R8A7792_CLK_RCAN>, <&can_clk>; clock-names = "clkp1", "clkp2", "can_clk"; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 916>; status = "disabled"; }; @@ -689,6 +724,7 @@ can1: can@e6e88000 { <&cpg CPG_CORE R8A7792_CLK_RCAN>, <&can_clk>; clock-names = "clkp1", "clkp2", "can_clk"; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 915>; status = "disabled"; }; @@ -699,6 +735,7 @@ vin0: video@e6ef0000 { interrupts = ; clocks = <&cpg CPG_MOD 811>; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 811>; status = "disabled"; }; @@ -709,6 +746,7 @@ vin1: video@e6ef1000 { interrupts = ; clocks = <&cpg CPG_MOD 810>; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 810>; status = "disabled"; }; @@ -719,6 +757,7 @@ vin2: video@e6ef2000 { interrupts = ; clocks = <&cpg CPG_MOD 809>; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 809>; status = "disabled"; }; @@ -729,6 +768,7 @@ vin3: video@e6ef3000 { interrupts = ; clocks = <&cpg CPG_MOD 808>; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 808>; status = "disabled"; }; @@ -739,6 +779,7 @@ vin4: video@e6ef4000 { interrupts = ; clocks = <&cpg CPG_MOD 805>; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 805>; status = "disabled"; }; @@ -749,6 +790,7 @@ vin5: video@e6ef5000 { interrupts = ; clocks = <&cpg CPG_MOD 804>; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 804>; status = "disabled"; }; @@ -758,6 +800,7 @@ vsp1@fe928000 { interrupts = ; clocks = <&cpg CPG_MOD 131>; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 131>; }; vsp1@fe930000 { @@ -766,6 +809,7 @@ vsp1@fe930000 { interrupts = ; clocks = <&cpg CPG_MOD 128>; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 128>; }; vsp1@fe938000 { @@ -774,6 +818,7 @@ vsp1@fe938000 { interrupts = ; clocks = <&cpg CPG_MOD 127>; power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; + resets = <&cpg 127>; }; cpg: clock-controller@e6150000 { From 84fb19e1d201ba862cf25995cdb7c061c9d938ea Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 11 Sep 2017 15:09:58 +0200 Subject: [PATCH 38/48] ARM: dts: r8a7793: Add reset control properties Add properties to describe the reset topology for on-SoC devices: - Add the "#reset-cells" property to the CPG/MSSR device node, - Add resets and reset-names properties to the various device nodes. This allows to reset SoC devices using the Reset Controller API. Note that resets usually match the corresponding module clocks. Exceptions are: - The audio module has resets for the Serial Sound Interfaces only, - The display module has only a single reset for all DU channels, but adding reset properties for the display is postponed. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7793.dtsi | 62 ++++++++++++++++++++++++++++++++++ 1 file changed, 62 insertions(+) diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi index d48b97c853cd..aa19b93494bf 100644 --- a/arch/arm/boot/dts/r8a7793.dtsi +++ b/arch/arm/boot/dts/r8a7793.dtsi @@ -111,6 +111,7 @@ gic: interrupt-controller@f1001000 { clocks = <&cpg CPG_MOD 408>; clock-names = "clk"; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 408>; }; gpio0: gpio@e6050000 { @@ -124,6 +125,7 @@ gpio0: gpio@e6050000 { interrupt-controller; clocks = <&cpg CPG_MOD 912>; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 912>; }; gpio1: gpio@e6051000 { @@ -137,6 +139,7 @@ gpio1: gpio@e6051000 { interrupt-controller; clocks = <&cpg CPG_MOD 911>; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 911>; }; gpio2: gpio@e6052000 { @@ -150,6 +153,7 @@ gpio2: gpio@e6052000 { interrupt-controller; clocks = <&cpg CPG_MOD 910>; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 910>; }; gpio3: gpio@e6053000 { @@ -163,6 +167,7 @@ gpio3: gpio@e6053000 { interrupt-controller; clocks = <&cpg CPG_MOD 909>; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 909>; }; gpio4: gpio@e6054000 { @@ -176,6 +181,7 @@ gpio4: gpio@e6054000 { interrupt-controller; clocks = <&cpg CPG_MOD 908>; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 908>; }; gpio5: gpio@e6055000 { @@ -189,6 +195,7 @@ gpio5: gpio@e6055000 { interrupt-controller; clocks = <&cpg CPG_MOD 907>; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 907>; }; gpio6: gpio@e6055400 { @@ -202,6 +209,7 @@ gpio6: gpio@e6055400 { interrupt-controller; clocks = <&cpg CPG_MOD 905>; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 905>; }; gpio7: gpio@e6055800 { @@ -215,6 +223,7 @@ gpio7: gpio@e6055800 { interrupt-controller; clocks = <&cpg CPG_MOD 904>; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 904>; }; thermal: thermal@e61f0000 { @@ -225,6 +234,7 @@ thermal: thermal@e61f0000 { interrupts = ; clocks = <&cpg CPG_MOD 522>; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 522>; #thermal-sensor-cells = <0>; }; @@ -244,6 +254,7 @@ cmt0: timer@ffca0000 { clocks = <&cpg CPG_MOD 124>; clock-names = "fck"; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 124>; renesas,channels-mask = <0x60>; @@ -264,6 +275,7 @@ cmt1: timer@e6130000 { clocks = <&cpg CPG_MOD 329>; clock-names = "fck"; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 329>; renesas,channels-mask = <0xff>; @@ -287,6 +299,7 @@ irqc0: interrupt-controller@e61c0000 { ; clocks = <&cpg CPG_MOD 407>; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 407>; }; dmac0: dma-controller@e6700000 { @@ -316,6 +329,7 @@ GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH clocks = <&cpg CPG_MOD 219>; clock-names = "fck"; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 219>; #dma-cells = <1>; dma-channels = <15>; }; @@ -347,6 +361,7 @@ GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH clocks = <&cpg CPG_MOD 218>; clock-names = "fck"; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 218>; #dma-cells = <1>; dma-channels = <15>; }; @@ -376,6 +391,7 @@ GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH clocks = <&cpg CPG_MOD 502>; clock-names = "fck"; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 502>; #dma-cells = <1>; dma-channels = <13>; }; @@ -405,6 +421,7 @@ GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH clocks = <&cpg CPG_MOD 501>; clock-names = "fck"; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 501>; #dma-cells = <1>; dma-channels = <13>; }; @@ -418,6 +435,7 @@ i2c0: i2c@e6508000 { interrupts = ; clocks = <&cpg CPG_MOD 931>; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 931>; i2c-scl-internal-delay-ns = <6>; status = "disabled"; }; @@ -430,6 +448,7 @@ i2c1: i2c@e6518000 { interrupts = ; clocks = <&cpg CPG_MOD 930>; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 930>; i2c-scl-internal-delay-ns = <6>; status = "disabled"; }; @@ -442,6 +461,7 @@ i2c2: i2c@e6530000 { interrupts = ; clocks = <&cpg CPG_MOD 929>; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 929>; i2c-scl-internal-delay-ns = <6>; status = "disabled"; }; @@ -454,6 +474,7 @@ i2c3: i2c@e6540000 { interrupts = ; clocks = <&cpg CPG_MOD 928>; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 928>; i2c-scl-internal-delay-ns = <6>; status = "disabled"; }; @@ -466,6 +487,7 @@ i2c4: i2c@e6520000 { interrupts = ; clocks = <&cpg CPG_MOD 927>; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 927>; i2c-scl-internal-delay-ns = <6>; status = "disabled"; }; @@ -479,6 +501,7 @@ i2c5: i2c@e6528000 { interrupts = ; clocks = <&cpg CPG_MOD 925>; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 925>; i2c-scl-internal-delay-ns = <110>; status = "disabled"; }; @@ -496,6 +519,7 @@ i2c6: i2c@e60b0000 { <&dmac1 0x77>, <&dmac1 0x78>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 926>; status = "disabled"; }; @@ -511,6 +535,7 @@ i2c7: i2c@e6500000 { <&dmac1 0x61>, <&dmac1 0x62>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 318>; status = "disabled"; }; @@ -526,6 +551,7 @@ i2c8: i2c@e6510000 { <&dmac1 0x65>, <&dmac1 0x66>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 323>; status = "disabled"; }; @@ -544,6 +570,7 @@ sdhi0: sd@ee100000 { dma-names = "tx", "rx", "tx", "rx"; max-frequency = <195000000>; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 314>; status = "disabled"; }; @@ -557,6 +584,7 @@ sdhi1: sd@ee140000 { dma-names = "tx", "rx", "tx", "rx"; max-frequency = <97500000>; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 312>; status = "disabled"; }; @@ -570,6 +598,7 @@ sdhi2: sd@ee160000 { dma-names = "tx", "rx", "tx", "rx"; max-frequency = <97500000>; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 311>; status = "disabled"; }; @@ -582,6 +611,7 @@ mmcif0: mmc@ee200000 { <&dmac1 0xd1>, <&dmac1 0xd2>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 315>; reg-io-width = <4>; status = "disabled"; max-frequency = <97500000>; @@ -598,6 +628,7 @@ scifa0: serial@e6c40000 { <&dmac1 0x21>, <&dmac1 0x22>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 204>; status = "disabled"; }; @@ -612,6 +643,7 @@ scifa1: serial@e6c50000 { <&dmac1 0x25>, <&dmac1 0x26>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 203>; status = "disabled"; }; @@ -626,6 +658,7 @@ scifa2: serial@e6c60000 { <&dmac1 0x27>, <&dmac1 0x28>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 202>; status = "disabled"; }; @@ -640,6 +673,7 @@ scifa3: serial@e6c70000 { <&dmac1 0x1b>, <&dmac1 0x1c>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 1106>; status = "disabled"; }; @@ -654,6 +688,7 @@ scifa4: serial@e6c78000 { <&dmac1 0x1f>, <&dmac1 0x20>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 1107>; status = "disabled"; }; @@ -668,6 +703,7 @@ scifa5: serial@e6c80000 { <&dmac1 0x23>, <&dmac1 0x24>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 1108>; status = "disabled"; }; @@ -682,6 +718,7 @@ scifb0: serial@e6c20000 { <&dmac1 0x3d>, <&dmac1 0x3e>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 206>; status = "disabled"; }; @@ -696,6 +733,7 @@ scifb1: serial@e6c30000 { <&dmac1 0x19>, <&dmac1 0x1a>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 207>; status = "disabled"; }; @@ -710,6 +748,7 @@ scifb2: serial@e6ce0000 { <&dmac1 0x1d>, <&dmac1 0x1e>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 216>; status = "disabled"; }; @@ -725,6 +764,7 @@ scif0: serial@e6e60000 { <&dmac1 0x29>, <&dmac1 0x2a>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 721>; status = "disabled"; }; @@ -740,6 +780,7 @@ scif1: serial@e6e68000 { <&dmac1 0x2d>, <&dmac1 0x2e>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 720>; status = "disabled"; }; @@ -755,6 +796,7 @@ scif2: serial@e6e58000 { <&dmac1 0x2b>, <&dmac1 0x2c>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 719>; status = "disabled"; }; @@ -770,6 +812,7 @@ scif3: serial@e6ea8000 { <&dmac1 0x2f>, <&dmac1 0x30>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 718>; status = "disabled"; }; @@ -785,6 +828,7 @@ scif4: serial@e6ee0000 { <&dmac1 0xfb>, <&dmac1 0xfc>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 715>; status = "disabled"; }; @@ -800,6 +844,7 @@ scif5: serial@e6ee8000 { <&dmac1 0xfd>, <&dmac1 0xfe>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 714>; status = "disabled"; }; @@ -815,6 +860,7 @@ hscif0: serial@e62c0000 { <&dmac1 0x39>, <&dmac1 0x3a>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 717>; status = "disabled"; }; @@ -830,6 +876,7 @@ hscif1: serial@e62c8000 { <&dmac1 0x4d>, <&dmac1 0x4e>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 716>; status = "disabled"; }; @@ -845,6 +892,7 @@ hscif2: serial@e62d0000 { <&dmac1 0x3b>, <&dmac1 0x3c>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 713>; status = "disabled"; }; @@ -872,6 +920,7 @@ ether: ethernet@ee700000 { interrupts = ; clocks = <&cpg CPG_MOD 813>; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 813>; phy-mode = "rmii"; #address-cells = <1>; #size-cells = <0>; @@ -884,6 +933,7 @@ vin0: video@e6ef0000 { interrupts = ; clocks = <&cpg CPG_MOD 811>; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 811>; status = "disabled"; }; @@ -893,6 +943,7 @@ vin1: video@e6ef1000 { interrupts = ; clocks = <&cpg CPG_MOD 810>; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 810>; status = "disabled"; }; @@ -902,6 +953,7 @@ vin2: video@e6ef2000 { interrupts = ; clocks = <&cpg CPG_MOD 809>; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 809>; status = "disabled"; }; @@ -914,6 +966,7 @@ qspi: spi@e6b10000 { <&dmac1 0x17>, <&dmac1 0x18>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 917>; num-cs = <1>; #address-cells = <1>; #size-cells = <0>; @@ -958,6 +1011,7 @@ can0: can@e6e80000 { <&can_clk>; clock-names = "clkp1", "clkp2", "can_clk"; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 916>; status = "disabled"; }; @@ -969,6 +1023,7 @@ can1: can@e6e88000 { <&can_clk>; clock-names = "clkp1", "clkp2", "can_clk"; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 915>; status = "disabled"; }; @@ -1147,6 +1202,13 @@ rcar_sound: sound@ec500000 { "dvc.0", "dvc.1", "clk_a", "clk_b", "clk_c", "clk_i"; power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; + resets = <&cpg 1005>, + <&cpg 1006>, <&cpg 1007>, <&cpg 1008>, <&cpg 1009>, + <&cpg 1010>, <&cpg 1011>, <&cpg 1012>, <&cpg 1013>, + <&cpg 1014>, <&cpg 1015>; + reset-names = "ssi-all", + "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5", + "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0"; status = "disabled"; From 615beb759ca494a4b1a202f571af41549064dc2f Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Mon, 11 Sep 2017 15:09:59 +0200 Subject: [PATCH 39/48] ARM: dts: r8a7794: Add reset control properties Add properties to describe the reset topology for on-SoC devices: - Add the "#reset-cells" property to the CPG/MSSR device node, - Add resets and reset-names properties to the various device nodes. This allows to reset SoC devices using the Reset Controller API. Note that resets usually match the corresponding module clocks. Exceptions are: - The audio module has resets for the Serial Sound Interfaces only, - The display module has only a single reset for all DU channels, but adding reset properties for the display is postponed. Signed-off-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7794.dtsi | 64 ++++++++++++++++++++++++++++++++++ 1 file changed, 64 insertions(+) diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi index a4c35d29f77c..035c33715b65 100644 --- a/arch/arm/boot/dts/r8a7794.dtsi +++ b/arch/arm/boot/dts/r8a7794.dtsi @@ -78,6 +78,7 @@ gic: interrupt-controller@f1001000 { clocks = <&cpg CPG_MOD 408>; clock-names = "clk"; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 408>; }; gpio0: gpio@e6050000 { @@ -91,6 +92,7 @@ gpio0: gpio@e6050000 { interrupt-controller; clocks = <&cpg CPG_MOD 912>; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 912>; }; gpio1: gpio@e6051000 { @@ -104,6 +106,7 @@ gpio1: gpio@e6051000 { interrupt-controller; clocks = <&cpg CPG_MOD 911>; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 911>; }; gpio2: gpio@e6052000 { @@ -117,6 +120,7 @@ gpio2: gpio@e6052000 { interrupt-controller; clocks = <&cpg CPG_MOD 910>; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 910>; }; gpio3: gpio@e6053000 { @@ -130,6 +134,7 @@ gpio3: gpio@e6053000 { interrupt-controller; clocks = <&cpg CPG_MOD 909>; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 909>; }; gpio4: gpio@e6054000 { @@ -143,6 +148,7 @@ gpio4: gpio@e6054000 { interrupt-controller; clocks = <&cpg CPG_MOD 908>; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 908>; }; gpio5: gpio@e6055000 { @@ -156,6 +162,7 @@ gpio5: gpio@e6055000 { interrupt-controller; clocks = <&cpg CPG_MOD 907>; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 907>; }; gpio6: gpio@e6055400 { @@ -169,6 +176,7 @@ gpio6: gpio@e6055400 { interrupt-controller; clocks = <&cpg CPG_MOD 905>; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 905>; }; cmt0: timer@ffca0000 { @@ -179,6 +187,7 @@ cmt0: timer@ffca0000 { clocks = <&cpg CPG_MOD 124>; clock-names = "fck"; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 124>; renesas,channels-mask = <0x60>; @@ -199,6 +208,7 @@ cmt1: timer@e6130000 { clocks = <&cpg CPG_MOD 329>; clock-names = "fck"; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 329>; renesas,channels-mask = <0xff>; @@ -230,6 +240,7 @@ irqc0: interrupt-controller@e61c0000 { ; clocks = <&cpg CPG_MOD 407>; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 407>; }; pfc: pin-controller@e6060000 { @@ -264,6 +275,7 @@ GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH clocks = <&cpg CPG_MOD 219>; clock-names = "fck"; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 219>; #dma-cells = <1>; dma-channels = <15>; }; @@ -295,6 +307,7 @@ GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH clocks = <&cpg CPG_MOD 218>; clock-names = "fck"; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 218>; #dma-cells = <1>; dma-channels = <15>; }; @@ -323,6 +336,7 @@ GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH clocks = <&cpg CPG_MOD 502>; clock-names = "fck"; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 502>; #dma-cells = <1>; dma-channels = <13>; }; @@ -338,6 +352,7 @@ scifa0: serial@e6c40000 { <&dmac1 0x21>, <&dmac1 0x22>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 204>; status = "disabled"; }; @@ -352,6 +367,7 @@ scifa1: serial@e6c50000 { <&dmac1 0x25>, <&dmac1 0x26>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 203>; status = "disabled"; }; @@ -366,6 +382,7 @@ scifa2: serial@e6c60000 { <&dmac1 0x27>, <&dmac1 0x28>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 202>; status = "disabled"; }; @@ -380,6 +397,7 @@ scifa3: serial@e6c70000 { <&dmac1 0x1b>, <&dmac1 0x1c>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 1106>; status = "disabled"; }; @@ -394,6 +412,7 @@ scifa4: serial@e6c78000 { <&dmac1 0x1f>, <&dmac1 0x20>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 1107>; status = "disabled"; }; @@ -408,6 +427,7 @@ scifa5: serial@e6c80000 { <&dmac1 0x23>, <&dmac1 0x24>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 1108>; status = "disabled"; }; @@ -422,6 +442,7 @@ scifb0: serial@e6c20000 { <&dmac1 0x3d>, <&dmac1 0x3e>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 206>; status = "disabled"; }; @@ -436,6 +457,7 @@ scifb1: serial@e6c30000 { <&dmac1 0x19>, <&dmac1 0x1a>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 207>; status = "disabled"; }; @@ -450,6 +472,7 @@ scifb2: serial@e6ce0000 { <&dmac1 0x1d>, <&dmac1 0x1e>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 216>; status = "disabled"; }; @@ -465,6 +488,7 @@ scif0: serial@e6e60000 { <&dmac1 0x29>, <&dmac1 0x2a>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 721>; status = "disabled"; }; @@ -480,6 +504,7 @@ scif1: serial@e6e68000 { <&dmac1 0x2d>, <&dmac1 0x2e>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 720>; status = "disabled"; }; @@ -495,6 +520,7 @@ scif2: serial@e6e58000 { <&dmac1 0x2b>, <&dmac1 0x2c>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 719>; status = "disabled"; }; @@ -510,6 +536,7 @@ scif3: serial@e6ea8000 { <&dmac1 0x2f>, <&dmac1 0x30>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 718>; status = "disabled"; }; @@ -525,6 +552,7 @@ scif4: serial@e6ee0000 { <&dmac1 0xfb>, <&dmac1 0xfc>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 715>; status = "disabled"; }; @@ -540,6 +568,7 @@ scif5: serial@e6ee8000 { <&dmac1 0xfd>, <&dmac1 0xfe>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 714>; status = "disabled"; }; @@ -555,6 +584,7 @@ hscif0: serial@e62c0000 { <&dmac1 0x39>, <&dmac1 0x3a>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 717>; status = "disabled"; }; @@ -570,6 +600,7 @@ hscif1: serial@e62c8000 { <&dmac1 0x4d>, <&dmac1 0x4e>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 716>; status = "disabled"; }; @@ -585,6 +616,7 @@ hscif2: serial@e62d0000 { <&dmac1 0x3b>, <&dmac1 0x3c>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 713>; status = "disabled"; }; @@ -612,6 +644,7 @@ ether: ethernet@ee700000 { interrupts = ; clocks = <&cpg CPG_MOD 813>; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 813>; phy-mode = "rmii"; #address-cells = <1>; #size-cells = <0>; @@ -625,6 +658,7 @@ avb: ethernet@e6800000 { interrupts = ; clocks = <&cpg CPG_MOD 812>; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 812>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -637,6 +671,7 @@ i2c0: i2c@e6508000 { interrupts = ; clocks = <&cpg CPG_MOD 931>; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 931>; #address-cells = <1>; #size-cells = <0>; i2c-scl-internal-delay-ns = <6>; @@ -649,6 +684,7 @@ i2c1: i2c@e6518000 { interrupts = ; clocks = <&cpg CPG_MOD 930>; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 930>; #address-cells = <1>; #size-cells = <0>; i2c-scl-internal-delay-ns = <6>; @@ -661,6 +697,7 @@ i2c2: i2c@e6530000 { interrupts = ; clocks = <&cpg CPG_MOD 929>; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 929>; #address-cells = <1>; #size-cells = <0>; i2c-scl-internal-delay-ns = <6>; @@ -673,6 +710,7 @@ i2c3: i2c@e6540000 { interrupts = ; clocks = <&cpg CPG_MOD 928>; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 928>; #address-cells = <1>; #size-cells = <0>; i2c-scl-internal-delay-ns = <6>; @@ -685,6 +723,7 @@ i2c4: i2c@e6520000 { interrupts = ; clocks = <&cpg CPG_MOD 927>; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 927>; #address-cells = <1>; #size-cells = <0>; i2c-scl-internal-delay-ns = <6>; @@ -697,6 +736,7 @@ i2c5: i2c@e6528000 { interrupts = ; clocks = <&cpg CPG_MOD 925>; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 925>; #address-cells = <1>; #size-cells = <0>; i2c-scl-internal-delay-ns = <6>; @@ -713,6 +753,7 @@ i2c6: i2c@e6500000 { <&dmac1 0x61>, <&dmac1 0x62>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 318>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -728,6 +769,7 @@ i2c7: i2c@e6510000 { <&dmac1 0x65>, <&dmac1 0x66>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 323>; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -742,6 +784,7 @@ mmcif0: mmc@ee200000 { <&dmac1 0xd1>, <&dmac1 0xd2>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 315>; reg-io-width = <4>; status = "disabled"; }; @@ -756,6 +799,7 @@ sdhi0: sd@ee100000 { dma-names = "tx", "rx", "tx", "rx"; max-frequency = <195000000>; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 314>; status = "disabled"; }; @@ -769,6 +813,7 @@ sdhi1: sd@ee140000 { dma-names = "tx", "rx", "tx", "rx"; max-frequency = <97500000>; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 312>; status = "disabled"; }; @@ -782,6 +827,7 @@ sdhi2: sd@ee160000 { dma-names = "tx", "rx", "tx", "rx"; max-frequency = <97500000>; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 311>; status = "disabled"; }; @@ -794,6 +840,7 @@ qspi: spi@e6b10000 { <&dmac1 0x17>, <&dmac1 0x18>; dma-names = "tx", "rx", "tx", "rx"; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 917>; num-cs = <1>; #address-cells = <1>; #size-cells = <0>; @@ -806,6 +853,7 @@ vin0: video@e6ef0000 { interrupts = ; clocks = <&cpg CPG_MOD 811>; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 811>; status = "disabled"; }; @@ -815,6 +863,7 @@ vin1: video@e6ef1000 { interrupts = ; clocks = <&cpg CPG_MOD 810>; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 810>; status = "disabled"; }; @@ -826,6 +875,7 @@ pci0: pci@ee090000 { interrupts = ; clocks = <&cpg CPG_MOD 703>; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 703>; status = "disabled"; bus-range = <0 0>; @@ -859,6 +909,7 @@ pci1: pci@ee0d0000 { interrupts = ; clocks = <&cpg CPG_MOD 703>; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 703>; status = "disabled"; bus-range = <1 1>; @@ -890,6 +941,7 @@ hsusb: usb@e6590000 { interrupts = ; clocks = <&cpg CPG_MOD 704>; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 704>; renesas,buswait = <4>; phys = <&usb0 1>; phy-names = "usb"; @@ -905,6 +957,7 @@ usbphy: usb-phy@e6590100 { clocks = <&cpg CPG_MOD 704>; clock-names = "usbhs"; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 704>; status = "disabled"; usb0: usb-channel@0 { @@ -923,6 +976,7 @@ vsp1@fe928000 { interrupts = ; clocks = <&cpg CPG_MOD 131>; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 131>; }; vsp1@fe930000 { @@ -931,6 +985,7 @@ vsp1@fe930000 { interrupts = ; clocks = <&cpg CPG_MOD 128>; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 128>; }; du: display@feb00000 { @@ -968,6 +1023,7 @@ can0: can@e6e80000 { <&can_clk>; clock-names = "clkp1", "clkp2", "can_clk"; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 916>; status = "disabled"; }; @@ -979,6 +1035,7 @@ can1: can@e6e88000 { <&can_clk>; clock-names = "clkp1", "clkp2", "can_clk"; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 915>; status = "disabled"; }; @@ -1151,6 +1208,13 @@ rcar_sound: sound@ec500000 { "dvc.0", "dvc.1", "clk_a", "clk_b", "clk_c", "clk_i"; power-domains = <&sysc R8A7794_PD_ALWAYS_ON>; + resets = <&cpg 1005>, + <&cpg 1006>, <&cpg 1007>, <&cpg 1008>, <&cpg 1009>, + <&cpg 1010>, <&cpg 1011>, <&cpg 1012>, <&cpg 1013>, + <&cpg 1014>, <&cpg 1015>; + reset-names = "ssi-all", + "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5", + "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0"; status = "disabled"; From 7079131ef9b934df48602b22e30282d25a6a4827 Mon Sep 17 00:00:00 2001 From: Fabrizio Castro Date: Wed, 13 Sep 2017 18:05:35 +0100 Subject: [PATCH 40/48] ARM: dts: r8a7745: Add SDHI controllers Add the SDHI controllers to the r8a7745 device tree. Signed-off-by: Fabrizio Castro Signed-off-by: Chris Paterson Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7745.dtsi | 42 ++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi index 6e82991b7997..adf30890cb07 100644 --- a/arch/arm/boot/dts/r8a7745.dtsi +++ b/arch/arm/boot/dts/r8a7745.dtsi @@ -735,6 +735,48 @@ mmcif0: mmc@ee200000 { max-frequency = <97500000>; status = "disabled"; }; + + sdhi0: sd@ee100000 { + compatible = "renesas,sdhi-r8a7745"; + reg = <0 0xee100000 0 0x328>; + interrupts = ; + clocks = <&cpg CPG_MOD 314>; + dmas = <&dmac0 0xcd>, <&dmac0 0xce>, + <&dmac1 0xcd>, <&dmac1 0xce>; + dma-names = "tx", "rx", "tx", "rx"; + max-frequency = <195000000>; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 314>; + status = "disabled"; + }; + + sdhi1: sd@ee140000 { + compatible = "renesas,sdhi-r8a7745"; + reg = <0 0xee140000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 312>; + dmas = <&dmac0 0xc1>, <&dmac0 0xc2>, + <&dmac1 0xc1>, <&dmac1 0xc2>; + dma-names = "tx", "rx", "tx", "rx"; + max-frequency = <97500000>; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 312>; + status = "disabled"; + }; + + sdhi2: sd@ee160000 { + compatible = "renesas,sdhi-r8a7745"; + reg = <0 0xee160000 0 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 311>; + dmas = <&dmac0 0xd3>, <&dmac0 0xd4>, + <&dmac1 0xd3>, <&dmac1 0xd4>; + dma-names = "tx", "rx", "tx", "rx"; + max-frequency = <97500000>; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + resets = <&cpg 311>; + status = "disabled"; + }; }; /* External root clock */ From 599114ee21057040c058043fdc1367878350d5e4 Mon Sep 17 00:00:00 2001 From: Fabrizio Castro Date: Wed, 13 Sep 2017 18:05:36 +0100 Subject: [PATCH 41/48] ARM: dts: iwg22m: Enable SDHI1 controller Enable the SDHI1 controller on iWave RZ/G1E SoM. Signed-off-by: Fabrizio Castro Signed-off-by: Chris Paterson Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7745-iwg22m.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm/boot/dts/r8a7745-iwg22m.dtsi b/arch/arm/boot/dts/r8a7745-iwg22m.dtsi index e306e7c5b644..f7f9ceff35a6 100644 --- a/arch/arm/boot/dts/r8a7745-iwg22m.dtsi +++ b/arch/arm/boot/dts/r8a7745-iwg22m.dtsi @@ -9,6 +9,7 @@ */ #include "r8a7745.dtsi" +#include / { compatible = "iwave,g22m", "renesas,r8a7745"; @@ -38,6 +39,12 @@ mmcif0_pins: mmc { function = "mmc"; }; + sdhi1_pins: sd1 { + groups = "sdhi1_data4", "sdhi1_ctrl"; + function = "sdhi1"; + power-source = <3300>; + }; + i2c3_pins: i2c3 { groups = "i2c3_b"; function = "i2c3"; @@ -54,6 +61,16 @@ &mmcif0 { status = "okay"; }; +&sdhi1 { + pinctrl-0 = <&sdhi1_pins>; + pinctrl-names = "default"; + + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_3p3v>; + cd-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + &i2c3 { pinctrl-0 = <&i2c3_pins>; pinctrl-names = "default"; From 450c03718e971880ae067dc5f94a86f961acd6c3 Mon Sep 17 00:00:00 2001 From: Fabrizio Castro Date: Wed, 13 Sep 2017 18:05:38 +0100 Subject: [PATCH 42/48] ARM: dts: r8a7743: Add QSPI support Add the DT node for the QSPI interface to the SoC dtsi. Signed-off-by: Fabrizio Castro Signed-off-by: Chris Paterson Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7743.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi index 266c5eca9f74..454f98060d6f 100644 --- a/arch/arm/boot/dts/r8a7743.dtsi +++ b/arch/arm/boot/dts/r8a7743.dtsi @@ -28,6 +28,7 @@ aliases { i2c6 = &iic0; i2c7 = &iic1; i2c8 = &iic3; + spi0 = &qspi; }; cpus { @@ -835,6 +836,22 @@ mmcif0: mmc@ee200000 { status = "disabled"; }; + qspi: spi@e6b10000 { + compatible = "renesas,qspi-r8a7743", "renesas,qspi"; + reg = <0 0xe6b10000 0 0x2c>; + interrupts = ; + clocks = <&cpg CPG_MOD 917>; + dmas = <&dmac0 0x17>, <&dmac0 0x18>, + <&dmac1 0x17>, <&dmac1 0x18>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + resets = <&cpg 917>; + status = "disabled"; + }; + sdhi0: sd@ee100000 { compatible = "renesas,sdhi-r8a7743"; reg = <0 0xee100000 0 0x328>; From 781e923a5fe4751d3aaa740ca3de0f9d179c34ef Mon Sep 17 00:00:00 2001 From: Fabrizio Castro Date: Wed, 13 Sep 2017 18:05:39 +0100 Subject: [PATCH 43/48] ARM: dts: iwg20m: Add SPI NOR support Add support for the SPI NOR device used to boot up the system to the System on Module DT. Signed-off-by: Fabrizio Castro Signed-off-by: Chris Paterson Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7743-iwg20m.dtsi | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm/boot/dts/r8a7743-iwg20m.dtsi b/arch/arm/boot/dts/r8a7743-iwg20m.dtsi index 4119737cb883..75a8ca571846 100644 --- a/arch/arm/boot/dts/r8a7743-iwg20m.dtsi +++ b/arch/arm/boot/dts/r8a7743-iwg20m.dtsi @@ -44,6 +44,11 @@ mmcif0_pins: mmc { function = "mmc"; }; + qspi_pins: qspi { + groups = "qspi_ctrl", "qspi_data2"; + function = "qspi"; + }; + sdhi0_pins: sd0 { groups = "sdhi0_data4", "sdhi0_ctrl"; function = "sdhi0"; @@ -61,6 +66,27 @@ &mmcif0 { status = "okay"; }; +&qspi { + pinctrl-0 = <&qspi_pins>; + pinctrl-names = "default"; + + status = "okay"; + + /* WARNING - This device contains the bootloader. Handle with care. */ + flash: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "sst,sst25vf016b", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <50000000>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <1>; + m25p,fast-read; + spi-cpol; + spi-cpha; + }; +}; + &sdhi0 { pinctrl-0 = <&sdhi0_pins>; pinctrl-names = "default"; From 2391d0269a85c3a7942cb7e2bbac5751a7191e10 Mon Sep 17 00:00:00 2001 From: Fabrizio Castro Date: Wed, 13 Sep 2017 18:05:40 +0100 Subject: [PATCH 44/48] ARM: dts: r8a7745: Add QSPI support Add the DT node for the QSPI interface to the SoC dtsi. Signed-off-by: Fabrizio Castro Signed-off-by: Chris Paterson Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7745.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi index adf30890cb07..5cc4009c4265 100644 --- a/arch/arm/boot/dts/r8a7745.dtsi +++ b/arch/arm/boot/dts/r8a7745.dtsi @@ -25,6 +25,7 @@ aliases { i2c3 = &i2c3; i2c4 = &i2c4; i2c5 = &i2c5; + spi0 = &qspi; }; cpus { @@ -736,6 +737,22 @@ mmcif0: mmc@ee200000 { status = "disabled"; }; + qspi: spi@e6b10000 { + compatible = "renesas,qspi-r8a7745", "renesas,qspi"; + reg = <0 0xe6b10000 0 0x2c>; + interrupts = ; + clocks = <&cpg CPG_MOD 917>; + dmas = <&dmac0 0x17>, <&dmac0 0x18>, + <&dmac1 0x17>, <&dmac1 0x18>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + num-cs = <1>; + #address-cells = <1>; + #size-cells = <0>; + resets = <&cpg 917>; + status = "disabled"; + }; + sdhi0: sd@ee100000 { compatible = "renesas,sdhi-r8a7745"; reg = <0 0xee100000 0 0x328>; From cf1cc6f1da41ceb60f6389b6b46f4f6dc06a2b63 Mon Sep 17 00:00:00 2001 From: Fabrizio Castro Date: Wed, 13 Sep 2017 18:05:41 +0100 Subject: [PATCH 45/48] ARM: dts: iwg22m: Add SPI NOR support Add support for the SPI NOR device used to boot up the system to the System on Module DT. Signed-off-by: Fabrizio Castro Signed-off-by: Chris Paterson Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7745-iwg22m.dtsi | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm/boot/dts/r8a7745-iwg22m.dtsi b/arch/arm/boot/dts/r8a7745-iwg22m.dtsi index f7f9ceff35a6..ed9a8cf3fe36 100644 --- a/arch/arm/boot/dts/r8a7745-iwg22m.dtsi +++ b/arch/arm/boot/dts/r8a7745-iwg22m.dtsi @@ -39,6 +39,11 @@ mmcif0_pins: mmc { function = "mmc"; }; + qspi_pins: qspi { + groups = "qspi_ctrl", "qspi_data2"; + function = "qspi"; + }; + sdhi1_pins: sd1 { groups = "sdhi1_data4", "sdhi1_ctrl"; function = "sdhi1"; @@ -61,6 +66,27 @@ &mmcif0 { status = "okay"; }; +&qspi { + pinctrl-0 = <&qspi_pins>; + pinctrl-names = "default"; + + status = "okay"; + + /* WARNING - This device contains the bootloader. Handle with care. */ + flash: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "sst,sst25vf016b", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <50000000>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <1>; + m25p,fast-read; + spi-cpol; + spi-cpha; + }; +}; + &sdhi1 { pinctrl-0 = <&sdhi1_pins>; pinctrl-names = "default"; From ec301d261d5a5a71f2ba1baf7a852b220fe69f3c Mon Sep 17 00:00:00 2001 From: Fabrizio Castro Date: Fri, 22 Sep 2017 14:01:02 +0100 Subject: [PATCH 46/48] ARM: dts: iwg22d: Enable SDHI0 controller Enable the SDHI0 controller on iWave RZ/G1E carrier board. Signed-off-by: Fabrizio Castro Signed-off-by: Chris Paterson Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts | 29 +++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts b/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts index aac84c67a31d..8772c561e3a8 100644 --- a/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts +++ b/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts @@ -24,6 +24,19 @@ chosen { bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp"; stdout-path = "serial0:115200n8"; }; + + vccq_sdhi0: regulator-vccq-sdhi0 { + compatible = "regulator-gpio"; + + regulator-name = "SDHI0 VccQ"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + + gpios = <&gpio0 20 GPIO_ACTIVE_LOW>; + gpios-states = <1>; + states = <3300000 1 + 1800000 0>; + }; }; &pfc { @@ -36,6 +49,12 @@ avb_pins: avb { groups = "avb_mdio", "avb_gmii"; function = "avb"; }; + + sdhi0_pins: sd0 { + groups = "sdhi0_data4", "sdhi0_ctrl"; + function = "sdhi0"; + power-source = <3300>; + }; }; &scif4 { @@ -63,3 +82,13 @@ phy3: ethernet-phy@3 { micrel,led-mode = <1>; }; }; + +&sdhi0 { + pinctrl-0 = <&sdhi0_pins>; + pinctrl-names = "default"; + + vmmc-supply = <®_3p3v>; + vqmmc-supply = <&vccq_sdhi0>; + cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>; + status = "okay"; +}; From e527649c320062f53d8437d1a49b3ed4fccf7750 Mon Sep 17 00:00:00 2001 From: Fabrizio Castro Date: Wed, 27 Sep 2017 10:57:05 +0100 Subject: [PATCH 47/48] ARM: dts: r8a7745: Add MSIOF[012] support Add the DT nodes needed by MSIOF[012] interfaces to the SoC dtsi. Also, define aliases for spi[123]. Signed-off-by: Fabrizio Castro Signed-off-by: Chris Paterson Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7745.dtsi | 51 ++++++++++++++++++++++++++++++++++ 1 file changed, 51 insertions(+) diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi index 5cc4009c4265..6ba3b8b04edb 100644 --- a/arch/arm/boot/dts/r8a7745.dtsi +++ b/arch/arm/boot/dts/r8a7745.dtsi @@ -26,6 +26,9 @@ aliases { i2c4 = &i2c4; i2c5 = &i2c5; spi0 = &qspi; + spi1 = &msiof0; + spi2 = &msiof1; + spi3 = &msiof2; }; cpus { @@ -753,6 +756,54 @@ qspi: spi@e6b10000 { status = "disabled"; }; + msiof0: spi@e6e20000 { + compatible = "renesas,msiof-r8a7745", + "renesas,rcar-gen2-msiof"; + reg = <0 0xe6e20000 0 0x0064>; + interrupts = ; + clocks = <&cpg CPG_MOD 000>; + dmas = <&dmac0 0x51>, <&dmac0 0x52>, + <&dmac1 0x51>, <&dmac1 0x52>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + #address-cells = <1>; + #size-cells = <0>; + resets = <&cpg 000>; + status = "disabled"; + }; + + msiof1: spi@e6e10000 { + compatible = "renesas,msiof-r8a7745", + "renesas,rcar-gen2-msiof"; + reg = <0 0xe6e10000 0 0x0064>; + interrupts = ; + clocks = <&cpg CPG_MOD 208>; + dmas = <&dmac0 0x55>, <&dmac0 0x56>, + <&dmac1 0x55>, <&dmac1 0x56>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + #address-cells = <1>; + #size-cells = <0>; + resets = <&cpg 208>; + status = "disabled"; + }; + + msiof2: spi@e6e00000 { + compatible = "renesas,msiof-r8a7745", + "renesas,rcar-gen2-msiof"; + reg = <0 0xe6e00000 0 0x0064>; + interrupts = ; + clocks = <&cpg CPG_MOD 205>; + dmas = <&dmac0 0x41>, <&dmac0 0x42>, + <&dmac1 0x41>, <&dmac1 0x42>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7745_PD_ALWAYS_ON>; + #address-cells = <1>; + #size-cells = <0>; + resets = <&cpg 205>; + status = "disabled"; + }; + sdhi0: sd@ee100000 { compatible = "renesas,sdhi-r8a7745"; reg = <0 0xee100000 0 0x328>; From 7031a219f649d12acda8a70a4b6b816ee123c8e2 Mon Sep 17 00:00:00 2001 From: Fabrizio Castro Date: Wed, 27 Sep 2017 10:57:04 +0100 Subject: [PATCH 48/48] ARM: dts: r8a7743: Add MSIOF[012] support Add the DT nodes needed by MSIOF[012] interfaces to the SoC dtsi. Also, define aliases for spi[123]. Signed-off-by: Fabrizio Castro Signed-off-by: Chris Paterson Reviewed-by: Geert Uytterhoeven Signed-off-by: Simon Horman --- arch/arm/boot/dts/r8a7743.dtsi | 51 ++++++++++++++++++++++++++++++++++ 1 file changed, 51 insertions(+) diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi index 454f98060d6f..d541fd9ffafb 100644 --- a/arch/arm/boot/dts/r8a7743.dtsi +++ b/arch/arm/boot/dts/r8a7743.dtsi @@ -29,6 +29,9 @@ aliases { i2c7 = &iic1; i2c8 = &iic3; spi0 = &qspi; + spi1 = &msiof0; + spi2 = &msiof1; + spi3 = &msiof2; }; cpus { @@ -852,6 +855,54 @@ qspi: spi@e6b10000 { status = "disabled"; }; + msiof0: spi@e6e20000 { + compatible = "renesas,msiof-r8a7743", + "renesas,rcar-gen2-msiof"; + reg = <0 0xe6e20000 0 0x0064>; + interrupts = ; + clocks = <&cpg CPG_MOD 000>; + dmas = <&dmac0 0x51>, <&dmac0 0x52>, + <&dmac1 0x51>, <&dmac1 0x52>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + #address-cells = <1>; + #size-cells = <0>; + resets = <&cpg 000>; + status = "disabled"; + }; + + msiof1: spi@e6e10000 { + compatible = "renesas,msiof-r8a7743", + "renesas,rcar-gen2-msiof"; + reg = <0 0xe6e10000 0 0x0064>; + interrupts = ; + clocks = <&cpg CPG_MOD 208>; + dmas = <&dmac0 0x55>, <&dmac0 0x56>, + <&dmac1 0x55>, <&dmac1 0x56>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + #address-cells = <1>; + #size-cells = <0>; + resets = <&cpg 208>; + status = "disabled"; + }; + + msiof2: spi@e6e00000 { + compatible = "renesas,msiof-r8a7743", + "renesas,rcar-gen2-msiof"; + reg = <0 0xe6e00000 0 0x0064>; + interrupts = ; + clocks = <&cpg CPG_MOD 205>; + dmas = <&dmac0 0x41>, <&dmac0 0x42>, + <&dmac1 0x41>, <&dmac1 0x42>; + dma-names = "tx", "rx", "tx", "rx"; + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; + #address-cells = <1>; + #size-cells = <0>; + resets = <&cpg 205>; + status = "disabled"; + }; + sdhi0: sd@ee100000 { compatible = "renesas,sdhi-r8a7743"; reg = <0 0xee100000 0 0x328>;