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arm64: dts: mediatek: mt8195: add MUTEX configuration for VPPSYS

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In MT8195, the MMSYS has two Video Processor Pipepline Subsystems
named VPPSYS0 and VPPSYS1, each with specific MUTEX to control
Start of Frame(SOF) and End of Frame (EOF) signals.
Before working with them, the addresses, interrupts, clocks and power
domains need to be set up in dts.

Signed-off-by: Moudy Ho <moudy.ho@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Tested-by: Chen-Yu Tsai <wenst@chromium.org>
Link: https://lore.kernel.org/r/20230206091109.1324-4-moudy.ho@mediatek.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
This commit is contained in:
Moudy Ho
2023-02-06 17:11:06 +08:00
committed by Matthias Brugger
parent 981f808e64
commit 018f1d4fa4
1 changed files with 18 additions and 0 deletions
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18
arch/arm64/boot/dts/mediatek/mt8195.dtsi
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@@ -1801,6 +1801,15 @@ vppsys0: syscon@14000000 {
#clock-cells = <1>;
};
mutex@1400f000 {
compatible = "mediatek,mt8195-vpp-mutex";
reg = <0 0x1400f000 0 0x1000>;
interrupts = <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH 0>;
mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xf000 0x1000>;
clocks = <&vppsys0 CLK_VPP0_MUTEX>;
power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
};
smi_sub_common_vpp0_vpp1_2x1: smi@14010000 {
compatible = "mediatek,mt8195-smi-sub-common";
reg = <0 0x14010000 0 0x1000>;
@@ -1906,6 +1915,15 @@ vppsys1: syscon@14f00000 {
#clock-cells = <1>;
};
mutex@14f01000 {
compatible = "mediatek,mt8195-vpp-mutex";
reg = <0 0x14f01000 0 0x1000>;
interrupts = <GIC_SPI 635 IRQ_TYPE_LEVEL_HIGH 0>;
mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x1000 0x1000>;
clocks = <&vppsys1 CLK_VPP1_DISP_MUTEX>;
power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
};
larb5: larb@14f02000 {
compatible = "mediatek,mt8195-smi-larb";
reg = <0 0x14f02000 0 0x1000>;