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As per RZ/G2L HW(Rev.0.50) manual, clock monitor register value
0 means clock is not supplied and 1 means clock is supplied.
This patch fixes the issue by removing the inverted logic.
Fixing the above, triggered following 2 issues
1) GIC interrupts don't work if we disable IA55_CLK and DMAC_ACLK.
Fixed this issue by adding these clocks as critical clocks.
2) DMA is not working, since the DMA driver is not turning on DMAC_PCLK.
So will provide a fix in the DMA driver to turn on DMA_PCLK.
Fixes: ef3c613ccd ("clk: renesas: Add CPG core wrapper for RZ/G2L SoC")
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20210922112405.26413-2-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Linux kernel
============
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There are various text files in the Documentation/ subdirectory,
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Please read the Documentation/process/changes.rst file, as it contains the
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